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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-328085cf8ccsm14314451fa.99.2025.05.18.03.55.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 May 2025 03:55:42 -0700 (PDT) From: Dmitry Baryshkov Date: Sun, 18 May 2025 13:55:28 +0300 Subject: [PATCH v3 10/11] drm/msm: enable separate binding of GPU and display devices Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250518-msm-gpu-split-v3-10-0e91e8e77023@oss.qualcomm.com> References: <20250518-msm-gpu-split-v3-0-0e91e8e77023@oss.qualcomm.com> In-Reply-To: <20250518-msm-gpu-split-v3-0-0e91e8e77023@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5220; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=c8ydcyDO/BqF2oOo3z5sqYBctAmcpc0ltuKnWJ+WQEo=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoKbyaRdSB02zKvPq4UwWXD+YF8pWpYeFOkXSUG J9PpnJZKuaJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaCm8mgAKCRCLPIo+Aiko 1RomCACPGsiSyB0yMMNsAQd0cnrf7rjgX6ZBJQBPS3cnk8zgBqIZlIRB5Kb55ZVapPEYxSX588S jKsiWCV+7NjviMSGSGZeSW5TBUI7dYOwsBQe/ooY/LdZ8/3T5ou/vvmV1hEZxDGsMjQpXKRfiIf nPuud3RgQll7DR63tfifpCR0YhUdfTthgox1l4S+1ESPO3F+8+YYcXobo2cSoJ+s40WwWpoUGAt jkAT2RTTAqND1MWBJQyoco3Lrv8MU0tyXxGlgqEFGR/rapd8271EJG05BGFhClirwtmPjl1MfbT UKkLbOerb6zvSFbH0odrT1cpPcdJgH6ZOeS2TgKJuVmaVhkD X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: 2B4LAExTiXx_SWVtKhCySXHQN-HpLQfW X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE4MDEwNCBTYWx0ZWRfX5L7dk/gAlFxl tBehPOOvYUEMfY6WgtWwYibcYMA1vLk7w9UdDM9jI45x694MElNR6QQP36NTRqoRC0VwBo/PQrR FHD3ors5ckMSKQ0ovBAd+ImKZ2buD+89jXtlUx6oXCetS7wYtAjGceXXyaxdidK3BYSMzthybTu 4BIBq2z/qmZZXupA73hhIqQ+LLPOWwLl28xs5S/wbQW1e6LxvwUnBAmeY+a1DUSB22AAuJzqn9I VeuGQNdkQwfV+UwrGYVxJjgyE+mELhxgN9cNx3oNkuJpV+TmghQjeHLbrNVKJQqcoglVqfA8Pus vkqs8dyuX+Cit+kTOwpuioO4CaxfehEpjeHIOjSQnbyIn8Xb5gu6P7PwKcyGDlxygCqoxXH6rpr 7og7p1cemjarPH5lvNOhP+ZBNd0snUNxqBKVvEfekJ3RNjxblb4J7EQMlCHBajyAfD4p9ZA6 X-Authority-Analysis: v=2.4 cv=CKkqXQrD c=1 sm=1 tr=0 ts=6829bcb1 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=d3EbUlffPpwbv2rupc8A:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 X-Proofpoint-GUID: 2B4LAExTiXx_SWVtKhCySXHQN-HpLQfW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-18_05,2025-05-16_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 mlxscore=0 mlxlogscore=999 suspectscore=0 spamscore=0 adultscore=0 impostorscore=0 phishscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505180104 There are cases when we want to have separate DRM devices for GPU and display pipelines. One example is development, when it is beneficial to be able to bind the GPU driver separately, without the display pipeline (and without the hacks adding "amd,imageon" to the compatible string). Another example is some of Qualcomm platforms, which have two MDSS units, but only one GPU. With current approach it is next to impossible to support this usecase properly, while separate binding allows users to have three DRM devices: two for MDSS units and a single headless GPU. Add kernel param msm.separate_gpu_drm, which if set to true forces creation of separate display and GPU DRM devices. Mesa supports this setup by using the kmsro wrapper. The param is disabled by default, in order to be able to test userspace for the compatibility issues. Simple clients are able to handle this setup automatically. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/adreno_device.c | 3 +- drivers/gpu/drm/msm/msm_drv.c | 47 ++++++++++++++++++++++++++= +--- drivers/gpu/drm/msm/msm_drv.h | 2 ++ 3 files changed, 47 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/m= sm/adreno/adreno_device.c index 574bc452f3df539cc8e03e161043b310d83c624f..142c321b57692649cfb8f2fc3b0= ff3b4a6012c1c 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -247,7 +247,8 @@ static const struct component_ops a3xx_ops =3D { =20 static int adreno_probe(struct platform_device *pdev) { - if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon")) + if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon") || + msm_gpu_no_components()) return msm_gpu_probe(pdev, &a3xx_ops); =20 return component_add(&pdev->dev, &a3xx_ops); diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 804b594ba1e7df9d9aec53a9be1451f1167fc77a..45953affccc73c622a805a13990= 2ebedcdf38b86 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -59,9 +59,18 @@ static bool modeset =3D true; MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=3Don (default),= 0=3Ddisable)"); module_param(modeset, bool, 0600); =20 +static bool separate_gpu_drm; +MODULE_PARM_DESC(separate_gpu_drm, "Use separate DRM device for the GPU (0= =3Dsingle DRM device for both GPU and display (default), 1=3Dtwo DRM device= s)"); +module_param(separate_gpu_drm, bool, 0400); + DECLARE_FAULT_ATTR(fail_gem_alloc); DECLARE_FAULT_ATTR(fail_gem_iova); =20 +bool msm_gpu_no_components(void) +{ + return separate_gpu_drm; +} + static int msm_drm_uninit(struct device *dev, const struct component_ops *= gpu_ops) { struct platform_device *pdev =3D to_platform_device(dev); @@ -898,6 +907,30 @@ static const struct drm_driver msm_driver =3D { .patchlevel =3D MSM_VERSION_PATCHLEVEL, }; =20 +static const struct drm_driver msm_kms_driver =3D { + .driver_features =3D DRIVER_GEM | + DRIVER_ATOMIC | + DRIVER_MODESET, + .open =3D msm_open, + .postclose =3D msm_postclose, + .dumb_create =3D msm_gem_dumb_create, + .dumb_map_offset =3D msm_gem_dumb_map_offset, + .gem_prime_import_sg_table =3D msm_gem_prime_import_sg_table, +#ifdef CONFIG_DEBUG_FS + .debugfs_init =3D msm_debugfs_init, +#endif + MSM_FBDEV_DRIVER_OPS, + .show_fdinfo =3D msm_show_fdinfo, + .ioctls =3D msm_ioctls, + .num_ioctls =3D ARRAY_SIZE(msm_ioctls), + .fops =3D &fops, + .name =3D "msm-kms", + .desc =3D "MSM Snapdragon DRM", + .major =3D MSM_VERSION_MAJOR, + .minor =3D MSM_VERSION_MINOR, + .patchlevel =3D MSM_VERSION_PATCHLEVEL, +}; + static const struct drm_driver msm_gpu_driver =3D { .driver_features =3D DRIVER_GEM | DRIVER_RENDER | @@ -1044,7 +1077,11 @@ static int add_gpu_components(struct device *dev, =20 static int msm_drm_bind(struct device *dev) { - return msm_drm_init(dev, &msm_driver, NULL); + return msm_drm_init(dev, + msm_gpu_no_components() ? + &msm_kms_driver : + &msm_driver, + NULL); } =20 static void msm_drm_unbind(struct device *dev) @@ -1080,9 +1117,11 @@ int msm_drv_probe(struct device *master_dev, return ret; } =20 - ret =3D add_gpu_components(master_dev, &match); - if (ret) - return ret; + if (!msm_gpu_no_components()) { + ret =3D add_gpu_components(master_dev, &match); + if (ret) + return ret; + } =20 /* on all devices that I am aware of, iommu's which can map * any address the cpu can see are used: diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index e7d8715bc61ccdee822bc6a1a0b0bbe7c8ff3552..1ff799f0c78133e73c6857e3692= c2dca2c5e60fa 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -543,4 +543,6 @@ void msm_kms_shutdown(struct platform_device *pdev); =20 bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver); =20 +bool msm_gpu_no_components(void); + #endif /* __MSM_DRV_H__ */ --=20 2.39.5