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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-328085cf8ccsm14314451fa.99.2025.05.18.03.55.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 May 2025 03:55:24 -0700 (PDT) From: Dmitry Baryshkov Date: Sun, 18 May 2025 13:55:19 +0300 Subject: [PATCH v3 01/11] drm/msm: move wq handling to KMS code Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250518-msm-gpu-split-v3-1-0e91e8e77023@oss.qualcomm.com> References: <20250518-msm-gpu-split-v3-0-0e91e8e77023@oss.qualcomm.com> In-Reply-To: <20250518-msm-gpu-split-v3-0-0e91e8e77023@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7139; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=zJfl99w8gPUfrdwYMYw+1yKgLUvglxsypWiv2LeoqZ8=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoKbyZa2rYnl2nhExspdmC9BS7VsDmJ1JWaTAsK ccOyKBqJn6JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaCm8mQAKCRCLPIo+Aiko 1avvB/oCplnUwEGLIc7F3z3QnZAbryimLiMtzlRC4ZxS0Ms5oEiYu7uLSsk194PIV5ddITjOOFR lfRHFmSgBKUWut+hnhvSw9WcewVxsIaKAeKbuNX7HtAUN6P1eavS0Tolzgfh3eXdhE/zCNi5AIY 8+K9cHSraqUODdc8/Emv03KlU7ASh+CVF4fN9X29LgWN3M6Xp2YZcw3MEwnCb34KOigtjvxVPw4 SJqHFuzKkzUKNVy89vfYZu4xgAQBWzL1Ci3edBsySaY8l4IkaSNOFvBoKrZAr4WBQqujvLEKW+2 krOa8+AfyInJpwoQc59C+/xbVjakh7yuqvl5wDgP/tNWR++k X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Authority-Analysis: v=2.4 cv=dIimmPZb c=1 sm=1 tr=0 ts=6829bc9f cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=lygNIV2IR02mpmLRnqcA:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 X-Proofpoint-ORIG-GUID: MVaxCbiuMwgoEtPKn057LmnuPxmWp7Qp X-Proofpoint-GUID: MVaxCbiuMwgoEtPKn057LmnuPxmWp7Qp X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE4MDEwNCBTYWx0ZWRfXw/Q1naxFiwuz qhb7gQ4XM40A7Q6qx6i7j6m1nhlkVHY5gdOJFEL9NNAO62Sa9MB/jzkhIGUZ3G4pnLiYokTuczJ gkpYRFtlF+iFFlrtTRGTPl4NLEoZCD9lV/osw/D2AjtXprMsWIx6raYTMuc7JkrDbehLtHaX0D2 njcK/yeVNLTmUV7TXaavIWW6mA1wUJwNVo4R4VFW0plX+eV0sPh1IBdqBpm4xrV3sxqul7OP5PY SJNGj4e83irS1zuetSxhKhFDKw7/dPzjMSGy1NQwxaGze7reIHq460OB1/yb9mmvmkirpxARpmW egTC0FTJM4R/zOdEVkUFnkRFPwXAR+i+iluxAbbxgVhmv47DFTn77c9mrX2k2kMVNPYYBZ6d9h5 iJwDVlUe/ksVHkrl6qg4set51CG+Fd+wIW+beC0ln3OUd4+lcMoFNP7et+Jg8U/FZCxjN7yh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-18_05,2025-05-16_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxscore=0 bulkscore=0 malwarescore=0 suspectscore=0 impostorscore=0 clxscore=1015 phishscore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505180104 The global workqueue is only used for vblanks inside KMS code. Move allocation / flushing / deallcation of it to msm_kms.c Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +- drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 2 +- drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 2 +- drivers/gpu/drm/msm/msm_drv.c | 21 ++------------------- drivers/gpu/drm/msm/msm_drv.h | 2 -- drivers/gpu/drm/msm/msm_kms.c | 11 +++++++++-- drivers/gpu/drm/msm/msm_kms.h | 8 ++++++++ 7 files changed, 22 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index f9c46180b8f7ace9122e74015244334c1f13ef2b..1aaed1cd9ec58fed3230acda4c2= 83f0eedf3a9f0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -980,7 +980,7 @@ static int dpu_encoder_resource_control(struct drm_enco= der *drm_enc, return 0; } =20 - queue_delayed_work(priv->wq, &dpu_enc->delayed_off_work, + queue_delayed_work(priv->kms->wq, &dpu_enc->delayed_off_work, msecs_to_jiffies(dpu_enc->idle_timeout)); =20 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c b/drivers/gpu/drm/ms= m/disp/mdp4/mdp4_crtc.c index b8610aa806eaeb540e76a6a17283faea6f482a99..5e1e62256c382426f70d21a5312= fb40dda68d695 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c @@ -511,7 +511,7 @@ static void mdp4_crtc_vblank_irq(struct mdp_irq *irq, u= int32_t irqstatus) =20 if (pending & PENDING_CURSOR) { update_cursor(crtc); - drm_flip_work_commit(&mdp4_crtc->unref_cursor_work, priv->wq); + drm_flip_work_commit(&mdp4_crtc->unref_cursor_work, priv->kms->wq); } } =20 diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/ms= m/disp/mdp5/mdp5_crtc.c index 0f653e62b4a008e3bafe09ee7fb4399e1fccb722..fce2365753e22850e56521e82b9= d9dca29c09280 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c @@ -1196,7 +1196,7 @@ static void mdp5_crtc_vblank_irq(struct mdp_irq *irq,= uint32_t irqstatus) } =20 if (pending & PENDING_CURSOR) - drm_flip_work_commit(&mdp5_crtc->unref_cursor_work, priv->wq); + drm_flip_work_commit(&mdp5_crtc->unref_cursor_work, priv->kms->wq); } =20 static void mdp5_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus) diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index f316e6776f672e7a97268f716040d0cf73256c4b..78cea9d4999488648b4131a2da4= 25fb349d1b664 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -82,13 +82,6 @@ static int msm_drm_uninit(struct device *dev) drm_atomic_helper_shutdown(ddev); } =20 - /* We must cancel and cleanup any pending vblank enable/disable - * work before msm_irq_uninstall() to avoid work re-enabling an - * irq after uninstall has disabled it. - */ - - flush_workqueue(priv->wq); - msm_gem_shrinker_cleanup(ddev); =20 msm_perf_debugfs_cleanup(priv); @@ -104,8 +97,6 @@ static int msm_drm_uninit(struct device *dev) ddev->dev_private =3D NULL; drm_dev_put(ddev); =20 - destroy_workqueue(priv->wq); - return 0; } =20 @@ -227,12 +218,6 @@ static int msm_drm_init(struct device *dev, const stru= ct drm_driver *drv) ddev->dev_private =3D priv; priv->dev =3D ddev; =20 - priv->wq =3D alloc_ordered_workqueue("msm", 0); - if (!priv->wq) { - ret =3D -ENOMEM; - goto err_put_dev; - } - INIT_LIST_HEAD(&priv->objects); mutex_init(&priv->obj_lock); =20 @@ -253,12 +238,12 @@ static int msm_drm_init(struct device *dev, const str= uct drm_driver *drv) if (priv->kms_init) { ret =3D drmm_mode_config_init(ddev); if (ret) - goto err_destroy_wq; + goto err_put_dev; } =20 ret =3D msm_init_vram(ddev); if (ret) - goto err_destroy_wq; + goto err_put_dev; =20 dma_set_max_seg_size(dev, UINT_MAX); =20 @@ -304,8 +289,6 @@ static int msm_drm_init(struct device *dev, const struc= t drm_driver *drv) =20 err_deinit_vram: msm_deinit_vram(ddev); -err_destroy_wq: - destroy_workqueue(priv->wq); err_put_dev: drm_dev_put(ddev); =20 diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index a65077855201746c37ee742364b61116565f3794..cc603bd4729e909e9381a3c277d= b262b13361de6 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -177,8 +177,6 @@ struct msm_drm_private { struct mutex lock; } lru; =20 - struct workqueue_struct *wq; - unsigned int num_crtcs; =20 struct msm_drm_thread event_thread[MAX_CRTCS]; diff --git a/drivers/gpu/drm/msm/msm_kms.c b/drivers/gpu/drm/msm/msm_kms.c index 35d5397e73b4c5cb90b1770e8570277e782be7ec..184a4503fef0deff7234a3ce332= e0bf564fbce46 100644 --- a/drivers/gpu/drm/msm/msm_kms.c +++ b/drivers/gpu/drm/msm/msm_kms.c @@ -137,7 +137,7 @@ static int vblank_ctrl_queue_work(struct msm_drm_privat= e *priv, vbl_work->enable =3D enable; vbl_work->priv =3D priv; =20 - queue_work(priv->wq, &vbl_work->work); + queue_work(priv->kms->wq, &vbl_work->work); =20 return 0; } @@ -227,6 +227,13 @@ void msm_drm_kms_uninit(struct device *dev) =20 BUG_ON(!kms); =20 + /* We must cancel and cleanup any pending vblank enable/disable + * work before msm_irq_uninstall() to avoid work re-enabling an + * irq after uninstall has disabled it. + */ + + flush_workqueue(kms->wq); + /* clean up event worker threads */ for (i =3D 0; i < priv->num_crtcs; i++) { if (priv->event_thread[i].worker) @@ -261,7 +268,7 @@ int msm_drm_kms_init(struct device *dev, const struct d= rm_driver *drv) ret =3D priv->kms_init(ddev); if (ret) { DRM_DEV_ERROR(dev, "failed to load kms\n"); - return ret; + goto err_msm_uninit; } =20 /* Enable normalization of plane zpos */ diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h index 43b58d052ee6aae0ce34d09c88e1e1c34f9c52ef..e52649bbee7dc6a80abfecf7f8d= 5bcfad3d8f60b 100644 --- a/drivers/gpu/drm/msm/msm_kms.h +++ b/drivers/gpu/drm/msm/msm_kms.h @@ -153,6 +153,8 @@ struct msm_kms { struct mutex commit_lock[MAX_CRTCS]; unsigned pending_crtc_mask; struct msm_pending_timer pending_timers[MAX_CRTCS]; + + struct workqueue_struct *wq; }; =20 static inline int msm_kms_init(struct msm_kms *kms, @@ -165,6 +167,10 @@ static inline int msm_kms_init(struct msm_kms *kms, =20 kms->funcs =3D funcs; =20 + kms->wq =3D alloc_ordered_workqueue("msm", 0); + if (!kms->wq) + return -ENOMEM; + for (i =3D 0; i < ARRAY_SIZE(kms->pending_timers); i++) { ret =3D msm_atomic_init_pending_timer(&kms->pending_timers[i], kms, i); if (ret) { @@ -181,6 +187,8 @@ static inline void msm_kms_destroy(struct msm_kms *kms) =20 for (i =3D 0; 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Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_drv.c | 9 +++------ drivers/gpu/drm/msm/msm_kms.c | 20 ++++++++++++++++++++ drivers/gpu/drm/msm/msm_kms.h | 2 ++ 3 files changed, 25 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 78cea9d4999488648b4131a2da425fb349d1b664..2c6997c85fbbc3767315ca3a166= a99b322f1218a 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -11,7 +11,6 @@ #include #include =20 -#include #include #include #include @@ -79,7 +78,7 @@ static int msm_drm_uninit(struct device *dev) if (ddev->registered) { drm_dev_unregister(ddev); if (priv->kms) - drm_atomic_helper_shutdown(ddev); + msm_drm_kms_unregister(dev); } =20 msm_gem_shrinker_cleanup(ddev); @@ -275,10 +274,8 @@ static int msm_drm_init(struct device *dev, const stru= ct drm_driver *drv) if (ret) goto err_msm_uninit; =20 - if (priv->kms_init) { - drm_kms_helper_poll_init(ddev); - drm_client_setup(ddev, NULL); - } + if (priv->kms_init) + msm_drm_kms_post_init(dev); =20 return 0; =20 diff --git a/drivers/gpu/drm/msm/msm_kms.c b/drivers/gpu/drm/msm/msm_kms.c index 184a4503fef0deff7234a3ce332e0bf564fbce46..49a56873100b2fdcded3eb6adcc= 7032bf404212c 100644 --- a/drivers/gpu/drm/msm/msm_kms.c +++ b/drivers/gpu/drm/msm/msm_kms.c @@ -13,6 +13,7 @@ #include #include #include +#include =20 #include "disp/msm_disp_snapshot.h" #include "msm_drv.h" @@ -217,6 +218,15 @@ struct msm_gem_address_space *msm_kms_init_aspace(stru= ct drm_device *dev) return aspace; } =20 +void msm_drm_kms_unregister(struct device *dev) +{ + struct platform_device *pdev =3D to_platform_device(dev); + struct msm_drm_private *priv =3D platform_get_drvdata(pdev); + struct drm_device *ddev =3D priv->dev; + + drm_atomic_helper_shutdown(ddev); +} + void msm_drm_kms_uninit(struct device *dev) { struct platform_device *pdev =3D to_platform_device(dev); @@ -366,3 +376,13 @@ void msm_kms_shutdown(struct platform_device *pdev) if (drm && drm->registered && priv->kms) drm_atomic_helper_shutdown(drm); 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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-328085cf8ccsm14314451fa.99.2025.05.18.03.55.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 May 2025 03:55:28 -0700 (PDT) From: Dmitry Baryshkov Date: Sun, 18 May 2025 13:55:21 +0300 Subject: [PATCH v3 03/11] drm/msm/mdp4: get rid of mdp4_crtc.id Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250518-msm-gpu-split-v3-3-0e91e8e77023@oss.qualcomm.com> References: <20250518-msm-gpu-split-v3-0-0e91e8e77023@oss.qualcomm.com> In-Reply-To: <20250518-msm-gpu-split-v3-0-0e91e8e77023@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3130; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=npSuxvWMmhzKLh8mAO06E84f1kOeMHWURDV7gpjmnuQ=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoKbyZ9AeY7obsJ4wix1fDb2P5WNV2DJztH7KUX 3sUn48fmuSJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaCm8mQAKCRCLPIo+Aiko 1YPGCACN8kXmecU+jG3vEQvTISfrFHslcPAcRaXFPhbbi4VHPcFPFd/CUJ/AH9rrZnpVoBDZy6V 1PVdYXdiazunhHd8l+Q+3DK0QPU3kMNS7CQWosLuWXXsk+mo5dZDEZ1KEee4yOFgZhp/wah9ghu /pNvAk4d7lrD/lYKjbjsyIBNPDkTPHdmS84bFJmCl1Us5guAjcT0Nev6LbOl095c/43foQOEUhk BCkAL6TS7XGsy5N6W9lb7lQG1n/f038edX+/tL13aSCY9xS8+K2sIzLP/rdwzJb0lSlEyncAhaa 2jjXKhtiP5QnmxP+LTFc0s5aIZLqn+wQfTqgjpyhyYUH7ely X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: htQv1g8tOemSnFvC9DLS5to7xq4V5FtN X-Authority-Analysis: v=2.4 cv=C4bpyRP+ c=1 sm=1 tr=0 ts=6829bca2 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=JeS6effYNUkig2QXyjUA:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 X-Proofpoint-GUID: htQv1g8tOemSnFvC9DLS5to7xq4V5FtN X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE4MDEwNCBTYWx0ZWRfX89WzwkcJPgPL AmK70oaiKSpQ8VUZyfnOjvBF6aQplNkAK5IC2Pgzklih/+9usI78PT/hLSFctlBT3lFFgc2Cd36 Qtxrww09Txrh/OLOb2Vywd93+aeE64gG34Vy1kLYFRxJTZ2UScj5i5gkjGMwhy+INVZSMpqTy5c xJhIrL9qXzsZjcRoMlOlh0iy8+GAmDWbkibhWnMtTmCTnrzexjLfhNHdGBu6Z2h/L9+b5rVY4LF oVCkv80z2fufXETR3gUxDuPmGGwAOD99FYimqZjpduesUJ/6ZchGOPRUi25MubMVxyPsvklXr/A HpauEnbG4Fh/3UqUhl9+9lnWQaooCywQlX8Kd/rvAnbxtO0nE+6TQGtk0UsRQR0z7KJLGw4h5uw MfT/fEhPveuy7+/W0bkz3mFkIk5lAtKYCwl2vHE7+n9B1bq1r/iqkXCt/0fXzpe6vsQfrJ1P X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-18_05,2025-05-16_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 impostorscore=0 adultscore=0 mlxlogscore=998 spamscore=0 lowpriorityscore=0 phishscore=0 mlxscore=0 bulkscore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505180104 There is no reason to store CRTC id, it's a part of the drm_crtc. Drop this member and use drm_crtc.name for the warning message. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 7 ++----- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 2 +- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h | 2 +- 3 files changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c b/drivers/gpu/drm/ms= m/disp/mdp4/mdp4_crtc.c index 5e1e62256c382426f70d21a5312fb40dda68d695..7596b45e234bdcf1b7cf37c4a8d= 39862f48819a8 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c @@ -17,7 +17,6 @@ struct mdp4_crtc { struct drm_crtc base; char name[8]; - int id; int ovlp; enum mdp4_dma dma; bool enabled; @@ -539,7 +538,7 @@ static void mdp4_crtc_wait_for_flush_done(struct drm_cr= tc *crtc) mdp4_crtc->flushed_mask), msecs_to_jiffies(50)); if (ret <=3D 0) - dev_warn(dev->dev, "vblank time out, crtc=3D%d\n", mdp4_crtc->id); + dev_warn(dev->dev, "vblank time out, crtc=3D%s\n", mdp4_crtc->base.name); =20 mdp4_crtc->flushed_mask =3D 0; =20 @@ -624,7 +623,7 @@ static void mdp4_crtc_flip_cleanup(struct drm_device *d= ev, void *ptr) =20 /* initialize crtc */ struct drm_crtc *mdp4_crtc_init(struct drm_device *dev, - struct drm_plane *plane, int id, int ovlp_id, + struct drm_plane *plane, int ovlp_id, enum mdp4_dma dma_id) { struct drm_crtc *crtc =3D NULL; @@ -639,8 +638,6 @@ struct drm_crtc *mdp4_crtc_init(struct drm_device *dev, =20 crtc =3D &mdp4_crtc->base; =20 - mdp4_crtc->id =3D id; - mdp4_crtc->ovlp =3D ovlp_id; mdp4_crtc->dma =3D dma_id; =20 diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm= /disp/mdp4/mdp4_kms.c index 7e942c1337b3597d557abd3e2e418c3958e5eb3f..00920bd44f6f73099ff2c293473= e427caa49b873 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c @@ -338,7 +338,7 @@ static int modeset_init(struct mdp4_kms *mdp4_kms) goto fail; } =20 - crtc =3D mdp4_crtc_init(dev, plane, priv->num_crtcs, i, + crtc =3D mdp4_crtc_init(dev, plane, i, mdp4_crtcs[i]); if (IS_ERR(crtc)) { DRM_DEV_ERROR(dev->dev, "failed to construct crtc for %s\n", diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h b/drivers/gpu/drm/msm= /disp/mdp4/mdp4_kms.h index f9d988076337cb6fb63af8e76be59b2eb34ab327..fb348583dc84de5c57c77fdf246= 894e9334af514 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h @@ -185,7 +185,7 @@ void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32= _t config); 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Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +-- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 3 --- drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 4 +--- drivers/gpu/drm/msm/msm_drv.h | 2 -- drivers/gpu/drm/msm/msm_kms.c | 4 ++-- 5 files changed, 4 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 1fd82b6747e9058ce11dc2620729921492d5ebdd..4b95fbbda8e120c1eb86a23e539= 7db30145d505a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -874,12 +874,11 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_= kms) ret =3D PTR_ERR(crtc); return ret; } - priv->num_crtcs++; } =20 /* All CRTCs are compatible with all encoders */ drm_for_each_encoder(encoder, dev) - encoder->possible_crtcs =3D (1 << priv->num_crtcs) - 1; + encoder->possible_crtcs =3D (1 << dev->mode_config.num_crtc) - 1; =20 return 0; } diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm= /disp/mdp4/mdp4_kms.c index 00920bd44f6f73099ff2c293473e427caa49b873..99ca1d6c54b2c24cde39de44bb5= 5151576dbe188 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c @@ -296,7 +296,6 @@ static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4= _kms, static int modeset_init(struct mdp4_kms *mdp4_kms) { struct drm_device *dev =3D mdp4_kms->dev; - struct msm_drm_private *priv =3D dev->dev_private; struct drm_plane *plane; struct drm_crtc *crtc; int i, ret; @@ -346,8 +345,6 @@ static int modeset_init(struct mdp4_kms *mdp4_kms) ret =3D PTR_ERR(crtc); goto fail; } - - priv->num_crtcs++; } =20 /* diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm= /disp/mdp5/mdp5_kms.c index 3fcca7a3d82e7aaa74379b19763c22eb43c953dd..5a706be17e2e5af2148366eacdd= db378b2f69dbd 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c @@ -374,7 +374,6 @@ static int modeset_init_intf(struct mdp5_kms *mdp5_kms, static int modeset_init(struct mdp5_kms *mdp5_kms) { struct drm_device *dev =3D mdp5_kms->dev; - struct msm_drm_private *priv =3D dev->dev_private; unsigned int num_crtcs; int i, ret, pi =3D 0, ci =3D 0; struct drm_plane *primary[MAX_BASES] =3D { NULL }; @@ -442,7 +441,6 @@ static int modeset_init(struct mdp5_kms *mdp5_kms) DRM_DEV_ERROR(dev->dev, "failed to construct crtc %d (%d)\n", i, ret); goto fail; } - priv->num_crtcs++; } =20 /* @@ -450,7 +448,7 @@ static int modeset_init(struct mdp5_kms *mdp5_kms) * crtcs for the encoders */ drm_for_each_encoder(encoder, dev) - encoder->possible_crtcs =3D (1 << priv->num_crtcs) - 1; + encoder->possible_crtcs =3D (1 << dev->mode_config.num_crtc) - 1; =20 return 0; =20 diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index cc603bd4729e909e9381a3c277db262b13361de6..09d5f57e9343cce404d4f8a3a6d= 8a285f662f60f 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -177,8 +177,6 @@ struct msm_drm_private { struct mutex lock; } lru; =20 - unsigned int num_crtcs; - struct msm_drm_thread event_thread[MAX_CRTCS]; =20 /* VRAM carveout, used when no IOMMU: */ diff --git a/drivers/gpu/drm/msm/msm_kms.c b/drivers/gpu/drm/msm/msm_kms.c index 49a56873100b2fdcded3eb6adcc7032bf404212c..9dfe0fb4755ddd11277f5242342= 97ccd5ea96001 100644 --- a/drivers/gpu/drm/msm/msm_kms.c +++ b/drivers/gpu/drm/msm/msm_kms.c @@ -245,7 +245,7 @@ void msm_drm_kms_uninit(struct device *dev) flush_workqueue(kms->wq); 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Move corresponding data pointers from struct msm_drm_private to struct msm_kms. Suggested-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 ++++---- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 32 +++++++++++--------= ---- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 8 +++--- drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 13 ++++----- drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c | 12 ++++----- drivers/gpu/drm/msm/dp/dp_display.c | 6 ++--- drivers/gpu/drm/msm/dsi/dsi.c | 4 +-- drivers/gpu/drm/msm/hdmi/hdmi.c | 13 ++++----- drivers/gpu/drm/msm/msm_drv.h | 11 +------- drivers/gpu/drm/msm/msm_kms.h | 6 +++++ 10 files changed, 57 insertions(+), 59 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index 1aaed1cd9ec58fed3230acda4c283f0eedf3a9f0..f661eec7b4d559dcaae8bef10da= 006510412d88d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -264,7 +264,7 @@ bool dpu_encoder_needs_periph_flush(struct dpu_encoder_= phys *phys_enc) mode =3D &phys_enc->cached_mode; =20 return phys_enc->hw_intf->cap->type =3D=3D INTF_DP && - msm_dp_needs_periph_flush(priv->dp[disp_info->h_tile_instance[0]],= mode); + msm_dp_needs_periph_flush(priv->kms->dp[disp_info->h_tile_instance= [0]], mode); } =20 /** @@ -283,9 +283,9 @@ bool dpu_encoder_is_widebus_enabled(const struct drm_en= coder *drm_enc) index =3D disp_info->h_tile_instance[0]; =20 if (disp_info->intf_type =3D=3D INTF_DP) - return msm_dp_wide_bus_available(priv->dp[index]); + return msm_dp_wide_bus_available(priv->kms->dp[index]); else if (disp_info->intf_type =3D=3D INTF_DSI) - return msm_dsi_wide_bus_enabled(priv->dsi[index]); + return msm_dsi_wide_bus_enabled(priv->kms->dsi[index]); =20 return false; } @@ -647,7 +647,7 @@ struct drm_dsc_config *dpu_encoder_get_dsc_config(struc= t drm_encoder *drm_enc) int index =3D dpu_enc->disp_info.h_tile_instance[0]; =20 if (dpu_enc->disp_info.intf_type =3D=3D INTF_DSI) - return msm_dsi_get_dsc_config(priv->dsi[index]); + return msm_dsi_get_dsc_config(priv->kms->dsi[index]); =20 return NULL; } @@ -709,7 +709,8 @@ void dpu_encoder_update_topology(struct drm_encoder *dr= m_enc, if (fb && MSM_FORMAT_IS_YUV(msm_framebuffer_format(fb))) topology->num_cdm++; } else if (disp_info->intf_type =3D=3D INTF_DP) { - if (msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]], a= dj_mode)) + if (msm_dp_is_yuv_420_enabled(priv->kms->dp[disp_info->h_tile_instance[0= ]], + adj_mode)) topology->num_cdm++; } } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 4b95fbbda8e120c1eb86a23e5397db30145d505a..4b85598104afbbfa52c7ee7529f= 9da403dabc10d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -582,7 +582,7 @@ static int _dpu_kms_initialize_dsi(struct drm_device *d= ev, struct msm_display_info info; int i, rc =3D 0; =20 - if (!(priv->dsi[0] || priv->dsi[1])) + if (!(priv->kms->dsi[0] || priv->kms->dsi[1])) return rc; =20 /* @@ -593,26 +593,26 @@ static int _dpu_kms_initialize_dsi(struct drm_device = *dev, * * TODO: Support swapping DSI0 and DSI1 in the bonded setup. */ - for (i =3D 0; i < ARRAY_SIZE(priv->dsi); i++) { + for (i =3D 0; i < ARRAY_SIZE(priv->kms->dsi); i++) { int other =3D (i + 1) % 2; =20 - if (!priv->dsi[i]) + if (!priv->kms->dsi[i]) continue; =20 - if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && - !msm_dsi_is_master_dsi(priv->dsi[i])) + if (msm_dsi_is_bonded_dsi(priv->kms->dsi[i]) && + !msm_dsi_is_master_dsi(priv->kms->dsi[i])) continue; =20 memset(&info, 0, sizeof(info)); info.intf_type =3D INTF_DSI; =20 info.h_tile_instance[info.num_of_h_tiles++] =3D i; - if (msm_dsi_is_bonded_dsi(priv->dsi[i])) + if (msm_dsi_is_bonded_dsi(priv->kms->dsi[i])) info.h_tile_instance[info.num_of_h_tiles++] =3D other; =20 - info.is_cmd_mode =3D msm_dsi_is_cmd_mode(priv->dsi[i]); + info.is_cmd_mode =3D msm_dsi_is_cmd_mode(priv->kms->dsi[i]); =20 - rc =3D dpu_kms_dsi_set_te_source(&info, priv->dsi[i]); + rc =3D dpu_kms_dsi_set_te_source(&info, priv->kms->dsi[i]); if (rc) { DPU_ERROR("failed to identify TE source for dsi display\n"); return rc; @@ -624,15 +624,15 @@ static int _dpu_kms_initialize_dsi(struct drm_device = *dev, return PTR_ERR(encoder); } =20 - rc =3D msm_dsi_modeset_init(priv->dsi[i], dev, encoder); + rc =3D msm_dsi_modeset_init(priv->kms->dsi[i], dev, encoder); if (rc) { DPU_ERROR("modeset_init failed for dsi[%d], rc =3D %d\n", i, rc); break; } =20 - if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) { - rc =3D msm_dsi_modeset_init(priv->dsi[other], dev, encoder); + if (msm_dsi_is_bonded_dsi(priv->kms->dsi[i]) && priv->kms->dsi[other]) { + rc =3D msm_dsi_modeset_init(priv->kms->dsi[other], dev, encoder); if (rc) { DPU_ERROR("modeset_init failed for dsi[%d], rc =3D %d\n", other, rc); @@ -654,8 +654,8 @@ static int _dpu_kms_initialize_displayport(struct drm_d= evice *dev, int rc; int i; =20 - for (i =3D 0; i < ARRAY_SIZE(priv->dp); i++) { - if (!priv->dp[i]) + for (i =3D 0; i < ARRAY_SIZE(priv->kms->dp); i++) { + if (!priv->kms->dp[i]) continue; =20 memset(&info, 0, sizeof(info)); @@ -670,7 +670,7 @@ static int _dpu_kms_initialize_displayport(struct drm_d= evice *dev, } =20 yuv_supported =3D !!dpu_kms->catalog->cdm; - rc =3D msm_dp_modeset_init(priv->dp[i], dev, encoder, yuv_supported); + rc =3D msm_dp_modeset_init(priv->kms->dp[i], dev, encoder, yuv_supported= ); if (rc) { DPU_ERROR("modeset_init failed for DP, rc =3D %d\n", rc); return rc; @@ -688,7 +688,7 @@ static int _dpu_kms_initialize_hdmi(struct drm_device *= dev, struct msm_display_info info; int rc; =20 - if (!priv->hdmi) + if (!priv->kms->hdmi) return 0; =20 memset(&info, 0, sizeof(info)); @@ -702,7 +702,7 @@ static int _dpu_kms_initialize_hdmi(struct drm_device *= dev, return PTR_ERR(encoder); } =20 - rc =3D msm_hdmi_modeset_init(priv->hdmi, dev, encoder); + rc =3D msm_hdmi_modeset_init(priv->kms->hdmi, dev, encoder); if (rc) { DPU_ERROR("modeset_init failed for DP, rc =3D %d\n", rc); return rc; diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm= /disp/mdp4/mdp4_kms.c index 99ca1d6c54b2c24cde39de44bb55151576dbe188..2bb93754925c31f515a56b842da= 122a9e0376638 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c @@ -249,9 +249,9 @@ static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4= _kms, /* DTV can be hooked to DMA_E: */ encoder->possible_crtcs =3D 1 << 1; =20 - if (priv->hdmi) { + if (priv->kms->hdmi) { /* Construct bridge/connector for HDMI: */ - ret =3D msm_hdmi_modeset_init(priv->hdmi, dev, encoder); + ret =3D msm_hdmi_modeset_init(priv->kms->hdmi, dev, encoder); if (ret) { DRM_DEV_ERROR(dev->dev, "failed to initialize HDMI: %d\n", ret); return ret; @@ -263,7 +263,7 @@ static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4= _kms, /* only DSI1 supported for now */ dsi_id =3D 0; =20 - if (!priv->dsi[dsi_id]) + if (!priv->kms->dsi[dsi_id]) break; =20 encoder =3D mdp4_dsi_encoder_init(dev); @@ -277,7 +277,7 @@ static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4= _kms, /* TODO: Add DMA_S later? */ encoder->possible_crtcs =3D 1 << DMA_P; =20 - ret =3D msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder); + ret =3D msm_dsi_modeset_init(priv->kms->dsi[dsi_id], dev, encoder); if (ret) { DRM_DEV_ERROR(dev->dev, "failed to initialize DSI: %d\n", ret); diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm= /disp/mdp5/mdp5_kms.c index 5a706be17e2e5af2148366eacdddb378b2f69dbd..87c2f7daa229dd936e0a43fd04e= 362b41a68478a 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c @@ -311,7 +311,7 @@ static int modeset_init_intf(struct mdp5_kms *mdp5_kms, DRM_DEV_INFO(dev->dev, "Skipping eDP interface %d\n", intf->num); break; case INTF_HDMI: - if (!priv->hdmi) + if (!priv->kms->hdmi) break; =20 ctl =3D mdp5_ctlm_request(ctlm, intf->num); @@ -326,7 +326,7 @@ static int modeset_init_intf(struct mdp5_kms *mdp5_kms, break; } =20 - ret =3D msm_hdmi_modeset_init(priv->hdmi, dev, encoder); + ret =3D msm_hdmi_modeset_init(priv->kms->hdmi, dev, encoder); break; case INTF_DSI: { @@ -334,14 +334,14 @@ static int modeset_init_intf(struct mdp5_kms *mdp5_km= s, mdp5_cfg_get_hw_config(mdp5_kms->cfg); int dsi_id =3D get_dsi_id_from_intf(hw_cfg, intf->num); =20 - if ((dsi_id >=3D ARRAY_SIZE(priv->dsi)) || (dsi_id < 0)) { + if ((dsi_id >=3D ARRAY_SIZE(priv->kms->dsi)) || (dsi_id < 0)) { DRM_DEV_ERROR(dev->dev, "failed to find dsi from intf %d\n", intf->num); ret =3D -EINVAL; break; } =20 - if (!priv->dsi[dsi_id]) + if (!priv->kms->dsi[dsi_id]) break; =20 ctl =3D mdp5_ctlm_request(ctlm, intf->num); @@ -356,9 +356,10 @@ static int modeset_init_intf(struct mdp5_kms *mdp5_kms, break; } =20 - ret =3D msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder); + ret =3D msm_dsi_modeset_init(priv->kms->dsi[dsi_id], dev, encoder); if (!ret) - mdp5_encoder_set_intf_mode(encoder, msm_dsi_is_cmd_mode(priv->dsi[dsi_i= d])); + mdp5_encoder_set_intf_mode(encoder, + msm_dsi_is_cmd_mode(priv->kms->dsi[dsi_id])); =20 break; } diff --git a/drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c b/drivers/gp= u/drm/msm/disp/msm_disp_snapshot_util.c index 07a2c1e872193bc96172c84142bd4ecc93a95a1c..071bcdea80f7114308e5a1e1a98= 9ad0f064a09d2 100644 --- a/drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c +++ b/drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c @@ -127,18 +127,18 @@ void msm_disp_snapshot_capture_state(struct msm_disp_= state *disp_state) priv =3D drm_dev->dev_private; kms =3D priv->kms; =20 - for (i =3D 0; i < ARRAY_SIZE(priv->dp); i++) { - if (!priv->dp[i]) + for (i =3D 0; i < ARRAY_SIZE(kms->dp); i++) { + if (!kms->dp[i]) continue; =20 - msm_dp_snapshot(disp_state, priv->dp[i]); + msm_dp_snapshot(disp_state, kms->dp[i]); } =20 - for (i =3D 0; i < ARRAY_SIZE(priv->dsi); i++) { - if (!priv->dsi[i]) + for (i =3D 0; i < ARRAY_SIZE(kms->dsi); i++) { + if (!kms->dsi[i]) continue; =20 - msm_dsi_snapshot(disp_state, priv->dsi[i]); + msm_dsi_snapshot(disp_state, kms->dsi[i]); } =20 if (kms->funcs->snapshot) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index ece184d20c0f8bffa3c2a48216015185d6cbc99e..acf126025f47589410a69e0b21c= 392854873d544 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -277,9 +277,7 @@ static int msm_dp_display_bind(struct device *dev, stru= ct device *master, struct drm_device *drm =3D priv->dev; =20 dp->msm_dp_display.drm_dev =3D drm; - priv->dp[dp->id] =3D &dp->msm_dp_display; - - + priv->kms->dp[dp->id] =3D &dp->msm_dp_display; =20 dp->drm_dev =3D drm; dp->aux->drm_dev =3D drm; @@ -313,7 +311,7 @@ static void msm_dp_display_unbind(struct device *dev, s= truct device *master, msm_dp_aux_unregister(dp->aux); dp->drm_dev =3D NULL; dp->aux->drm_dev =3D NULL; - priv->dp[dp->id] =3D NULL; + priv->kms->dp[dp->id] =3D NULL; } =20 static const struct component_ops msm_dp_display_comp_ops =3D { diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c index 2962158776135d6e3c5b119bf4341c135c8f5248..d8bb40ef820e2b8c8ac933ca01e= 1dc46f087a218 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.c +++ b/drivers/gpu/drm/msm/dsi/dsi.c @@ -136,7 +136,7 @@ static int dsi_bind(struct device *dev, struct device *= master, void *data) msm_dsi->next_bridge =3D ext_bridge; } =20 - priv->dsi[msm_dsi->id] =3D msm_dsi; + priv->kms->dsi[msm_dsi->id] =3D msm_dsi; =20 return 0; } @@ -148,7 +148,7 @@ static void dsi_unbind(struct device *dev, struct devic= e *master, struct msm_dsi *msm_dsi =3D dev_get_drvdata(dev); =20 msm_dsi_tx_buf_free(msm_dsi->host); - priv->dsi[msm_dsi->id] =3D NULL; + priv->kms->dsi[msm_dsi->id] =3D NULL; } =20 static const struct component_ops dsi_ops =3D { diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdm= i.c index 248541ff449204c72cd444458dadb9ae4a0a53d1..9970176d74302964dc80e4eb5b9= 149161667cfc3 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c @@ -14,6 +14,7 @@ #include #include =20 +#include "msm_kms.h" #include "hdmi.h" =20 void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on) @@ -253,7 +254,7 @@ static int msm_hdmi_bind(struct device *dev, struct dev= ice *master, void *data) err =3D msm_hdmi_init(hdmi); if (err) return err; - priv->hdmi =3D hdmi; + priv->kms->hdmi =3D hdmi; =20 return 0; } @@ -263,12 +264,12 @@ static void msm_hdmi_unbind(struct device *dev, struc= t device *master, { struct msm_drm_private *priv =3D dev_get_drvdata(master); =20 - if (priv->hdmi) { - if (priv->hdmi->bridge) - msm_hdmi_hpd_disable(priv->hdmi); + if (priv->kms->hdmi) { + if (priv->kms->hdmi->bridge) + msm_hdmi_hpd_disable(priv->kms->hdmi); =20 - msm_hdmi_destroy(priv->hdmi); - priv->hdmi =3D NULL; + msm_hdmi_destroy(priv->kms->hdmi); + priv->kms->hdmi =3D NULL; } } =20 diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 09d5f57e9343cce404d4f8a3a6d8a285f662f60f..5ec129bf6a9c83ec8e3d5b66741= 1dd0917a76582 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -88,16 +88,6 @@ struct msm_drm_private { /* subordinate devices, if present: */ struct platform_device *gpu_pdev; =20 - /* possibly this should be in the kms component, but it is - * shared by both mdp4 and mdp5.. - */ - struct hdmi *hdmi; - - /* DSI is shared by mdp4 and mdp5 */ - struct msm_dsi *dsi[MSM_DSI_CONTROLLER_COUNT]; - - struct msm_dp *dp[MSM_DP_CONTROLLER_COUNT]; - /* when we have more than one 'msm_gpu' these need to be an array: */ struct msm_gpu *gpu; =20 @@ -356,6 +346,7 @@ static inline const char *msm_dsi_get_te_source(struct = msm_dsi *msm_dsi) } #endif =20 +struct msm_dp; #ifdef CONFIG_DRM_MSM_DP int __init msm_dp_register(void); void __exit msm_dp_unregister(void); diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h index 26cbb662e7533fdfd55fb7f200b99c79c3fd3211..14762b39edca381c817fa509d0d= 1da6f535e5da7 100644 --- a/drivers/gpu/drm/msm/msm_kms.h +++ b/drivers/gpu/drm/msm/msm_kms.h @@ -131,6 +131,12 @@ struct msm_kms { const struct msm_kms_funcs *funcs; struct drm_device *dev; =20 + struct hdmi *hdmi; + + struct msm_dsi *dsi[MSM_DSI_CONTROLLER_COUNT]; + + struct msm_dp *dp[MSM_DP_CONTROLLER_COUNT]; + /* irq number to be passed on to msm_irq_install */ int irq; bool irq_requested; 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Build corresponding parts conditionally, only selecting them if modeset support is actually required. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/Kconfig | 14 +++++ drivers/gpu/drm/msm/Makefile | 19 +++---- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 +- drivers/gpu/drm/msm/dp/dp_debug.c | 4 ++ drivers/gpu/drm/msm/msm_debugfs.c | 92 ++++++++++++++++++----------= ---- drivers/gpu/drm/msm/msm_drv.h | 10 +--- drivers/gpu/drm/msm/msm_kms.c | 6 +-- drivers/gpu/drm/msm/msm_kms.h | 30 +++++++++++ 8 files changed, 117 insertions(+), 62 deletions(-) diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index 7f127e2ae44292f8f5c7ff6a9251c3d7ec8c9f58..cada5832db3e894c9bae4c6b0c6= d935dbf5d933f 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -66,6 +66,14 @@ config DRM_MSM_VALIDATE_XML Validate XML files with register definitions against rules-fd schema. This option is mostly targeting DRM MSM developers. If unsure, say N. =20 +config DRM_MSM_KMS + def_bool n + depends on DRM_MSM + +config DRM_MSM_KMS_FBDEV + def_bool DRM_FBDEV_EMULATION + depends on DRM_MSM_KMS + config DRM_MSM_MDSS bool depends on DRM_MSM @@ -74,6 +82,7 @@ config DRM_MSM_MDSS config DRM_MSM_MDP4 bool "Enable MDP4 support in MSM DRM driver" depends on DRM_MSM + select DRM_MSM_KMS default y help Compile in support for the Mobile Display Processor v4 (MDP4) in @@ -84,6 +93,7 @@ config DRM_MSM_MDP5 bool "Enable MDP5 support in MSM DRM driver" depends on DRM_MSM select DRM_MSM_MDSS + select DRM_MSM_KMS default y help Compile in support for the Mobile Display Processor v5 (MDP5) in @@ -94,6 +104,7 @@ config DRM_MSM_DPU bool "Enable DPU support in MSM DRM driver" depends on DRM_MSM select DRM_MSM_MDSS + select DRM_MSM_KMS select DRM_DISPLAY_DSC_HELPER default y help @@ -104,6 +115,7 @@ config DRM_MSM_DPU config DRM_MSM_DP bool "Enable DisplayPort support in MSM DRM driver" depends on DRM_MSM + depends on DRM_MSM_KMS select DRM_DISPLAY_HDMI_AUDIO_HELPER select RATIONAL default y @@ -115,6 +127,7 @@ config DRM_MSM_DP config DRM_MSM_DSI bool "Enable DSI support in MSM DRM driver" depends on DRM_MSM + depends on DRM_MSM_KMS select DRM_PANEL select DRM_MIPI_DSI select DRM_DISPLAY_DSC_HELPER @@ -170,6 +183,7 @@ config DRM_MSM_DSI_7NM_PHY config DRM_MSM_HDMI bool "Enable HDMI support in MSM DRM driver" depends on DRM_MSM + depends on DRM_MSM_KMS default y select DRM_DISPLAY_HDMI_HELPER select DRM_DISPLAY_HDMI_STATE_HELPER diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 7a2ada6e2d74a902879e4f12a78ed475e5209ec2..7c4508f0e5c84914633f8f2d5dd= d04bd10e4d189 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -100,18 +100,15 @@ msm-display-$(CONFIG_DRM_MSM_DPU) +=3D \ msm-display-$(CONFIG_DRM_MSM_MDSS) +=3D \ msm_mdss.o \ =20 -msm-display-y +=3D \ +msm-display-$(CONFIG_DRM_MSM_KMS) +=3D \ disp/mdp_format.o \ disp/mdp_kms.o \ disp/msm_disp_snapshot.o \ disp/msm_disp_snapshot_util.o \ =20 msm-y +=3D \ - msm_atomic.o \ - msm_atomic_tracepoints.o \ msm_debugfs.o \ msm_drv.o \ - msm_fb.o \ msm_fence.o \ msm_gem.o \ msm_gem_prime.o \ @@ -122,21 +119,24 @@ msm-y +=3D \ msm_gpu_devfreq.o \ msm_io_utils.o \ msm_iommu.o \ - msm_kms.o \ msm_perf.o \ msm_rd.o \ msm_ringbuffer.o \ msm_submitqueue.o \ msm_gpu_tracepoints.o \ =20 -msm-$(CONFIG_DRM_FBDEV_EMULATION) +=3D msm_fbdev.o +msm-$(CONFIG_DRM_MSM_KMS) +=3D \ + msm_atomic.o \ + msm_atomic_tracepoints.o \ + msm_fb.o \ + msm_kms.o \ =20 -msm-display-$(CONFIG_DEBUG_FS) +=3D \ - dp/dp_debug.o +msm-$(CONFIG_DRM_MSM_KMS_FBDEV) +=3D msm_fbdev.o =20 msm-display-$(CONFIG_DRM_MSM_DP)+=3D dp/dp_aux.o \ dp/dp_catalog.o \ dp/dp_ctrl.o \ + dp/dp_debug.o \ dp/dp_display.o \ dp/dp_drm.o \ dp/dp_link.o \ @@ -159,7 +159,8 @@ msm-display-$(CONFIG_DRM_MSM_DSI_14NM_PHY) +=3D dsi/phy= /dsi_phy_14nm.o msm-display-$(CONFIG_DRM_MSM_DSI_10NM_PHY) +=3D dsi/phy/dsi_phy_10nm.o msm-display-$(CONFIG_DRM_MSM_DSI_7NM_PHY) +=3D dsi/phy/dsi_phy_7nm.o =20 -msm-y +=3D $(adreno-y) $(msm-display-y) +msm-y +=3D $(adreno-y) +msm-$(CONFIG_DRM_MSM_KMS) +=3D $(msm-display-y) =20 obj-$(CONFIG_DRM_MSM) +=3D msm.o =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 0714936d883523e5c53bfb42f932234db76c58db..08ea11d452f2ea93fba8bdcc487= 385433e81d224 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -709,7 +709,7 @@ void dpu_crtc_frame_event_cb(struct drm_crtc *crtc, u32= event) fevent->event =3D event; fevent->crtc =3D crtc; fevent->ts =3D ktime_get(); - kthread_queue_work(priv->event_thread[crtc_id].worker, &fevent->work); + kthread_queue_work(priv->kms->event_thread[crtc_id].worker, &fevent->work= ); } =20 /** @@ -878,7 +878,7 @@ static void dpu_crtc_atomic_flush(struct drm_crtc *crtc, dev =3D crtc->dev; priv =3D dev->dev_private; =20 - if (crtc->index >=3D ARRAY_SIZE(priv->event_thread)) { + if (crtc->index >=3D ARRAY_SIZE(priv->kms->event_thread)) { DPU_ERROR("invalid crtc index[%d]\n", crtc->index); return; } diff --git a/drivers/gpu/drm/msm/dp/dp_debug.c b/drivers/gpu/drm/msm/dp/dp_= debug.c index 22fd946ee201397b72b43c8499714139deb7ba82..7835d93015b31a69aac824ca04d= c65b374546e5c 100644 --- a/drivers/gpu/drm/msm/dp/dp_debug.c +++ b/drivers/gpu/drm/msm/dp/dp_debug.c @@ -5,6 +5,8 @@ =20 #define pr_fmt(fmt)"[drm-dp] %s: " fmt, __func__ =20 +#ifdef CONFIG_DEBUG_FS + #include #include #include @@ -235,3 +237,5 @@ int msm_dp_debug_init(struct device *dev, struct msm_dp= _panel *panel, =20 return 0; } + +#endif diff --git a/drivers/gpu/drm/msm/msm_debugfs.c b/drivers/gpu/drm/msm/msm_de= bugfs.c index 7ab607252d183f78b99c3a8b878c949ed5f99fec..2b12f2851fadbc3c924827e1157= 0352736869614 100644 --- a/drivers/gpu/drm/msm/msm_debugfs.c +++ b/drivers/gpu/drm/msm/msm_debugfs.c @@ -117,6 +117,36 @@ static const struct file_operations msm_gpu_fops =3D { .release =3D msm_gpu_release, }; =20 +#ifdef CONFIG_DRM_MSM_KMS +static int msm_fb_show(struct seq_file *m, void *arg) +{ + struct drm_info_node *node =3D m->private; + struct drm_device *dev =3D node->minor->dev; + struct drm_framebuffer *fb, *fbdev_fb =3D NULL; + + if (dev->fb_helper && dev->fb_helper->fb) { + seq_puts(m, "fbcon "); + fbdev_fb =3D dev->fb_helper->fb; + msm_framebuffer_describe(fbdev_fb, m); + } + + mutex_lock(&dev->mode_config.fb_lock); + list_for_each_entry(fb, &dev->mode_config.fb_list, head) { + if (fb =3D=3D fbdev_fb) + continue; + + seq_puts(m, "user "); + msm_framebuffer_describe(fb, m); + } + mutex_unlock(&dev->mode_config.fb_lock); + + return 0; +} + +static struct drm_info_list msm_kms_debugfs_list[] =3D { + { "fb", msm_fb_show }, +}; + /* * Display Snapshot: */ @@ -180,6 +210,27 @@ static const struct file_operations msm_kms_fops =3D { .release =3D msm_kms_release, }; =20 +static void msm_debugfs_kms_init(struct drm_minor *minor) +{ + struct drm_device *dev =3D minor->dev; + struct msm_drm_private *priv =3D dev->dev_private; + + drm_debugfs_create_files(msm_kms_debugfs_list, + ARRAY_SIZE(msm_kms_debugfs_list), + minor->debugfs_root, minor); + debugfs_create_file("kms", 0400, minor->debugfs_root, + dev, &msm_kms_fops); + + if (priv->kms->funcs->debugfs_init) + priv->kms->funcs->debugfs_init(priv->kms, minor); + +} +#else /* ! CONFIG_DRM_MSM_KMS */ +static void msm_debugfs_kms_init(struct drm_minor *minor) +{ +} +#endif + /* * Other debugfs: */ @@ -238,40 +289,11 @@ static int msm_mm_show(struct seq_file *m, void *arg) return 0; } =20 -static int msm_fb_show(struct seq_file *m, void *arg) -{ - struct drm_info_node *node =3D m->private; - struct drm_device *dev =3D node->minor->dev; - struct drm_framebuffer *fb, *fbdev_fb =3D NULL; - - if (dev->fb_helper && dev->fb_helper->fb) { - seq_printf(m, "fbcon "); - fbdev_fb =3D dev->fb_helper->fb; - msm_framebuffer_describe(fbdev_fb, m); - } - - mutex_lock(&dev->mode_config.fb_lock); - list_for_each_entry(fb, &dev->mode_config.fb_list, head) { - if (fb =3D=3D fbdev_fb) - continue; - - seq_printf(m, "user "); - msm_framebuffer_describe(fb, m); - } - mutex_unlock(&dev->mode_config.fb_lock); - - return 0; -} - static struct drm_info_list msm_debugfs_list[] =3D { {"gem", msm_gem_show}, { "mm", msm_mm_show }, }; =20 -static struct drm_info_list msm_kms_debugfs_list[] =3D { - { "fb", msm_fb_show }, -}; - static int late_init_minor(struct drm_minor *minor) { int ret; @@ -343,20 +365,12 @@ void msm_debugfs_init(struct drm_minor *minor) if (priv->gpu_pdev) msm_debugfs_gpu_init(minor); =20 - if (priv->kms) { - drm_debugfs_create_files(msm_kms_debugfs_list, - ARRAY_SIZE(msm_kms_debugfs_list), - minor->debugfs_root, minor); - debugfs_create_file("kms", S_IRUSR, minor->debugfs_root, - dev, &msm_kms_fops); - } + if (priv->kms) + msm_debugfs_kms_init(minor); =20 debugfs_create_file("shrink", S_IRWXU, minor->debugfs_root, dev, &shrink_fops); =20 - if (priv->kms && priv->kms->funcs->debugfs_init) - priv->kms->funcs->debugfs_init(priv->kms, minor); - fault_create_debugfs_attr("fail_gem_alloc", minor->debugfs_root, &fail_gem_alloc); fault_create_debugfs_attr("fail_gem_iova", minor->debugfs_root, diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 5ec129bf6a9c83ec8e3d5b667411dd0917a76582..f6b4c5e1dc3a18516e0e40703b2= 4d3ae37b7c35d 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -72,12 +72,6 @@ enum msm_dsi_controller { =20 #define MSM_GPU_MAX_RINGS 4 =20 -/* Commit/Event thread specific structure */ -struct msm_drm_thread { - struct drm_device *dev; - struct kthread_worker *worker; -}; - struct msm_drm_private { =20 struct drm_device *dev; @@ -167,8 +161,6 @@ struct msm_drm_private { struct mutex lock; } lru; =20 - struct msm_drm_thread event_thread[MAX_CRTCS]; - /* VRAM carveout, used when no IOMMU: */ struct { unsigned long size; @@ -261,7 +253,7 @@ struct drm_framebuffer *msm_framebuffer_create(struct d= rm_device *dev, struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev, int w, int h, int p, uint32_t format); =20 -#ifdef CONFIG_DRM_FBDEV_EMULATION +#ifdef CONFIG_DRM_MSM_KMS_FBDEV int msm_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper, struct drm_fb_helper_surface_size *sizes); #define MSM_FBDEV_DRIVER_OPS \ diff --git a/drivers/gpu/drm/msm/msm_kms.c b/drivers/gpu/drm/msm/msm_kms.c index 9dfe0fb4755ddd11277f524234297ccd5ea96001..ea133e50d0bfd2b2b60e5ceb37d= faf72f43a2828 100644 --- a/drivers/gpu/drm/msm/msm_kms.c +++ b/drivers/gpu/drm/msm/msm_kms.c @@ -246,8 +246,8 @@ void msm_drm_kms_uninit(struct device *dev) =20 /* clean up event worker threads */ for (i =3D 0; i < MAX_CRTCS; i++) { - if (priv->event_thread[i].worker) - kthread_destroy_worker(priv->event_thread[i].worker); + if (kms->event_thread[i].worker) + kthread_destroy_worker(kms->event_thread[i].worker); } =20 drm_kms_helper_poll_fini(ddev); @@ -300,7 +300,7 @@ int msm_drm_kms_init(struct device *dev, const struct d= rm_driver *drv) struct msm_drm_thread *ev_thread; =20 /* initialize event thread */ - ev_thread =3D &priv->event_thread[drm_crtc_index(crtc)]; + ev_thread =3D &kms->event_thread[drm_crtc_index(crtc)]; ev_thread->dev =3D ddev; ev_thread->worker =3D kthread_run_worker(0, "crtc_event:%d", crtc->base.= id); if (IS_ERR(ev_thread->worker)) { diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h index 14762b39edca381c817fa509d0d1da6f535e5da7..c15868bd380937d64455f9bf2d2= 571c7492396b4 100644 --- a/drivers/gpu/drm/msm/msm_kms.h +++ b/drivers/gpu/drm/msm/msm_kms.h @@ -13,6 +13,8 @@ =20 #include "msm_drv.h" =20 +#ifdef CONFIG_DRM_MSM_KMS + #define MAX_PLANE 4 =20 /* As there are different display controller blocks depending on the @@ -127,6 +129,12 @@ struct msm_pending_timer { unsigned crtc_idx; }; =20 +/* Commit/Event thread specific structure */ +struct msm_drm_thread { + struct drm_device *dev; + struct kthread_worker *worker; +}; + struct msm_kms { const struct msm_kms_funcs *funcs; struct drm_device *dev; @@ -161,6 +169,7 @@ struct msm_kms { struct msm_pending_timer pending_timers[MAX_CRTCS]; =20 struct workqueue_struct *wq; + struct msm_drm_thread event_thread[MAX_CRTCS]; }; =20 static inline int msm_kms_init(struct msm_kms *kms, @@ -210,4 +219,25 @@ void msm_drm_kms_post_init(struct device *dev); void msm_drm_kms_unregister(struct device *dev); void msm_drm_kms_uninit(struct device *dev); =20 +#else /* ! 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Bail out if we are registering a KMS-only device. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_debugfs.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_debugfs.c b/drivers/gpu/drm/msm/msm_de= bugfs.c index 2b12f2851fadbc3c924827e11570352736869614..6e60a74b13d72c47e45cb9dc65e= d67b977e900fa 100644 --- a/drivers/gpu/drm/msm/msm_debugfs.c +++ b/drivers/gpu/drm/msm/msm_debugfs.c @@ -296,11 +296,16 @@ static struct drm_info_list msm_debugfs_list[] =3D { =20 static int late_init_minor(struct drm_minor *minor) { + struct drm_device *dev =3D minor->dev; + struct msm_drm_private *priv =3D dev->dev_private; int ret; =20 if (!minor) return 0; =20 + if (!priv->gpu_pdev) + return 0; + ret =3D msm_rd_debugfs_init(minor); if (ret) { DRM_DEV_ERROR(minor->dev->dev, "could not install rd debugfs\n"); --=20 2.39.5 From nobody Fri Dec 19 20:35:45 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B06A218AC3 for ; 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Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/Kconfig | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index cada5832db3e894c9bae4c6b0c6d935dbf5d933f..f6360931ae55a2923264f0e6cc3= 3c6af0d50c706 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -15,18 +15,8 @@ config DRM_MSM select IOMMU_IO_PGTABLE select QCOM_MDT_LOADER if ARCH_QCOM select REGULATOR - select DRM_CLIENT_SELECTION - select DRM_DISPLAY_DP_AUX_BUS - select DRM_DISPLAY_DP_HELPER - select DRM_DISPLAY_HELPER - select DRM_BRIDGE_CONNECTOR select DRM_EXEC - select DRM_KMS_HELPER - select DRM_PANEL - select DRM_BRIDGE - select DRM_PANEL_BRIDGE select DRM_SCHED - select FB_SYSMEM_HELPERS if DRM_FBDEV_EMULATION select SHMEM select TMPFS select QCOM_SCM @@ -69,10 +59,18 @@ config DRM_MSM_VALIDATE_XML config DRM_MSM_KMS def_bool n depends on DRM_MSM + select DRM_BRIDGE + select DRM_BRIDGE_CONNECTOR + select DRM_CLIENT_SELECTION + select DRM_DISPLAY_HELPER + select DRM_KMS_HELPER + select DRM_PANEL + select DRM_PANEL_BRIDGE =20 config DRM_MSM_KMS_FBDEV def_bool DRM_FBDEV_EMULATION depends on DRM_MSM_KMS + select FB_SYSMEM_HELPERS =20 config DRM_MSM_MDSS bool @@ -118,6 +116,8 @@ config DRM_MSM_DP depends on DRM_MSM_KMS select DRM_DISPLAY_HDMI_AUDIO_HELPER select RATIONAL + select DRM_DISPLAY_DP_AUX_BUS + select DRM_DISPLAY_DP_HELPER default y help Compile in support for DP driver in MSM DRM driver. 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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-328085cf8ccsm14314451fa.99.2025.05.18.03.55.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 May 2025 03:55:41 -0700 (PDT) From: Dmitry Baryshkov Date: Sun, 18 May 2025 13:55:27 +0300 Subject: [PATCH v3 09/11] drm/msm: rework binding of Imageon GPUs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250518-msm-gpu-split-v3-9-0e91e8e77023@oss.qualcomm.com> References: <20250518-msm-gpu-split-v3-0-0e91e8e77023@oss.qualcomm.com> In-Reply-To: <20250518-msm-gpu-split-v3-0-0e91e8e77023@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=8539; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=0LqRPtPOFWdF3NM/7wOtnNgFIrF9n7ejqAUYuZxTuFI=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoKbya1AzQz4b/8IxydV3XRJgKMle+XUQ911LvG uFJbg4dUPaJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaCm8mgAKCRCLPIo+Aiko 1R1WB/9d+TsZ3SeNofduSai6+uHnuuU/lV5GVRWJONKdBgldEBA1F6wl966+AltHq7n0pqjdGaE u8XN4j/FwePUJ9+RgMiYXi3LCi+VwyuhX7Lk1a41EILLFzlgEo6fJpQN92kO5RoLZc/+PbtSOjN cMaqKP/YICW7Ryp7gJgf5xssIH6TNvoxHlH8zwxnpyqeO1JtFnXy9siIPizhNsj0F8RZUymiZ1B /iCW+c5FXdVTvYJ48xPRYZPvoQiwQz9O947HAALux9fpM/aGdeChukq1GHug2Ne3+qQ6agNitaK yXxbevk+JDjxu/1cdxuMcmDbpQDbi9cnAGyLpJz1q7oAVUq5 X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: 6DGR_86qNjRtAGJhWTS6r_KM23mZlubN X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE4MDEwNCBTYWx0ZWRfXyjQKlJhVlhw1 OF/Cr71oeoWhX0LRMC9n9s0vQPcw+HNkLzgCX76RpOh/VjKAo4qYhznxLNo4123ijlI5Mu+p5eH gCH7kyJmEuw5mHvt1u7ltTOkmo+2mq+EdVBqcZlqbb5H/eGTe6rsR1VQ3UTltaR4cgyJO6UUlbh 1QZS89fPqg6YqA9DMMgorgqwhqhCBwj3jzJaWlABCvs1PqIRE/cc7d5Q7QvDBsxNlzElX+vQoHr rPsSf/HMeqe2go+GWEwgL14TloC9vOdWhAf7uqqws2uzY0Hw/K3eVhiJOiCWd4f8chGFmtEH0S4 8Dgj2v+CpHUJbyRTFwkcOwB/SfXKu/ZU24ekyJ4IVbVsIzWgl6AFB6Uo5KahzMsCg2cJfxtDuId HOOa7VpZFmL4x3NyvKVQKls+rZKuu9axXFe96A6aOAHepjBKUC0uxIEBkIM0NxMvxNMrMrEu X-Authority-Analysis: v=2.4 cv=aJXwqa9m c=1 sm=1 tr=0 ts=6829bcaf cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=WrGWoQF6NLblfNs28g4A:9 a=QEXdDO2ut3YA:10 a=iYH6xdkBrDN1Jqds4HTS:22 X-Proofpoint-ORIG-GUID: 6DGR_86qNjRtAGJhWTS6r_KM23mZlubN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-18_05,2025-05-16_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 phishscore=0 adultscore=0 clxscore=1015 mlxlogscore=999 spamscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505180104 Currently the msm driver creates an extra interim platform device for Imageon GPUs. This is not ideal, as the device doesn't have corresponding OF node. If the headless mode is used for newer GPUs, then the msm_use_mmu() function can not detect corresponding IOMMU devices. Also the DRM device (although it's headless) is created with modesetting flags being set. To solve all these issues, rework the way the Imageon devices are bound. Remove the interim device, don't register a component and instead use a cut-down version of the normal functions to probe or remove the driver. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/adreno_device.c | 36 +++--------- drivers/gpu/drm/msm/msm_drv.c | 91 ++++++++++++++++++++------= ---- drivers/gpu/drm/msm/msm_drv.h | 4 ++ 3 files changed, 72 insertions(+), 59 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/m= sm/adreno/adreno_device.c index f5e1490d07c1868fa21cddb38de44c28af5ca0d5..574bc452f3df539cc8e03e16104= 3b310d83c624f 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -245,42 +245,22 @@ static const struct component_ops a3xx_ops =3D { .unbind =3D adreno_unbind, }; =20 -static void adreno_device_register_headless(void) -{ - /* on imx5, we don't have a top-level mdp/dpu node - * this creates a dummy node for the driver for that case - */ - struct platform_device_info dummy_info =3D { - .parent =3D NULL, - .name =3D "msm", - .id =3D -1, - .res =3D NULL, - .num_res =3D 0, - .data =3D NULL, - .size_data =3D 0, - .dma_mask =3D ~0, - }; - platform_device_register_full(&dummy_info); -} - static int adreno_probe(struct platform_device *pdev) { - - int ret; - - ret =3D component_add(&pdev->dev, &a3xx_ops); - if (ret) - return ret; - if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon")) - adreno_device_register_headless(); + return msm_gpu_probe(pdev, &a3xx_ops); =20 - return 0; + return component_add(&pdev->dev, &a3xx_ops); } =20 static void adreno_remove(struct platform_device *pdev) { - component_del(&pdev->dev, &a3xx_ops); + struct msm_drm_private *priv =3D platform_get_drvdata(pdev); + + if (priv->kms_init) + component_del(&pdev->dev, &a3xx_ops); + else + msm_gpu_remove(pdev, &a3xx_ops); } =20 static void adreno_shutdown(struct platform_device *pdev) diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 2c6997c85fbbc3767315ca3a166a99b322f1218a..804b594ba1e7df9d9aec53a9be1= 451f1167fc77a 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -62,7 +62,7 @@ module_param(modeset, bool, 0600); DECLARE_FAULT_ATTR(fail_gem_alloc); DECLARE_FAULT_ATTR(fail_gem_iova); =20 -static int msm_drm_uninit(struct device *dev) +static int msm_drm_uninit(struct device *dev, const struct component_ops *= gpu_ops) { struct platform_device *pdev =3D to_platform_device(dev); struct msm_drm_private *priv =3D platform_get_drvdata(pdev); @@ -91,7 +91,10 @@ static int msm_drm_uninit(struct device *dev) =20 msm_deinit_vram(ddev); =20 - component_unbind_all(dev, ddev); + if (gpu_ops) + gpu_ops->unbind(dev, dev, NULL); + else + component_unbind_all(dev, ddev); =20 ddev->dev_private =3D NULL; drm_dev_put(ddev); @@ -200,7 +203,8 @@ static void msm_deinit_vram(struct drm_device *ddev) attrs); } =20 -static int msm_drm_init(struct device *dev, const struct drm_driver *drv) +static int msm_drm_init(struct device *dev, const struct drm_driver *drv, + const struct component_ops *gpu_ops) { struct msm_drm_private *priv =3D dev_get_drvdata(dev); struct drm_device *ddev; @@ -247,7 +251,10 @@ static int msm_drm_init(struct device *dev, const stru= ct drm_driver *drv) dma_set_max_seg_size(dev, UINT_MAX); =20 /* Bind all our sub-components: */ - ret =3D component_bind_all(dev, ddev); + if (gpu_ops) + ret =3D gpu_ops->bind(dev, dev, NULL); + else + ret =3D component_bind_all(dev, ddev); if (ret) goto err_deinit_vram; =20 @@ -259,11 +266,6 @@ static int msm_drm_init(struct device *dev, const stru= ct drm_driver *drv) ret =3D msm_drm_kms_init(dev, drv); if (ret) goto err_msm_uninit; - } else { - /* valid only for the dummy headless case, where of_node=3DNULL */ - WARN_ON(dev->of_node); - ddev->driver_features &=3D ~DRIVER_MODESET; - ddev->driver_features &=3D ~DRIVER_ATOMIC; } =20 ret =3D drm_dev_register(ddev, 0); @@ -280,7 +282,7 @@ static int msm_drm_init(struct device *dev, const struc= t drm_driver *drv) return 0; =20 err_msm_uninit: - msm_drm_uninit(dev); + msm_drm_uninit(dev, gpu_ops); =20 return ret; =20 @@ -896,6 +898,28 @@ static const struct drm_driver msm_driver =3D { .patchlevel =3D MSM_VERSION_PATCHLEVEL, }; =20 +static const struct drm_driver msm_gpu_driver =3D { + .driver_features =3D DRIVER_GEM | + DRIVER_RENDER | + DRIVER_SYNCOBJ_TIMELINE | + DRIVER_SYNCOBJ, + .open =3D msm_open, + .postclose =3D msm_postclose, + .gem_prime_import_sg_table =3D msm_gem_prime_import_sg_table, +#ifdef CONFIG_DEBUG_FS + .debugfs_init =3D msm_debugfs_init, +#endif + .show_fdinfo =3D msm_show_fdinfo, + .ioctls =3D msm_ioctls, + .num_ioctls =3D ARRAY_SIZE(msm_ioctls), + .fops =3D &fops, + .name =3D "msm", + .desc =3D "MSM Snapdragon DRM", + .major =3D MSM_VERSION_MAJOR, + .minor =3D MSM_VERSION_MINOR, + .patchlevel =3D MSM_VERSION_PATCHLEVEL, +}; + /* * Componentized driver support: */ @@ -1020,12 +1044,12 @@ static int add_gpu_components(struct device *dev, =20 static int msm_drm_bind(struct device *dev) { - return msm_drm_init(dev, &msm_driver); + return msm_drm_init(dev, &msm_driver, NULL); } =20 static void msm_drm_unbind(struct device *dev) { - msm_drm_uninit(dev); + msm_drm_uninit(dev, NULL); } =20 const struct component_master_ops msm_drm_ops =3D { @@ -1074,29 +1098,34 @@ int msm_drv_probe(struct device *master_dev, return 0; } =20 -/* - * Platform driver: - * Used only for headlesss GPU instances - */ - -static int msm_pdev_probe(struct platform_device *pdev) +int msm_gpu_probe(struct platform_device *pdev, + const struct component_ops *ops) { - return msm_drv_probe(&pdev->dev, NULL, NULL); + struct msm_drm_private *priv; + int ret; + + priv =3D devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + platform_set_drvdata(pdev, priv); + + /* on all devices that I am aware of, iommu's which can map + * any address the cpu can see are used: + */ + ret =3D dma_set_mask_and_coherent(&pdev->dev, ~0); + if (ret) + return ret; + + return msm_drm_init(&pdev->dev, &msm_gpu_driver, ops); } =20 -static void msm_pdev_remove(struct platform_device *pdev) +void msm_gpu_remove(struct platform_device *pdev, + const struct component_ops *ops) { - component_master_del(&pdev->dev, &msm_drm_ops); + msm_drm_uninit(&pdev->dev, ops); } =20 -static struct platform_driver msm_platform_driver =3D { - .probe =3D msm_pdev_probe, - .remove =3D msm_pdev_remove, - .driver =3D { - .name =3D "msm", - }, -}; - static int __init msm_drm_register(void) { if (!modeset) @@ -1111,13 +1140,13 @@ static int __init msm_drm_register(void) adreno_register(); msm_mdp4_register(); msm_mdss_register(); - return platform_driver_register(&msm_platform_driver); + + return 0; } =20 static void __exit msm_drm_unregister(void) { DBG("fini"); - platform_driver_unregister(&msm_platform_driver); msm_mdss_unregister(); msm_mdp4_unregister(); msm_dp_unregister(); diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index f6b4c5e1dc3a18516e0e40703b24d3ae37b7c35d..e7d8715bc61ccdee822bc6a1a0b= 0bbe7c8ff3552 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -532,6 +532,10 @@ extern const struct component_master_ops msm_drm_ops; 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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-328085cf8ccsm14314451fa.99.2025.05.18.03.55.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 May 2025 03:55:42 -0700 (PDT) From: Dmitry Baryshkov Date: Sun, 18 May 2025 13:55:28 +0300 Subject: [PATCH v3 10/11] drm/msm: enable separate binding of GPU and display devices Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250518-msm-gpu-split-v3-10-0e91e8e77023@oss.qualcomm.com> References: <20250518-msm-gpu-split-v3-0-0e91e8e77023@oss.qualcomm.com> In-Reply-To: <20250518-msm-gpu-split-v3-0-0e91e8e77023@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5220; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=c8ydcyDO/BqF2oOo3z5sqYBctAmcpc0ltuKnWJ+WQEo=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoKbyaRdSB02zKvPq4UwWXD+YF8pWpYeFOkXSUG J9PpnJZKuaJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaCm8mgAKCRCLPIo+Aiko 1RomCACPGsiSyB0yMMNsAQd0cnrf7rjgX6ZBJQBPS3cnk8zgBqIZlIRB5Kb55ZVapPEYxSX588S jKsiWCV+7NjviMSGSGZeSW5TBUI7dYOwsBQe/ooY/LdZ8/3T5ou/vvmV1hEZxDGsMjQpXKRfiIf nPuud3RgQll7DR63tfifpCR0YhUdfTthgox1l4S+1ESPO3F+8+YYcXobo2cSoJ+s40WwWpoUGAt jkAT2RTTAqND1MWBJQyoco3Lrv8MU0tyXxGlgqEFGR/rapd8271EJG05BGFhClirwtmPjl1MfbT UKkLbOerb6zvSFbH0odrT1cpPcdJgH6ZOeS2TgKJuVmaVhkD X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: 2B4LAExTiXx_SWVtKhCySXHQN-HpLQfW X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE4MDEwNCBTYWx0ZWRfX5L7dk/gAlFxl tBehPOOvYUEMfY6WgtWwYibcYMA1vLk7w9UdDM9jI45x694MElNR6QQP36NTRqoRC0VwBo/PQrR FHD3ors5ckMSKQ0ovBAd+ImKZ2buD+89jXtlUx6oXCetS7wYtAjGceXXyaxdidK3BYSMzthybTu 4BIBq2z/qmZZXupA73hhIqQ+LLPOWwLl28xs5S/wbQW1e6LxvwUnBAmeY+a1DUSB22AAuJzqn9I VeuGQNdkQwfV+UwrGYVxJjgyE+mELhxgN9cNx3oNkuJpV+TmghQjeHLbrNVKJQqcoglVqfA8Pus vkqs8dyuX+Cit+kTOwpuioO4CaxfehEpjeHIOjSQnbyIn8Xb5gu6P7PwKcyGDlxygCqoxXH6rpr 7og7p1cemjarPH5lvNOhP+ZBNd0snUNxqBKVvEfekJ3RNjxblb4J7EQMlCHBajyAfD4p9ZA6 X-Authority-Analysis: v=2.4 cv=CKkqXQrD c=1 sm=1 tr=0 ts=6829bcb1 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=d3EbUlffPpwbv2rupc8A:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 X-Proofpoint-GUID: 2B4LAExTiXx_SWVtKhCySXHQN-HpLQfW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-18_05,2025-05-16_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 mlxscore=0 mlxlogscore=999 suspectscore=0 spamscore=0 adultscore=0 impostorscore=0 phishscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505180104 There are cases when we want to have separate DRM devices for GPU and display pipelines. One example is development, when it is beneficial to be able to bind the GPU driver separately, without the display pipeline (and without the hacks adding "amd,imageon" to the compatible string). Another example is some of Qualcomm platforms, which have two MDSS units, but only one GPU. With current approach it is next to impossible to support this usecase properly, while separate binding allows users to have three DRM devices: two for MDSS units and a single headless GPU. Add kernel param msm.separate_gpu_drm, which if set to true forces creation of separate display and GPU DRM devices. Mesa supports this setup by using the kmsro wrapper. The param is disabled by default, in order to be able to test userspace for the compatibility issues. Simple clients are able to handle this setup automatically. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/adreno_device.c | 3 +- drivers/gpu/drm/msm/msm_drv.c | 47 ++++++++++++++++++++++++++= +--- drivers/gpu/drm/msm/msm_drv.h | 2 ++ 3 files changed, 47 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/m= sm/adreno/adreno_device.c index 574bc452f3df539cc8e03e161043b310d83c624f..142c321b57692649cfb8f2fc3b0= ff3b4a6012c1c 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -247,7 +247,8 @@ static const struct component_ops a3xx_ops =3D { =20 static int adreno_probe(struct platform_device *pdev) { - if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon")) + if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon") || + msm_gpu_no_components()) return msm_gpu_probe(pdev, &a3xx_ops); =20 return component_add(&pdev->dev, &a3xx_ops); diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 804b594ba1e7df9d9aec53a9be1451f1167fc77a..45953affccc73c622a805a13990= 2ebedcdf38b86 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -59,9 +59,18 @@ static bool modeset =3D true; MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=3Don (default),= 0=3Ddisable)"); module_param(modeset, bool, 0600); =20 +static bool separate_gpu_drm; +MODULE_PARM_DESC(separate_gpu_drm, "Use separate DRM device for the GPU (0= =3Dsingle DRM device for both GPU and display (default), 1=3Dtwo DRM device= s)"); +module_param(separate_gpu_drm, bool, 0400); + DECLARE_FAULT_ATTR(fail_gem_alloc); DECLARE_FAULT_ATTR(fail_gem_iova); =20 +bool msm_gpu_no_components(void) +{ + return separate_gpu_drm; +} + static int msm_drm_uninit(struct device *dev, const struct component_ops *= gpu_ops) { struct platform_device *pdev =3D to_platform_device(dev); @@ -898,6 +907,30 @@ static const struct drm_driver msm_driver =3D { .patchlevel =3D MSM_VERSION_PATCHLEVEL, }; =20 +static const struct drm_driver msm_kms_driver =3D { + .driver_features =3D DRIVER_GEM | + DRIVER_ATOMIC | + DRIVER_MODESET, + .open =3D msm_open, + .postclose =3D msm_postclose, + .dumb_create =3D msm_gem_dumb_create, + .dumb_map_offset =3D msm_gem_dumb_map_offset, + .gem_prime_import_sg_table =3D msm_gem_prime_import_sg_table, +#ifdef CONFIG_DEBUG_FS + .debugfs_init =3D msm_debugfs_init, +#endif + MSM_FBDEV_DRIVER_OPS, + .show_fdinfo =3D msm_show_fdinfo, + .ioctls =3D msm_ioctls, + .num_ioctls =3D ARRAY_SIZE(msm_ioctls), + .fops =3D &fops, + .name =3D "msm-kms", + .desc =3D "MSM Snapdragon DRM", + .major =3D MSM_VERSION_MAJOR, + .minor =3D MSM_VERSION_MINOR, + .patchlevel =3D MSM_VERSION_PATCHLEVEL, +}; + static const struct drm_driver msm_gpu_driver =3D { .driver_features =3D DRIVER_GEM | DRIVER_RENDER | @@ -1044,7 +1077,11 @@ static int add_gpu_components(struct device *dev, =20 static int msm_drm_bind(struct device *dev) { - return msm_drm_init(dev, &msm_driver, NULL); + return msm_drm_init(dev, + msm_gpu_no_components() ? + &msm_kms_driver : + &msm_driver, + NULL); } =20 static void msm_drm_unbind(struct device *dev) @@ -1080,9 +1117,11 @@ int msm_drv_probe(struct device *master_dev, return ret; } =20 - ret =3D add_gpu_components(master_dev, &match); - if (ret) - return ret; + if (!msm_gpu_no_components()) { + ret =3D add_gpu_components(master_dev, &match); + if (ret) + return ret; + } =20 /* on all devices that I am aware of, iommu's which can map * any address the cpu can see are used: diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index e7d8715bc61ccdee822bc6a1a0b0bbe7c8ff3552..1ff799f0c78133e73c6857e3692= c2dca2c5e60fa 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -543,4 +543,6 @@ void msm_kms_shutdown(struct platform_device *pdev); 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Make it possible to disable the GPU part of the driver and build the KMS-only part. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/Kconfig | 25 +++++-- drivers/gpu/drm/msm/Makefile | 14 ++-- drivers/gpu/drm/msm/msm_debugfs.c | 135 ++++++++++++++++++------------= ---- drivers/gpu/drm/msm/msm_drv.c | 37 ++++++++-- drivers/gpu/drm/msm/msm_drv.h | 3 + drivers/gpu/drm/msm/msm_gpu.h | 71 +++++++++++++++--- drivers/gpu/drm/msm/msm_submitqueue.c | 12 +-- 7 files changed, 194 insertions(+), 103 deletions(-) diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index f6360931ae55a2923264f0e6cc33c6af0d50c706..4c94c0a43f1c204866d8259d3c1= c38065c957a1f 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -13,31 +13,39 @@ config DRM_MSM depends on QCOM_COMMAND_DB || QCOM_COMMAND_DB=3Dn depends on PM select IOMMU_IO_PGTABLE - select QCOM_MDT_LOADER if ARCH_QCOM select REGULATOR - select DRM_EXEC - select DRM_SCHED select SHMEM select TMPFS - select QCOM_SCM select WANT_DEV_COREDUMP select SND_SOC_HDMI_CODEC if SND_SOC - select SYNC_FILE select PM_OPP - select NVMEM select PM_GENERIC_DOMAINS select TRACE_GPU_MEM help DRM/KMS driver for MSM/snapdragon. =20 +config DRM_MSM_ADRENO + bool "Qualcomm Adreno GPU support" + default y + depends on DRM_MSM + select DRM_EXEC + select DRM_SCHED + select NVMEM + select QCOM_MDT_LOADER if ARCH_QCOM + select QCOM_SCM if ARCH_QCOM + select SYNC_FILE + help + Enable support for the GPU present on most of Qualcomm Snapdragon + SoCs. If you are unsure, say Y. + config DRM_MSM_GPU_STATE bool - depends on DRM_MSM && (DEBUG_FS || DEV_COREDUMP) + depends on DRM_MSM_ADRENO && (DEBUG_FS || DEV_COREDUMP) default y =20 config DRM_MSM_GPU_SUDO bool "Enable SUDO flag on submits" - depends on DRM_MSM && EXPERT + depends on DRM_MSM_ADRENO && EXPERT default n help Enable userspace that has CAP_SYS_RAWIO to submit GPU commands @@ -187,6 +195,7 @@ config DRM_MSM_HDMI default y select DRM_DISPLAY_HDMI_HELPER select DRM_DISPLAY_HDMI_STATE_HELPER + select QCOM_SCM help Compile in support for the HDMI output MSM DRM driver. It can be a primary or a secondary display on device. Note that this is used diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 7c4508f0e5c84914633f8f2d5ddd04bd10e4d189..6a24f78d7fc51cc1c9cd706d746= cabd5f567d282 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -109,21 +109,23 @@ msm-display-$(CONFIG_DRM_MSM_KMS) +=3D \ msm-y +=3D \ msm_debugfs.o \ msm_drv.o \ - msm_fence.o \ msm_gem.o \ msm_gem_prime.o \ msm_gem_shrinker.o \ - msm_gem_submit.o \ msm_gem_vma.o \ - msm_gpu.o \ - msm_gpu_devfreq.o \ msm_io_utils.o \ msm_iommu.o \ + msm_gpu_tracepoints.o \ + +msm-$(CONFIG_DRM_MSM_ADRENO) +=3D \ + msm_fence.o \ + msm_gem_submit.o \ + msm_gpu.o \ + msm_gpu_devfreq.o \ msm_perf.o \ msm_rd.o \ msm_ringbuffer.o \ msm_submitqueue.o \ - msm_gpu_tracepoints.o \ =20 msm-$(CONFIG_DRM_MSM_KMS) +=3D \ msm_atomic.o \ @@ -159,7 +161,7 @@ msm-display-$(CONFIG_DRM_MSM_DSI_14NM_PHY) +=3D dsi/phy= /dsi_phy_14nm.o msm-display-$(CONFIG_DRM_MSM_DSI_10NM_PHY) +=3D dsi/phy/dsi_phy_10nm.o msm-display-$(CONFIG_DRM_MSM_DSI_7NM_PHY) +=3D dsi/phy/dsi_phy_7nm.o =20 -msm-y +=3D $(adreno-y) +msm-$(CONFIG_DRM_MSM_ADRENO) +=3D $(adreno-y) msm-$(CONFIG_DRM_MSM_KMS) +=3D $(msm-display-y) =20 obj-$(CONFIG_DRM_MSM) +=3D msm.o diff --git a/drivers/gpu/drm/msm/msm_debugfs.c b/drivers/gpu/drm/msm/msm_de= bugfs.c index 6e60a74b13d72c47e45cb9dc65ed67b977e900fa..fa9a94a86d060e28d4ee93fda1f= 22924fd5af606 100644 --- a/drivers/gpu/drm/msm/msm_debugfs.c +++ b/drivers/gpu/drm/msm/msm_debugfs.c @@ -20,6 +20,7 @@ #include "msm_debugfs.h" #include "disp/msm_disp_snapshot.h" =20 +#ifdef CONFIG_DRM_MSM_ADRENO /* * GPU Snapshot: */ @@ -117,6 +118,76 @@ static const struct file_operations msm_gpu_fops =3D { .release =3D msm_gpu_release, }; =20 +static void msm_debugfs_gpu_init(struct drm_minor *minor) +{ + struct drm_device *dev =3D minor->dev; + struct msm_drm_private *priv =3D dev->dev_private; + struct dentry *gpu_devfreq; + + debugfs_create_file("gpu", 0400, minor->debugfs_root, + dev, &msm_gpu_fops); + + debugfs_create_u32("hangcheck_period_ms", 0600, minor->debugfs_root, + &priv->hangcheck_period); + + debugfs_create_bool("disable_err_irq", 0600, minor->debugfs_root, + &priv->disable_err_irq); + + gpu_devfreq =3D debugfs_create_dir("devfreq", minor->debugfs_root); + + debugfs_create_bool("idle_clamp", 0600, gpu_devfreq, + &priv->gpu_clamp_to_idle); + + debugfs_create_u32("upthreshold", 0600, gpu_devfreq, + &priv->gpu_devfreq_config.upthreshold); + + debugfs_create_u32("downdifferential", 0600, gpu_devfreq, + &priv->gpu_devfreq_config.downdifferential); +} + +static int late_init_minor(struct drm_minor *minor) +{ + struct drm_device *dev =3D minor->dev; + struct msm_drm_private *priv =3D dev->dev_private; + int ret; + + if (!minor) + return 0; + + if (!priv->gpu_pdev) + return 0; + + ret =3D msm_rd_debugfs_init(minor); + if (ret) { + DRM_DEV_ERROR(minor->dev->dev, "could not install rd debugfs\n"); + return ret; + } + + ret =3D msm_perf_debugfs_init(minor); + if (ret) { + DRM_DEV_ERROR(minor->dev->dev, "could not install perf debugfs\n"); + return ret; + } + + return 0; +} + +int msm_debugfs_late_init(struct drm_device *dev) +{ + int ret; + + ret =3D late_init_minor(dev->primary); + if (ret) + return ret; + ret =3D late_init_minor(dev->render); + return ret; +} +#else /* ! CONFIG_DRM_MSM_ADRENO */ +static void msm_debugfs_gpu_init(struct drm_minor *minor) +{ +} +#endif /* CONFIG_DRM_MSM_ADRENO */ + #ifdef CONFIG_DRM_MSM_KMS static int msm_fb_show(struct seq_file *m, void *arg) { @@ -294,70 +365,6 @@ static struct drm_info_list msm_debugfs_list[] =3D { { "mm", msm_mm_show }, }; =20 -static int late_init_minor(struct drm_minor *minor) -{ - struct drm_device *dev =3D minor->dev; - struct msm_drm_private *priv =3D dev->dev_private; - int ret; - - if (!minor) - return 0; - - if (!priv->gpu_pdev) - return 0; - - ret =3D msm_rd_debugfs_init(minor); - if (ret) { - DRM_DEV_ERROR(minor->dev->dev, "could not install rd debugfs\n"); - return ret; - } - - ret =3D msm_perf_debugfs_init(minor); - if (ret) { - DRM_DEV_ERROR(minor->dev->dev, "could not install perf debugfs\n"); - return ret; - } - - return 0; -} - -int msm_debugfs_late_init(struct drm_device *dev) -{ - int ret; - ret =3D late_init_minor(dev->primary); - if (ret) - return ret; - ret =3D late_init_minor(dev->render); - return ret; -} - -static void msm_debugfs_gpu_init(struct drm_minor *minor) -{ - struct drm_device *dev =3D minor->dev; - struct msm_drm_private *priv =3D dev->dev_private; - struct dentry *gpu_devfreq; - - debugfs_create_file("gpu", S_IRUSR, minor->debugfs_root, - dev, &msm_gpu_fops); - - debugfs_create_u32("hangcheck_period_ms", 0600, minor->debugfs_root, - &priv->hangcheck_period); - - debugfs_create_bool("disable_err_irq", 0600, minor->debugfs_root, - &priv->disable_err_irq); - - gpu_devfreq =3D debugfs_create_dir("devfreq", minor->debugfs_root); - - debugfs_create_bool("idle_clamp",0600, gpu_devfreq, - &priv->gpu_clamp_to_idle); - - debugfs_create_u32("upthreshold",0600, gpu_devfreq, - &priv->gpu_devfreq_config.upthreshold); - - debugfs_create_u32("downdifferential",0600, gpu_devfreq, - &priv->gpu_devfreq_config.downdifferential); -} - void msm_debugfs_init(struct drm_minor *minor) { struct drm_device *dev =3D minor->dev; diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 45953affccc73c622a805a139902ebedcdf38b86..97f2595a4a83ea04361c3aed634= 39d4e5e032a60 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -59,7 +59,11 @@ static bool modeset =3D true; MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=3Don (default),= 0=3Ddisable)"); module_param(modeset, bool, 0600); =20 +#ifndef CONFIG_DRM_MSM_ADRENO +static bool separate_gpu_drm =3D true; +#else static bool separate_gpu_drm; +#endif MODULE_PARM_DESC(separate_gpu_drm, "Use separate DRM device for the GPU (0= =3Dsingle DRM device for both GPU and display (default), 1=3Dtwo DRM device= s)"); module_param(separate_gpu_drm, bool, 0400); =20 @@ -320,6 +324,22 @@ static void load_gpu(struct drm_device *dev) mutex_unlock(&init_lock); } =20 +void __msm_file_private_destroy(struct kref *kref) +{ + struct msm_file_private *ctx =3D container_of(kref, + struct msm_file_private, ref); + + msm_submitqueue_fini(ctx); + msm_gem_address_space_put(ctx->aspace); + +#ifdef CONFIG_DRM_MSM_ADRENO + kfree(ctx->comm); + kfree(ctx->cmdline); +#endif + + kfree(ctx); +} + static int context_init(struct drm_device *dev, struct drm_file *file) { static atomic_t ident =3D ATOMIC_INIT(0); @@ -330,9 +350,6 @@ static int context_init(struct drm_device *dev, struct = drm_file *file) if (!ctx) return -ENOMEM; =20 - INIT_LIST_HEAD(&ctx->submitqueues); - rwlock_init(&ctx->queuelock); - kref_init(&ctx->ref); msm_submitqueue_init(dev, ctx); =20 @@ -717,6 +734,7 @@ static int msm_ioctl_gem_info(struct drm_device *dev, v= oid *data, return ret; } =20 +#ifdef CONFIG_DRM_MSM_ADRENO static int wait_fence(struct msm_gpu_submitqueue *queue, uint32_t fence_id, ktime_t timeout, uint32_t flags) { @@ -787,6 +805,7 @@ static int msm_ioctl_wait_fence(struct drm_device *dev,= void *data, =20 return ret; } +#endif =20 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data, struct drm_file *file) @@ -820,6 +839,7 @@ static int msm_ioctl_gem_madvise(struct drm_device *dev= , void *data, } =20 =20 +#ifdef CONFIG_DRM_MSM_ADRENO static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data, struct drm_file *file) { @@ -845,6 +865,7 @@ static int msm_ioctl_submitqueue_close(struct drm_devic= e *dev, void *data, =20 return msm_submitqueue_remove(file->driver_priv, id); } +#endif =20 static const struct drm_ioctl_desc msm_ioctls[] =3D { DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_AL= LOW), @@ -853,12 +874,14 @@ static const struct drm_ioctl_desc msm_ioctls[] =3D { DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_AL= LOW), DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_AL= LOW), DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_AL= LOW), + DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_AL= LOW), +#ifdef CONFIG_DRM_MSM_ADRENO DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_AL= LOW), DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_AL= LOW), - DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_AL= LOW), DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM= _RENDER_ALLOW), DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM= _RENDER_ALLOW), DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM= _RENDER_ALLOW), +#endif }; =20 static void msm_show_fdinfo(struct drm_printer *p, struct drm_file *file) @@ -866,10 +889,8 @@ static void msm_show_fdinfo(struct drm_printer *p, str= uct drm_file *file) struct drm_device *dev =3D file->minor->dev; struct msm_drm_private *priv =3D dev->dev_private; =20 - if (!priv->gpu) - return; - - msm_gpu_show_fdinfo(priv->gpu, file->driver_priv, p); + if (priv->gpu) + msm_gpu_show_fdinfo(priv->gpu, file->driver_priv, p); =20 drm_show_memory_stats(p, file); } diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 1ff799f0c78133e73c6857e3692c2dca2c5e60fa..ba4012ea2f6845061380ae2daa8= eb3a0999f2e9e 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -424,6 +424,9 @@ static inline void msm_mdss_unregister(void) {} =20 #ifdef CONFIG_DEBUG_FS void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file = *m); +#endif + +#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_DRM_MSM_ADRENO) int msm_debugfs_late_init(struct drm_device *dev); int msm_rd_debugfs_init(struct drm_minor *minor); void msm_rd_debugfs_cleanup(struct msm_drm_private *priv); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index e25009150579c08f7b98d4461a75757d1093734a..6db6ef6b02db2450be68cc27e65= be9aced6da7ce 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -358,12 +358,13 @@ struct msm_gpu_perfcntr { * @seqno: unique per process seqno */ struct msm_file_private { - rwlock_t queuelock; - struct list_head submitqueues; - int queueid; struct msm_gem_address_space *aspace; struct kref ref; int seqno; +#ifdef CONFIG_DRM_MSM_ADRENO + rwlock_t queuelock; + struct list_head submitqueues; + int queueid; =20 /** * sysprof: @@ -425,6 +426,7 @@ struct msm_file_private { * level. */ struct drm_sched_entity *entities[NR_SCHED_PRIORITIES * MSM_GPU_MAX_RINGS= ]; +#endif =20 /** * ctx_mem: @@ -559,6 +561,7 @@ struct msm_gpu_state { struct msm_gpu_state_bo *bos; }; =20 +#ifdef CONFIG_DRM_MSM_ADRENO static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data) { writel(data, gpu->mmio + (reg << 2)); @@ -612,6 +615,7 @@ void msm_gpu_show_fdinfo(struct msm_gpu *gpu, struct ms= m_file_private *ctx, struct drm_printer *p); =20 int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *= ctx); +void msm_submitqueue_fini(struct msm_file_private *ctx); struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *c= tx, u32 id); int msm_submitqueue_create(struct drm_device *drm, @@ -624,8 +628,42 @@ void msm_submitqueue_close(struct msm_file_private *ct= x); =20 void msm_submitqueue_destroy(struct kref *kref); =20 +static inline void msm_submitqueue_put(struct msm_gpu_submitqueue *queue) +{ + if (queue) + kref_put(&queue->ref, msm_submitqueue_destroy); +} + int msm_file_private_set_sysprof(struct msm_file_private *ctx, struct msm_gpu *gpu, int sysprof); +#else +static inline void msm_gpu_show_fdinfo(struct msm_gpu *gpu, + struct msm_file_private *ctx, + struct drm_printer *p) +{ +} + +static inline int msm_submitqueue_init(struct drm_device *drm, struct msm_= file_private *ctx) +{ + return -ENXIO; +} + +static inline void msm_submitqueue_fini(struct msm_file_private *ctx) +{ +} + +static inline void msm_submitqueue_close(struct msm_file_private *ctx) +{ +} + +static inline int msm_file_private_set_sysprof(struct msm_file_private *ct= x, + struct msm_gpu *gpu, + int sysprof) +{ + return 0; +} +#endif + void __msm_file_private_destroy(struct kref *kref); =20 static inline void msm_file_private_put(struct msm_file_private *ctx) @@ -640,6 +678,7 @@ static inline struct msm_file_private *msm_file_private= _get( return ctx; } =20 +#ifdef CONFIG_DRM_MSM_ADRENO void msm_devfreq_init(struct msm_gpu *gpu); void msm_devfreq_cleanup(struct msm_gpu *gpu); void msm_devfreq_resume(struct msm_gpu *gpu); @@ -671,12 +710,6 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev= ); void __init adreno_register(void); void __exit adreno_unregister(void); =20 -static inline void msm_submitqueue_put(struct msm_gpu_submitqueue *queue) -{ - if (queue) - kref_put(&queue->ref, msm_submitqueue_destroy); -} - static inline struct msm_gpu_state *msm_gpu_crashstate_get(struct msm_gpu = *gpu) { struct msm_gpu_state *state =3D NULL; @@ -712,5 +745,25 @@ static inline void msm_gpu_crashstate_put(struct msm_g= pu *gpu) #define check_apriv(gpu, flags) \ (((gpu)->hw_apriv ? MSM_BO_MAP_PRIV : 0) | (flags)) =20 +#else /* ! CONFIG_DRM_MSM_ADRENO */ +static inline struct msm_gem_address_space * +msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_stru= ct *task) +{ + return NULL; +} + +static inline struct msm_gpu *adreno_load_gpu(struct drm_device *dev) +{ + return NULL; +} + +static inline void __init adreno_register(void) +{ +} + +static inline void __exit adreno_unregister(void) +{ +} +#endif /* ! CONFIG_DRM_MSM_ADRENO */ =20 #endif /* __MSM_GPU_H__ */ diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c b/drivers/gpu/drm/msm/ms= m_submitqueue.c index 7fed1de63b5d9e20df88db8d9ca6ea45ec1a2846..dfb6f42a963ee3d314f11716d86= 49f3bf82a3eb6 100644 --- a/drivers/gpu/drm/msm/msm_submitqueue.c +++ b/drivers/gpu/drm/msm/msm_submitqueue.c @@ -46,10 +46,8 @@ int msm_file_private_set_sysprof(struct msm_file_private= *ctx, return 0; } =20 -void __msm_file_private_destroy(struct kref *kref) +void msm_submitqueue_fini(struct msm_file_private *ctx) { - struct msm_file_private *ctx =3D container_of(kref, - struct msm_file_private, ref); int i; =20 for (i =3D 0; i < ARRAY_SIZE(ctx->entities); i++) { @@ -59,11 +57,6 @@ void __msm_file_private_destroy(struct kref *kref) drm_sched_entity_destroy(ctx->entities[i]); kfree(ctx->entities[i]); } - - msm_gem_address_space_put(ctx->aspace); - kfree(ctx->comm); - kfree(ctx->cmdline); - kfree(ctx); } =20 void msm_submitqueue_destroy(struct kref *kref) @@ -226,6 +219,9 @@ int msm_submitqueue_init(struct drm_device *drm, struct= msm_file_private *ctx) struct msm_drm_private *priv =3D drm->dev_private; int default_prio, max_priority; =20 + INIT_LIST_HEAD(&ctx->submitqueues); + rwlock_init(&ctx->queuelock); + if (!priv->gpu) return -ENODEV; =20 --=20 2.39.5