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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-328084ca34csm14186881fa.30.2025.05.18.04.21.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 May 2025 04:21:38 -0700 (PDT) From: Dmitry Baryshkov Date: Sun, 18 May 2025 14:21:34 +0300 Subject: [PATCH v6 01/11] drm/msm/dp: split MMSS_DP_DSC_DTO register write to a separate function Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250518-fd-dp-audio-fixup-v6-1-2f0ec3ec000d@oss.qualcomm.com> References: <20250518-fd-dp-audio-fixup-v6-0-2f0ec3ec000d@oss.qualcomm.com> In-Reply-To: <20250518-fd-dp-audio-fixup-v6-0-2f0ec3ec000d@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Paloma Arellano Cc: Douglas Anderson , Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3146; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=/GMTajfgX5DJx2us6iS4i6AlKgNdptMEPO7PC3DA05s=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoKcK/DjiL8Y03I/FRxMKvknvQjg2GH898wVxON gb+VHMeBeaJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaCnCvwAKCRCLPIo+Aiko 1Tr+B/41Vm0d/UkXnBsuj88/YsnYqBtPAKHVqUq3MtR5mgOWjdUnk7xRAwa8FowVCRn1PaKePum YIZ5S8u05sRpyoWM1lyW04bRa3S+5lyYiUctfEKv3/dY7fq1/ekPj/NGlwGLQ7Ku9LRnTl8X5hO DwM/b5e2mQYZKeMG6cdi97l7/B7SBnIOVKQ/E3J2TnwtOAMRfUHZH1W3+UZ1xiDo01PtIx1zl+S fUcdoULfPfKhLtyPt7TTUdH8g11GguNzNeOxtjgkk1Zb+JUjpGtEE8UEX987jMBIiAILZLyTqL3 VDnfTpRp6ANMaiN7E6QAI428jBB1zH27USM5xJzQxN7wgLEA X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Authority-Analysis: v=2.4 cv=dIimmPZb c=1 sm=1 tr=0 ts=6829c2c5 cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=KKAkSRfTAAAA:8 a=cm27Pg_UAAAA:8 a=zRKm0RuqD35KdulPN9UA:9 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: MsoRc1tPPXYtsMo3y0i2Hu4BhyVuE2Rs X-Proofpoint-GUID: MsoRc1tPPXYtsMo3y0i2Hu4BhyVuE2Rs X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE4MDEwOCBTYWx0ZWRfX5yBG2aeoiJ7l Zb/NBjP3jftGI912HNTxfuUe6fWHBJYRkJBW4eZX9GkODDPTYK7nl46R02NvMUOywvWw5lsDLG9 VaCpvtZxC1/pDhmUMAiL9gKWG4Kle+adAT2AO2GE6GpbUTGlhnWPiR9MXAPvtdkltMeeM9s6WpA nYZcKkPTqwr4tP44G9jOtEbkmO39lWVDNw+tcId2CaKFu/+X0/qCs9cTylZo/b8mC/KL9cn9xNT /41rk1ERE8dnaI4AVnhAnZicwijzVTIkgxTTBjQDgnBnnfea/pNNXVwINolUZCbWh2WioPNO6KO ibrlIGSxoxWNllqcyJkhjxB/PzTb4sTWtzz6b16No8glqGnzOAniyscH1g80ohiSKiwcMYctpho NjenSladZAQknDeHyCx+gsnmb46iLb+74J26RRK6KdRW6jY4AZ693OVcM6hH5vDqFT+lpKP0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-18_06,2025-05-16_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxscore=0 bulkscore=0 malwarescore=0 suspectscore=0 impostorscore=0 clxscore=1015 phishscore=0 adultscore=0 priorityscore=1501 mlxlogscore=966 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505180108 From: Dmitry Baryshkov It's the dp_panel's duty to clear the MMSS_DP_DSC_DTO register. Once DP driver gets DSC support, it will handle that register in other places too. Split a call to write 0x0 to that register to a separate function. Reviewed-by: Stephen Boyd Tested-by: Stephen Boyd # sc7180-trogdor Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_catalog.c | 9 ++++++++- drivers/gpu/drm/msm/dp/dp_catalog.h | 2 ++ drivers/gpu/drm/msm/dp/dp_ctrl.c | 2 ++ 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/d= p_catalog.c index 7b7eadb2f83b169d8df27ee93589abe05b38f3ae..4f80eceb6ae19f542110d737900= 7f57c2ac16a8a 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -486,7 +486,6 @@ void msm_dp_catalog_ctrl_config_msa(struct msm_dp_catal= og *msm_dp_catalog, drm_dbg_dp(catalog->drm_dev, "mvid=3D0x%x, nvid=3D0x%x\n", mvid, nvid); msm_dp_write_link(catalog, REG_DP_SOFTWARE_MVID, mvid); msm_dp_write_link(catalog, REG_DP_SOFTWARE_NVID, nvid); - msm_dp_write_p0(catalog, MMSS_DP_DSC_DTO, 0x0); } =20 int msm_dp_catalog_ctrl_set_pattern_state_bit(struct msm_dp_catalog *msm_d= p_catalog, @@ -1039,6 +1038,14 @@ void msm_dp_catalog_panel_tpg_disable(struct msm_dp_= catalog *msm_dp_catalog) msm_dp_write_p0(catalog, MMSS_DP_TIMING_ENGINE_EN, 0x0); } =20 +void msm_dp_catalog_panel_clear_dsc_dto(struct msm_dp_catalog *msm_dp_cata= log) +{ + struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, + struct msm_dp_catalog_private, msm_dp_catalog); + + msm_dp_write_p0(catalog, MMSS_DP_DSC_DTO, 0x0); +} + static void __iomem *msm_dp_ioremap(struct platform_device *pdev, int idx,= size_t *len) { struct resource *res; diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/d= p_catalog.h index 6678b0ac9a67881244884d59487fa288d33d1be7..08bb42e91b779633875dbeb4130= bc55a6571cfb1 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -92,6 +92,8 @@ void msm_dp_catalog_panel_tpg_enable(struct msm_dp_catalo= g *msm_dp_catalog, struct drm_display_mode *drm_mode); void msm_dp_catalog_panel_tpg_disable(struct msm_dp_catalog *msm_dp_catalo= g); =20 +void msm_dp_catalog_panel_clear_dsc_dto(struct msm_dp_catalog *msm_dp_cata= log); + struct msm_dp_catalog *msm_dp_catalog_get(struct device *dev); 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Read it once, after the first software reset. Reviewed-by: Stephen Boyd Tested-by: Stephen Boyd # sc7180-trogdor Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_catalog.c | 29 ++++++++--------------------- drivers/gpu/drm/msm/dp/dp_catalog.h | 2 +- 2 files changed, 9 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/d= p_catalog.c index 4f80eceb6ae19f542110d7379007f57c2ac16a8a..23f9fcb75123a58b3a4b69d3dad= 0598135108eec 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -414,14 +414,13 @@ void msm_dp_catalog_ctrl_config_misc(struct msm_dp_ca= talog *msm_dp_catalog, =20 void msm_dp_catalog_setup_peripheral_flush(struct msm_dp_catalog *msm_dp_c= atalog) { - u32 mainlink_ctrl, hw_revision; + u32 mainlink_ctrl; struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, msm_dp_catalog); =20 mainlink_ctrl =3D msm_dp_read_link(catalog, REG_DP_MAINLINK_CTRL); =20 - hw_revision =3D msm_dp_catalog_hw_revision(msm_dp_catalog); - if (hw_revision >=3D DP_HW_VERSION_1_2) + if (msm_dp_catalog->hw_revision >=3D DP_HW_VERSION_1_2) mainlink_ctrl |=3D DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE; else mainlink_ctrl |=3D DP_MAINLINK_FLUSH_MODE_UPDATE_SDP; @@ -514,22 +513,6 @@ int msm_dp_catalog_ctrl_set_pattern_state_bit(struct m= sm_dp_catalog *msm_dp_cata return 0; } =20 -/** - * msm_dp_catalog_hw_revision() - retrieve DP hw revision - * - * @msm_dp_catalog: DP catalog structure - * - * Return: DP controller hw revision - * - */ -u32 msm_dp_catalog_hw_revision(const struct msm_dp_catalog *msm_dp_catalog) -{ - const struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_cata= log, - struct msm_dp_catalog_private, msm_dp_catalog); - - return msm_dp_read_ahb(catalog, REG_DP_HW_VERSION); -} - /** * msm_dp_catalog_ctrl_reset() - reset DP controller * @@ -556,6 +539,9 @@ void msm_dp_catalog_ctrl_reset(struct msm_dp_catalog *m= sm_dp_catalog) =20 sw_reset &=3D ~DP_SW_RESET; msm_dp_write_ahb(catalog, REG_DP_SW_RESET, sw_reset); + + if (!msm_dp_catalog->hw_revision) + msm_dp_catalog->hw_revision =3D msm_dp_read_ahb(catalog, REG_DP_HW_VERSI= ON); } =20 bool msm_dp_catalog_ctrl_mainlink_ready(struct msm_dp_catalog *msm_dp_cata= log) @@ -895,9 +881,10 @@ static void msm_dp_catalog_panel_update_sdp(struct msm= _dp_catalog *msm_dp_catalo u32 hw_revision; =20 catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, m= sm_dp_catalog); + hw_revision =3D msm_dp_catalog->hw_revision; =20 - hw_revision =3D msm_dp_catalog_hw_revision(msm_dp_catalog); - if (hw_revision < DP_HW_VERSION_1_2 && hw_revision >=3D DP_HW_VERSION_1_0= ) { + if (hw_revision < DP_HW_VERSION_1_2 && + hw_revision >=3D DP_HW_VERSION_1_0) { msm_dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x01); msm_dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x00); } diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/d= p_catalog.h index 08bb42e91b779633875dbeb4130bc55a6571cfb1..379fa4fef9ceb63b20c4aec2fca= 1e09003dc738b 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -33,6 +33,7 @@ =20 struct msm_dp_catalog { bool wide_bus_en; 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Move I/O region base and size to the globally visible struct msm_dp_catalog. Reviewed-by: Stephen Boyd Tested-by: Stephen Boyd # sc7180-trogdor Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_catalog.c | 536 +++++++++++++++-----------------= ---- drivers/gpu/drm/msm/dp/dp_catalog.h | 12 + 2 files changed, 231 insertions(+), 317 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/d= p_catalog.c index 23f9fcb75123a58b3a4b69d3dad0598135108eec..74ab86035f3b98b498756673229= 218558b6713c3 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -63,154 +63,127 @@ #define DP_DEFAULT_P0_OFFSET 0x1000 #define DP_DEFAULT_P0_SIZE 0x0400 =20 -struct dss_io_region { - size_t len; - void __iomem *base; -}; - -struct dss_io_data { - struct dss_io_region ahb; - struct dss_io_region aux; - struct dss_io_region link; - struct dss_io_region p0; -}; - struct msm_dp_catalog_private { struct device *dev; struct drm_device *drm_dev; - struct dss_io_data io; struct msm_dp_catalog msm_dp_catalog; }; =20 void msm_dp_catalog_snapshot(struct msm_dp_catalog *msm_dp_catalog, struct= msm_disp_state *disp_state) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - struct dss_io_data *dss =3D &catalog->io; - - msm_disp_snapshot_add_block(disp_state, dss->ahb.len, dss->ahb.base, "dp_= ahb"); - msm_disp_snapshot_add_block(disp_state, dss->aux.len, dss->aux.base, "dp_= aux"); - msm_disp_snapshot_add_block(disp_state, dss->link.len, dss->link.base, "d= p_link"); - msm_disp_snapshot_add_block(disp_state, dss->p0.len, dss->p0.base, "dp_p0= "); + msm_disp_snapshot_add_block(disp_state, + msm_dp_catalog->ahb_len, msm_dp_catalog->ahb_base, "dp_ahb"); + msm_disp_snapshot_add_block(disp_state, + msm_dp_catalog->aux_len, msm_dp_catalog->aux_base, "dp_aux"); + msm_disp_snapshot_add_block(disp_state, + msm_dp_catalog->link_len, msm_dp_catalog->link_base, "dp_link"); + msm_disp_snapshot_add_block(disp_state, + msm_dp_catalog->p0_len, msm_dp_catalog->p0_base, "dp_p0"); } =20 -static inline u32 msm_dp_read_aux(struct msm_dp_catalog_private *catalog, = u32 offset) +static inline u32 msm_dp_read_aux(struct msm_dp_catalog *msm_dp_catalog, u= 32 offset) { - return readl_relaxed(catalog->io.aux.base + offset); + return readl_relaxed(msm_dp_catalog->aux_base + offset); } =20 -static inline void msm_dp_write_aux(struct msm_dp_catalog_private *catalog, +static inline void msm_dp_write_aux(struct msm_dp_catalog *msm_dp_catalog, u32 offset, u32 data) { /* * To make sure aux reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io.aux.base + offset); + writel(data, msm_dp_catalog->aux_base + offset); } =20 -static inline u32 msm_dp_read_ahb(const struct msm_dp_catalog_private *cat= alog, u32 offset) +static inline u32 msm_dp_read_ahb(const struct msm_dp_catalog *msm_dp_cata= log, u32 offset) { - return readl_relaxed(catalog->io.ahb.base + offset); + return readl_relaxed(msm_dp_catalog->ahb_base + offset); } =20 -static inline void msm_dp_write_ahb(struct msm_dp_catalog_private *catalog, +static inline void msm_dp_write_ahb(struct msm_dp_catalog *msm_dp_catalog, u32 offset, u32 data) { /* * To make sure phy reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io.ahb.base + offset); + writel(data, msm_dp_catalog->ahb_base + offset); } =20 -static inline void msm_dp_write_p0(struct msm_dp_catalog_private *catalog, +static inline void msm_dp_write_p0(struct msm_dp_catalog *msm_dp_catalog, u32 offset, u32 data) { /* * To make sure interface reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io.p0.base + offset); + writel(data, msm_dp_catalog->p0_base + offset); } =20 -static inline u32 msm_dp_read_p0(struct msm_dp_catalog_private *catalog, +static inline u32 msm_dp_read_p0(struct msm_dp_catalog *msm_dp_catalog, u32 offset) { /* * To make sure interface reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - return readl_relaxed(catalog->io.p0.base + offset); + return readl_relaxed(msm_dp_catalog->p0_base + offset); } =20 -static inline u32 msm_dp_read_link(struct msm_dp_catalog_private *catalog,= u32 offset) +static inline u32 msm_dp_read_link(struct msm_dp_catalog *msm_dp_catalog, = u32 offset) { - return readl_relaxed(catalog->io.link.base + offset); + return readl_relaxed(msm_dp_catalog->link_base + offset); } =20 -static inline void msm_dp_write_link(struct msm_dp_catalog_private *catalo= g, +static inline void msm_dp_write_link(struct msm_dp_catalog *msm_dp_catalog, u32 offset, u32 data) { /* * To make sure link reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io.link.base + offset); + writel(data, msm_dp_catalog->link_base + offset); } =20 /* aux related catalog functions */ u32 msm_dp_catalog_aux_read_data(struct msm_dp_catalog *msm_dp_catalog) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - return msm_dp_read_aux(catalog, REG_DP_AUX_DATA); + return msm_dp_read_aux(msm_dp_catalog, REG_DP_AUX_DATA); } =20 int msm_dp_catalog_aux_write_data(struct msm_dp_catalog *msm_dp_catalog, u= 32 data) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - msm_dp_write_aux(catalog, REG_DP_AUX_DATA, data); + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_DATA, data); return 0; } =20 int msm_dp_catalog_aux_write_trans(struct msm_dp_catalog *msm_dp_catalog, = u32 data) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - msm_dp_write_aux(catalog, REG_DP_AUX_TRANS_CTRL, data); + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_TRANS_CTRL, data); return 0; } =20 int msm_dp_catalog_aux_clear_trans(struct msm_dp_catalog *msm_dp_catalog, = bool read) { u32 data; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); =20 if (read) { - data =3D msm_dp_read_aux(catalog, REG_DP_AUX_TRANS_CTRL); + data =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_AUX_TRANS_CTRL); data &=3D ~DP_AUX_TRANS_CTRL_GO; - msm_dp_write_aux(catalog, REG_DP_AUX_TRANS_CTRL, data); + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_TRANS_CTRL, data); } else { - msm_dp_write_aux(catalog, REG_DP_AUX_TRANS_CTRL, 0); + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_TRANS_CTRL, 0); } return 0; } =20 int msm_dp_catalog_aux_clear_hw_interrupts(struct msm_dp_catalog *msm_dp_c= atalog) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - msm_dp_read_aux(catalog, REG_DP_PHY_AUX_INTERRUPT_STATUS); - msm_dp_write_aux(catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x1f); - msm_dp_write_aux(catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x9f); - msm_dp_write_aux(catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0); + msm_dp_read_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_STATUS); + msm_dp_write_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x1f); + msm_dp_write_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x9f); + msm_dp_write_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0); return 0; } =20 @@ -229,47 +202,41 @@ int msm_dp_catalog_aux_clear_hw_interrupts(struct msm= _dp_catalog *msm_dp_catalog void msm_dp_catalog_aux_reset(struct msm_dp_catalog *msm_dp_catalog) { u32 aux_ctrl; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); =20 - aux_ctrl =3D msm_dp_read_aux(catalog, REG_DP_AUX_CTRL); + aux_ctrl =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_AUX_CTRL); =20 aux_ctrl |=3D DP_AUX_CTRL_RESET; - msm_dp_write_aux(catalog, REG_DP_AUX_CTRL, aux_ctrl); + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_CTRL, aux_ctrl); usleep_range(1000, 1100); /* h/w recommended delay */ =20 aux_ctrl &=3D ~DP_AUX_CTRL_RESET; - msm_dp_write_aux(catalog, REG_DP_AUX_CTRL, aux_ctrl); + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_CTRL, aux_ctrl); } =20 void msm_dp_catalog_aux_enable(struct msm_dp_catalog *msm_dp_catalog, bool= enable) { u32 aux_ctrl; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); =20 - aux_ctrl =3D msm_dp_read_aux(catalog, REG_DP_AUX_CTRL); + aux_ctrl =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_AUX_CTRL); =20 if (enable) { - msm_dp_write_aux(catalog, REG_DP_TIMEOUT_COUNT, 0xffff); - msm_dp_write_aux(catalog, REG_DP_AUX_LIMITS, 0xffff); + msm_dp_write_aux(msm_dp_catalog, REG_DP_TIMEOUT_COUNT, 0xffff); + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_LIMITS, 0xffff); aux_ctrl |=3D DP_AUX_CTRL_ENABLE; } else { aux_ctrl &=3D ~DP_AUX_CTRL_ENABLE; } =20 - msm_dp_write_aux(catalog, REG_DP_AUX_CTRL, aux_ctrl); + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_CTRL, aux_ctrl); } =20 int msm_dp_catalog_aux_wait_for_hpd_connect_state(struct msm_dp_catalog *m= sm_dp_catalog, unsigned long wait_us) { u32 state; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); =20 /* poll for hpd connected status every 2ms and timeout after wait_us */ - return readl_poll_timeout(catalog->io.aux.base + + return readl_poll_timeout(msm_dp_catalog->aux_base + REG_DP_DP_HPD_INT_STATUS, state, state & DP_DP_HPD_STATE_STATUS_CONNECTED, min(wait_us, 2000), wait_us); @@ -277,15 +244,13 @@ int msm_dp_catalog_aux_wait_for_hpd_connect_state(str= uct msm_dp_catalog *msm_dp_ =20 u32 msm_dp_catalog_aux_get_irq(struct msm_dp_catalog *msm_dp_catalog) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); u32 intr, intr_ack; =20 - intr =3D msm_dp_read_ahb(catalog, REG_DP_INTR_STATUS); + intr =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_INTR_STATUS); intr &=3D ~DP_INTERRUPT_STATUS1_MASK; intr_ack =3D (intr & DP_INTERRUPT_STATUS1) << DP_INTERRUPT_STATUS_ACK_SHIFT; - msm_dp_write_ahb(catalog, REG_DP_INTR_STATUS, intr_ack | + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, intr_ack | DP_INTERRUPT_STATUS1_MASK); =20 return intr; @@ -297,20 +262,14 @@ void msm_dp_catalog_ctrl_update_transfer_unit(struct = msm_dp_catalog *msm_dp_cata u32 msm_dp_tu, u32 valid_boundary, u32 valid_boundary2) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - msm_dp_write_link(catalog, REG_DP_VALID_BOUNDARY, valid_boundary); - msm_dp_write_link(catalog, REG_DP_TU, msm_dp_tu); - msm_dp_write_link(catalog, REG_DP_VALID_BOUNDARY_2, valid_boundary2); + msm_dp_write_link(msm_dp_catalog, REG_DP_VALID_BOUNDARY, valid_boundary); + msm_dp_write_link(msm_dp_catalog, REG_DP_TU, msm_dp_tu); + msm_dp_write_link(msm_dp_catalog, REG_DP_VALID_BOUNDARY_2, valid_boundary= 2); } =20 void msm_dp_catalog_ctrl_state_ctrl(struct msm_dp_catalog *msm_dp_catalog,= u32 state) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - msm_dp_write_link(catalog, REG_DP_STATE_CTRL, state); + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, state); } =20 void msm_dp_catalog_ctrl_config_ctrl(struct msm_dp_catalog *msm_dp_catalog= , u32 cfg) @@ -320,13 +279,11 @@ void msm_dp_catalog_ctrl_config_ctrl(struct msm_dp_ca= talog *msm_dp_catalog, u32 =20 drm_dbg_dp(catalog->drm_dev, "DP_CONFIGURATION_CTRL=3D0x%x\n", cfg); =20 - msm_dp_write_link(catalog, REG_DP_CONFIGURATION_CTRL, cfg); + msm_dp_write_link(msm_dp_catalog, REG_DP_CONFIGURATION_CTRL, cfg); } =20 void msm_dp_catalog_ctrl_lane_mapping(struct msm_dp_catalog *msm_dp_catalo= g) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); u32 ln_0 =3D 0, ln_1 =3D 1, ln_2 =3D 2, ln_3 =3D 3; /* One-to-One mapping= */ u32 ln_mapping; =20 @@ -335,7 +292,7 @@ void msm_dp_catalog_ctrl_lane_mapping(struct msm_dp_cat= alog *msm_dp_catalog) ln_mapping |=3D ln_2 << LANE2_MAPPING_SHIFT; ln_mapping |=3D ln_3 << LANE3_MAPPING_SHIFT; =20 - msm_dp_write_link(catalog, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, + msm_dp_write_link(msm_dp_catalog, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, ln_mapping); } =20 @@ -343,17 +300,15 @@ void msm_dp_catalog_ctrl_psr_mainlink_enable(struct m= sm_dp_catalog *msm_dp_catal bool enable) { u32 val; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); =20 - val =3D msm_dp_read_link(catalog, REG_DP_MAINLINK_CTRL); + val =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); =20 if (enable) val |=3D DP_MAINLINK_CTRL_ENABLE; else val &=3D ~DP_MAINLINK_CTRL_ENABLE; =20 - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, val); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, val); } =20 void msm_dp_catalog_ctrl_mainlink_ctrl(struct msm_dp_catalog *msm_dp_catal= og, @@ -369,25 +324,25 @@ void msm_dp_catalog_ctrl_mainlink_ctrl(struct msm_dp_= catalog *msm_dp_catalog, * To make sure link reg writes happens before other operation, * msm_dp_write_link() function uses writel() */ - mainlink_ctrl =3D msm_dp_read_link(catalog, REG_DP_MAINLINK_CTRL); + mainlink_ctrl =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); =20 mainlink_ctrl &=3D ~(DP_MAINLINK_CTRL_RESET | DP_MAINLINK_CTRL_ENABLE); - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); =20 mainlink_ctrl |=3D DP_MAINLINK_CTRL_RESET; - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); =20 mainlink_ctrl &=3D ~DP_MAINLINK_CTRL_RESET; - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); =20 mainlink_ctrl |=3D (DP_MAINLINK_CTRL_ENABLE | DP_MAINLINK_FB_BOUNDARY_SEL); - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } else { - mainlink_ctrl =3D msm_dp_read_link(catalog, REG_DP_MAINLINK_CTRL); + mainlink_ctrl =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); mainlink_ctrl &=3D ~DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } } =20 @@ -399,7 +354,7 @@ void msm_dp_catalog_ctrl_config_misc(struct msm_dp_cata= log *msm_dp_catalog, struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, msm_dp_catalog); =20 - misc_val =3D msm_dp_read_link(catalog, REG_DP_MISC1_MISC0); + misc_val =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MISC1_MISC0); =20 /* clear bpp bits */ misc_val &=3D ~(0x07 << DP_MISC0_TEST_BITS_DEPTH_SHIFT); @@ -409,23 +364,21 @@ void msm_dp_catalog_ctrl_config_misc(struct msm_dp_ca= talog *msm_dp_catalog, misc_val |=3D DP_MISC0_SYNCHRONOUS_CLK; =20 drm_dbg_dp(catalog->drm_dev, "misc settings =3D 0x%x\n", misc_val); - msm_dp_write_link(catalog, REG_DP_MISC1_MISC0, misc_val); + msm_dp_write_link(msm_dp_catalog, REG_DP_MISC1_MISC0, misc_val); } =20 void msm_dp_catalog_setup_peripheral_flush(struct msm_dp_catalog *msm_dp_c= atalog) { u32 mainlink_ctrl; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); =20 - mainlink_ctrl =3D msm_dp_read_link(catalog, REG_DP_MAINLINK_CTRL); + mainlink_ctrl =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); =20 if (msm_dp_catalog->hw_revision >=3D DP_HW_VERSION_1_2) mainlink_ctrl |=3D DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE; else mainlink_ctrl |=3D DP_MAINLINK_FLUSH_MODE_UPDATE_SDP; =20 - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } =20 void msm_dp_catalog_ctrl_config_msa(struct msm_dp_catalog *msm_dp_catalog, @@ -483,8 +436,8 @@ void msm_dp_catalog_ctrl_config_msa(struct msm_dp_catal= og *msm_dp_catalog, nvid *=3D 3; =20 drm_dbg_dp(catalog->drm_dev, "mvid=3D0x%x, nvid=3D0x%x\n", mvid, nvid); - msm_dp_write_link(catalog, REG_DP_SOFTWARE_MVID, mvid); - msm_dp_write_link(catalog, REG_DP_SOFTWARE_NVID, nvid); + msm_dp_write_link(msm_dp_catalog, REG_DP_SOFTWARE_MVID, mvid); + msm_dp_write_link(msm_dp_catalog, REG_DP_SOFTWARE_NVID, nvid); } =20 int msm_dp_catalog_ctrl_set_pattern_state_bit(struct msm_dp_catalog *msm_d= p_catalog, @@ -502,7 +455,7 @@ int msm_dp_catalog_ctrl_set_pattern_state_bit(struct ms= m_dp_catalog *msm_dp_cata bit =3D BIT(state_bit - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT; =20 /* Poll for mainlink ready status */ - ret =3D readx_poll_timeout(readl, catalog->io.link.base + + ret =3D readx_poll_timeout(readl, msm_dp_catalog->link_base + REG_DP_MAINLINK_READY, data, data & bit, POLLING_SLEEP_US, POLLING_TIMEOUT_US); @@ -528,31 +481,27 @@ int msm_dp_catalog_ctrl_set_pattern_state_bit(struct = msm_dp_catalog *msm_dp_cata void msm_dp_catalog_ctrl_reset(struct msm_dp_catalog *msm_dp_catalog) { u32 sw_reset; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); =20 - sw_reset =3D msm_dp_read_ahb(catalog, REG_DP_SW_RESET); + sw_reset =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_SW_RESET); =20 sw_reset |=3D DP_SW_RESET; - msm_dp_write_ahb(catalog, REG_DP_SW_RESET, sw_reset); + msm_dp_write_ahb(msm_dp_catalog, REG_DP_SW_RESET, sw_reset); usleep_range(1000, 1100); /* h/w recommended delay */ =20 sw_reset &=3D ~DP_SW_RESET; - msm_dp_write_ahb(catalog, REG_DP_SW_RESET, sw_reset); + msm_dp_write_ahb(msm_dp_catalog, REG_DP_SW_RESET, sw_reset); =20 if (!msm_dp_catalog->hw_revision) - msm_dp_catalog->hw_revision =3D msm_dp_read_ahb(catalog, REG_DP_HW_VERSI= ON); + msm_dp_catalog->hw_revision =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_H= W_VERSION); } =20 bool msm_dp_catalog_ctrl_mainlink_ready(struct msm_dp_catalog *msm_dp_cata= log) { u32 data; int ret; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); =20 /* Poll for mainlink ready status */ - ret =3D readl_poll_timeout(catalog->io.link.base + + ret =3D readl_poll_timeout(msm_dp_catalog->link_base + REG_DP_MAINLINK_READY, data, data & DP_MAINLINK_READY_FOR_VIDEO, POLLING_SLEEP_US, POLLING_TIMEOUT_US); @@ -567,17 +516,14 @@ bool msm_dp_catalog_ctrl_mainlink_ready(struct msm_dp= _catalog *msm_dp_catalog) void msm_dp_catalog_ctrl_enable_irq(struct msm_dp_catalog *msm_dp_catalog, bool enable) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - if (enable) { - msm_dp_write_ahb(catalog, REG_DP_INTR_STATUS, + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, DP_INTERRUPT_STATUS1_MASK); - msm_dp_write_ahb(catalog, REG_DP_INTR_STATUS2, + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2, DP_INTERRUPT_STATUS2_MASK); } else { - msm_dp_write_ahb(catalog, REG_DP_INTR_STATUS, 0x00); - msm_dp_write_ahb(catalog, REG_DP_INTR_STATUS2, 0x00); + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, 0x00); + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2, 0x00); } } =20 @@ -587,73 +533,63 @@ void msm_dp_catalog_hpd_config_intr(struct msm_dp_cat= alog *msm_dp_catalog, struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, msm_dp_catalog); =20 - u32 config =3D msm_dp_read_aux(catalog, REG_DP_DP_HPD_INT_MASK); + u32 config =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK); =20 config =3D (en ? config | intr_mask : config & ~intr_mask); =20 drm_dbg_dp(catalog->drm_dev, "intr_mask=3D%#x config=3D%#x\n", intr_mask, config); - msm_dp_write_aux(catalog, REG_DP_DP_HPD_INT_MASK, + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK, config & DP_DP_HPD_INT_MASK); } =20 void msm_dp_catalog_ctrl_hpd_enable(struct msm_dp_catalog *msm_dp_catalog) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - u32 reftimer =3D msm_dp_read_aux(catalog, REG_DP_DP_HPD_REFTIMER); + u32 reftimer =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER); =20 /* Configure REFTIMER and enable it */ reftimer |=3D DP_DP_HPD_REFTIMER_ENABLE; - msm_dp_write_aux(catalog, REG_DP_DP_HPD_REFTIMER, reftimer); + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER, reftimer); =20 /* Enable HPD */ - msm_dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_EN); + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_E= N); } =20 void msm_dp_catalog_ctrl_hpd_disable(struct msm_dp_catalog *msm_dp_catalog) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - u32 reftimer =3D msm_dp_read_aux(catalog, REG_DP_DP_HPD_REFTIMER); + u32 reftimer =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER); =20 reftimer &=3D ~DP_DP_HPD_REFTIMER_ENABLE; - msm_dp_write_aux(catalog, REG_DP_DP_HPD_REFTIMER, reftimer); + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER, reftimer); =20 - msm_dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, 0); + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_CTRL, 0); } =20 -static void msm_dp_catalog_enable_sdp(struct msm_dp_catalog_private *catal= og) +static void msm_dp_catalog_enable_sdp(struct msm_dp_catalog *msm_dp_catalo= g) { /* trigger sdp */ - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG3, UPDATE_SDP); - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x0); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, UPDATE_SDP); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, 0x0); } =20 void msm_dp_catalog_ctrl_config_psr(struct msm_dp_catalog *msm_dp_catalog) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); u32 config; =20 /* enable PSR1 function */ - config =3D msm_dp_read_link(catalog, REG_PSR_CONFIG); + config =3D msm_dp_read_link(msm_dp_catalog, REG_PSR_CONFIG); config |=3D PSR1_SUPPORTED; - msm_dp_write_link(catalog, REG_PSR_CONFIG, config); + msm_dp_write_link(msm_dp_catalog, REG_PSR_CONFIG, config); =20 - msm_dp_write_ahb(catalog, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4); - msm_dp_catalog_enable_sdp(catalog); + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4); + msm_dp_catalog_enable_sdp(msm_dp_catalog); } =20 void msm_dp_catalog_ctrl_set_psr(struct msm_dp_catalog *msm_dp_catalog, bo= ol enter) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); u32 cmd; =20 - cmd =3D msm_dp_read_link(catalog, REG_PSR_CMD); + cmd =3D msm_dp_read_link(msm_dp_catalog, REG_PSR_CMD); =20 cmd &=3D ~(PSR_ENTER | PSR_EXIT); =20 @@ -662,8 +598,8 @@ void msm_dp_catalog_ctrl_set_psr(struct msm_dp_catalog = *msm_dp_catalog, bool ent else cmd |=3D PSR_EXIT; =20 - msm_dp_catalog_enable_sdp(catalog); - msm_dp_write_link(catalog, REG_PSR_CMD, cmd); + msm_dp_catalog_enable_sdp(msm_dp_catalog); + msm_dp_write_link(msm_dp_catalog, REG_PSR_CMD, cmd); } =20 u32 msm_dp_catalog_link_is_connected(struct msm_dp_catalog *msm_dp_catalog) @@ -672,7 +608,7 @@ u32 msm_dp_catalog_link_is_connected(struct msm_dp_cata= log *msm_dp_catalog) struct msm_dp_catalog_private, msm_dp_catalog); u32 status; =20 - status =3D msm_dp_read_aux(catalog, REG_DP_DP_HPD_INT_STATUS); + status =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_STATUS); drm_dbg_dp(catalog->drm_dev, "aux status: %#x\n", status); status >>=3D DP_DP_HPD_STATE_STATUS_BITS_SHIFT; status &=3D DP_DP_HPD_STATE_STATUS_BITS_MASK; @@ -682,14 +618,12 @@ u32 msm_dp_catalog_link_is_connected(struct msm_dp_ca= talog *msm_dp_catalog) =20 u32 msm_dp_catalog_hpd_get_intr_status(struct msm_dp_catalog *msm_dp_catal= og) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); int isr, mask; =20 - isr =3D msm_dp_read_aux(catalog, REG_DP_DP_HPD_INT_STATUS); - msm_dp_write_aux(catalog, REG_DP_DP_HPD_INT_ACK, + isr =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_STATUS); + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_ACK, (isr & DP_DP_HPD_INT_MASK)); - mask =3D msm_dp_read_aux(catalog, REG_DP_DP_HPD_INT_MASK); + mask =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK); =20 /* * We only want to return interrupts that are unmasked to the caller. @@ -703,29 +637,25 @@ u32 msm_dp_catalog_hpd_get_intr_status(struct msm_dp_= catalog *msm_dp_catalog) =20 u32 msm_dp_catalog_ctrl_read_psr_interrupt_status(struct msm_dp_catalog *m= sm_dp_catalog) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); u32 intr, intr_ack; =20 - intr =3D msm_dp_read_ahb(catalog, REG_DP_INTR_STATUS4); + intr =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_INTR_STATUS4); intr_ack =3D (intr & DP_INTERRUPT_STATUS4) << DP_INTERRUPT_STATUS_ACK_SHIFT; - msm_dp_write_ahb(catalog, REG_DP_INTR_STATUS4, intr_ack); + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS4, intr_ack); =20 return intr; } =20 int msm_dp_catalog_ctrl_get_interrupt(struct msm_dp_catalog *msm_dp_catalo= g) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); u32 intr, intr_ack; =20 - intr =3D msm_dp_read_ahb(catalog, REG_DP_INTR_STATUS2); + intr =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2); intr &=3D ~DP_INTERRUPT_STATUS2_MASK; intr_ack =3D (intr & DP_INTERRUPT_STATUS2) << DP_INTERRUPT_STATUS_ACK_SHIFT; - msm_dp_write_ahb(catalog, REG_DP_INTR_STATUS2, + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2, intr_ack | DP_INTERRUPT_STATUS2_MASK); =20 return intr; @@ -733,13 +663,10 @@ int msm_dp_catalog_ctrl_get_interrupt(struct msm_dp_c= atalog *msm_dp_catalog) =20 void msm_dp_catalog_ctrl_phy_reset(struct msm_dp_catalog *msm_dp_catalog) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - msm_dp_write_ahb(catalog, REG_DP_PHY_CTRL, + msm_dp_write_ahb(msm_dp_catalog, REG_DP_PHY_CTRL, DP_PHY_CTRL_SW_RESET | DP_PHY_CTRL_SW_RESET_PLL); usleep_range(1000, 1100); /* h/w recommended delay */ - msm_dp_write_ahb(catalog, REG_DP_PHY_CTRL, 0x0); + msm_dp_write_ahb(msm_dp_catalog, REG_DP_PHY_CTRL, 0x0); } =20 void msm_dp_catalog_ctrl_send_phy_pattern(struct msm_dp_catalog *msm_dp_ca= talog, @@ -750,66 +677,66 @@ void msm_dp_catalog_ctrl_send_phy_pattern(struct msm_= dp_catalog *msm_dp_catalog, u32 value =3D 0x0; =20 /* Make sure to clear the current pattern before starting a new one */ - msm_dp_write_link(catalog, REG_DP_STATE_CTRL, 0x0); + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, 0x0); =20 drm_dbg_dp(catalog->drm_dev, "pattern: %#x\n", pattern); switch (pattern) { case DP_PHY_TEST_PATTERN_D10_2: - msm_dp_write_link(catalog, REG_DP_STATE_CTRL, + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_LINK_TRAINING_PATTERN1); break; case DP_PHY_TEST_PATTERN_ERROR_COUNT: value &=3D ~(1 << 16); - msm_dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value); value |=3D SCRAMBLER_RESET_COUNT_VALUE; - msm_dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value); - msm_dp_write_link(catalog, REG_DP_MAINLINK_LEVELS, + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_LEVELS, DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); - msm_dp_write_link(catalog, REG_DP_STATE_CTRL, + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); break; case DP_PHY_TEST_PATTERN_PRBS7: - msm_dp_write_link(catalog, REG_DP_STATE_CTRL, + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_LINK_PRBS7); break; case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: - msm_dp_write_link(catalog, REG_DP_STATE_CTRL, + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN); /* 00111110000011111000001111100000 */ - msm_dp_write_link(catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0, + msm_dp_write_link(msm_dp_catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0, 0x3E0F83E0); /* 00001111100000111110000011111000 */ - msm_dp_write_link(catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1, + msm_dp_write_link(msm_dp_catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1, 0x0F83E0F8); /* 1111100000111110 */ - msm_dp_write_link(catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2, + msm_dp_write_link(msm_dp_catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2, 0x0000F83E); break; case DP_PHY_TEST_PATTERN_CP2520: - value =3D msm_dp_read_link(catalog, REG_DP_MAINLINK_CTRL); + value =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); value &=3D ~DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER; - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, value); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, value); =20 value =3D DP_HBR2_ERM_PATTERN; - msm_dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value); value |=3D SCRAMBLER_RESET_COUNT_VALUE; - msm_dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value); - msm_dp_write_link(catalog, REG_DP_MAINLINK_LEVELS, + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_LEVELS, DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); - msm_dp_write_link(catalog, REG_DP_STATE_CTRL, + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); - value =3D msm_dp_read_link(catalog, REG_DP_MAINLINK_CTRL); + value =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); value |=3D DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, value); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, value); break; case DP_PHY_TEST_PATTERN_SEL_MASK: - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, DP_MAINLINK_CTRL_ENABLE); - msm_dp_write_link(catalog, REG_DP_STATE_CTRL, + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_LINK_TRAINING_PATTERN4); break; default: @@ -821,26 +748,21 @@ void msm_dp_catalog_ctrl_send_phy_pattern(struct msm_= dp_catalog *msm_dp_catalog, =20 u32 msm_dp_catalog_ctrl_read_phy_pattern(struct msm_dp_catalog *msm_dp_cat= alog) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - return msm_dp_read_link(catalog, REG_DP_MAINLINK_READY); + return msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_READY); } =20 /* panel related catalog functions */ int msm_dp_catalog_panel_timing_cfg(struct msm_dp_catalog *msm_dp_catalog,= u32 total, u32 sync_start, u32 width_blanking, u32 msm_dp_active) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); u32 reg; =20 - msm_dp_write_link(catalog, REG_DP_TOTAL_HOR_VER, total); - msm_dp_write_link(catalog, REG_DP_START_HOR_VER_FROM_SYNC, sync_start); - msm_dp_write_link(catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, width_blank= ing); - msm_dp_write_link(catalog, REG_DP_ACTIVE_HOR_VER, msm_dp_active); + msm_dp_write_link(msm_dp_catalog, REG_DP_TOTAL_HOR_VER, total); + msm_dp_write_link(msm_dp_catalog, REG_DP_START_HOR_VER_FROM_SYNC, sync_st= art); + msm_dp_write_link(msm_dp_catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, widt= h_blanking); + msm_dp_write_link(msm_dp_catalog, REG_DP_ACTIVE_HOR_VER, msm_dp_active); =20 - reg =3D msm_dp_read_p0(catalog, MMSS_DP_INTF_CONFIG); + reg =3D msm_dp_read_p0(msm_dp_catalog, MMSS_DP_INTF_CONFIG); =20 if (msm_dp_catalog->wide_bus_en) reg |=3D DP_INTF_CONFIG_DATABUS_WIDEN; @@ -850,43 +772,38 @@ int msm_dp_catalog_panel_timing_cfg(struct msm_dp_cat= alog *msm_dp_catalog, u32 t =20 DRM_DEBUG_DP("wide_bus_en=3D%d reg=3D%#x\n", msm_dp_catalog->wide_bus_en,= reg); =20 - msm_dp_write_p0(catalog, MMSS_DP_INTF_CONFIG, reg); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_CONFIG, reg); return 0; } =20 static void msm_dp_catalog_panel_send_vsc_sdp(struct msm_dp_catalog *msm_d= p_catalog, struct dp_sdp *vsc_sdp) { - struct msm_dp_catalog_private *catalog; u32 header[2]; u32 val; int i; =20 - catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, m= sm_dp_catalog); - msm_dp_utils_pack_sdp_header(&vsc_sdp->sdp_header, header); =20 - msm_dp_write_link(catalog, MMSS_DP_GENERIC0_0, header[0]); - msm_dp_write_link(catalog, MMSS_DP_GENERIC0_1, header[1]); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_0, header[0]); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_1, header[1]); =20 for (i =3D 0; i < sizeof(vsc_sdp->db); i +=3D 4) { val =3D ((vsc_sdp->db[i]) | (vsc_sdp->db[i + 1] << 8) | (vsc_sdp->db[i += 2] << 16) | (vsc_sdp->db[i + 3] << 24)); - msm_dp_write_link(catalog, MMSS_DP_GENERIC0_2 + i, val); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_2 + i, val); } } =20 static void msm_dp_catalog_panel_update_sdp(struct msm_dp_catalog *msm_dp_= catalog) { - struct msm_dp_catalog_private *catalog; u32 hw_revision; =20 - catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, m= sm_dp_catalog); hw_revision =3D msm_dp_catalog->hw_revision; =20 if (hw_revision < DP_HW_VERSION_1_2 && hw_revision >=3D DP_HW_VERSION_1_0) { - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x01); - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x00); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, 0x01); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, 0x00); } } =20 @@ -897,15 +814,15 @@ void msm_dp_catalog_panel_enable_vsc_sdp(struct msm_d= p_catalog *msm_dp_catalog, =20 catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, m= sm_dp_catalog); =20 - cfg =3D msm_dp_read_link(catalog, MMSS_DP_SDP_CFG); - cfg2 =3D msm_dp_read_link(catalog, MMSS_DP_SDP_CFG2); - misc =3D msm_dp_read_link(catalog, REG_DP_MISC1_MISC0); + cfg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG); + cfg2 =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2); + misc =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MISC1_MISC0); =20 cfg |=3D GEN0_SDP_EN; - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG, cfg); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, cfg); =20 cfg2 |=3D GENERIC0_SDPSIZE_VALID; - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG2, cfg2); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, cfg2); =20 msm_dp_catalog_panel_send_vsc_sdp(msm_dp_catalog, vsc_sdp); =20 @@ -915,7 +832,7 @@ void msm_dp_catalog_panel_enable_vsc_sdp(struct msm_dp_= catalog *msm_dp_catalog, drm_dbg_dp(catalog->drm_dev, "vsc sdp enable=3D1\n"); =20 pr_debug("misc settings =3D 0x%x\n", misc); - msm_dp_write_link(catalog, REG_DP_MISC1_MISC0, misc); + msm_dp_write_link(msm_dp_catalog, REG_DP_MISC1_MISC0, misc); =20 msm_dp_catalog_panel_update_sdp(msm_dp_catalog); } @@ -927,15 +844,15 @@ void msm_dp_catalog_panel_disable_vsc_sdp(struct msm_= dp_catalog *msm_dp_catalog) =20 catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, m= sm_dp_catalog); =20 - cfg =3D msm_dp_read_link(catalog, MMSS_DP_SDP_CFG); - cfg2 =3D msm_dp_read_link(catalog, MMSS_DP_SDP_CFG2); - misc =3D msm_dp_read_link(catalog, REG_DP_MISC1_MISC0); + cfg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG); + cfg2 =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2); + misc =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MISC1_MISC0); =20 cfg &=3D ~GEN0_SDP_EN; - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG, cfg); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, cfg); =20 cfg2 &=3D ~GENERIC0_SDPSIZE_VALID; - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG2, cfg2); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, cfg2); =20 /* switch back to MSA */ misc &=3D ~DP_MISC1_VSC_SDP; @@ -943,7 +860,7 @@ void msm_dp_catalog_panel_disable_vsc_sdp(struct msm_dp= _catalog *msm_dp_catalog) drm_dbg_dp(catalog->drm_dev, "vsc sdp enable=3D0\n"); =20 pr_debug("misc settings =3D 0x%x\n", misc); - msm_dp_write_link(catalog, REG_DP_MISC1_MISC0, misc); + msm_dp_write_link(msm_dp_catalog, REG_DP_MISC1_MISC0, misc); =20 msm_dp_catalog_panel_update_sdp(msm_dp_catalog); } @@ -984,53 +901,47 @@ void msm_dp_catalog_panel_tpg_enable(struct msm_dp_ca= talog *msm_dp_catalog, display_hctl =3D (hsync_end_x << 16) | hsync_start_x; =20 =20 - msm_dp_write_p0(catalog, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); - msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period * + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_perio= d * hsync_period); - msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width * + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync= _width * hsync_period); - msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); - msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_HCTL, 0); - msm_dp_write_p0(catalog, MMSS_INTF_DISPLAY_V_START_F0, display_v_start); - msm_dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end); - msm_dp_write_p0(catalog, MMSS_INTF_DISPLAY_V_START_F1, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_POLARITY_CTL, 0); - - msm_dp_write_p0(catalog, MMSS_DP_TPG_MAIN_CONTROL, + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_ACTIVE_HCTL, 0); + msm_dp_write_p0(msm_dp_catalog, MMSS_INTF_DISPLAY_V_START_F0, display_v_s= tart); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_= end); + msm_dp_write_p0(msm_dp_catalog, MMSS_INTF_DISPLAY_V_START_F1, 0); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_POLARITY_CTL, 0); + + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_TPG_MAIN_CONTROL, DP_TPG_CHECKERED_RECT_PATTERN); - msm_dp_write_p0(catalog, MMSS_DP_TPG_VIDEO_CONFIG, + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_TPG_VIDEO_CONFIG, DP_TPG_VIDEO_CONFIG_BPP_8BIT | DP_TPG_VIDEO_CONFIG_RGB); - msm_dp_write_p0(catalog, MMSS_DP_BIST_ENABLE, + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_BIST_ENABLE, DP_BIST_ENABLE_DPBIST_EN); - msm_dp_write_p0(catalog, MMSS_DP_TIMING_ENGINE_EN, + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_TIMING_ENGINE_EN, DP_TIMING_ENGINE_EN_EN); drm_dbg_dp(catalog->drm_dev, "%s: enabled tpg\n", __func__); } =20 void msm_dp_catalog_panel_tpg_disable(struct msm_dp_catalog *msm_dp_catalo= g) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - msm_dp_write_p0(catalog, MMSS_DP_TPG_MAIN_CONTROL, 0x0); - msm_dp_write_p0(catalog, MMSS_DP_BIST_ENABLE, 0x0); - msm_dp_write_p0(catalog, MMSS_DP_TIMING_ENGINE_EN, 0x0); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_TPG_MAIN_CONTROL, 0x0); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_BIST_ENABLE, 0x0); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_TIMING_ENGINE_EN, 0x0); } =20 void msm_dp_catalog_panel_clear_dsc_dto(struct msm_dp_catalog *msm_dp_cata= log) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - msm_dp_write_p0(catalog, MMSS_DP_DSC_DTO, 0x0); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_DSC_DTO, 0x0); } =20 static void __iomem *msm_dp_ioremap(struct platform_device *pdev, int idx,= size_t *len) @@ -1047,15 +958,15 @@ static void __iomem *msm_dp_ioremap(struct platform_= device *pdev, int idx, size_ =20 static int msm_dp_catalog_get_io(struct msm_dp_catalog_private *catalog) { + struct msm_dp_catalog *msm_dp_catalog =3D &catalog->msm_dp_catalog; struct platform_device *pdev =3D to_platform_device(catalog->dev); - struct dss_io_data *dss =3D &catalog->io; =20 - dss->ahb.base =3D msm_dp_ioremap(pdev, 0, &dss->ahb.len); - if (IS_ERR(dss->ahb.base)) - return PTR_ERR(dss->ahb.base); + msm_dp_catalog->ahb_base =3D msm_dp_ioremap(pdev, 0, &msm_dp_catalog->ahb= _len); + if (IS_ERR(msm_dp_catalog->ahb_base)) + return PTR_ERR(msm_dp_catalog->ahb_base); =20 - dss->aux.base =3D msm_dp_ioremap(pdev, 1, &dss->aux.len); - if (IS_ERR(dss->aux.base)) { + msm_dp_catalog->aux_base =3D msm_dp_ioremap(pdev, 1, &msm_dp_catalog->aux= _len); + if (IS_ERR(msm_dp_catalog->aux_base)) { /* * The initial binding had a single reg, but in order to * support variation in the sub-region sizes this was split. @@ -1063,34 +974,35 @@ static int msm_dp_catalog_get_io(struct msm_dp_catal= og_private *catalog) * reg is specified, so fill in the sub-region offsets and * lengths based on this single region. */ - if (PTR_ERR(dss->aux.base) =3D=3D -EINVAL) { - if (dss->ahb.len < DP_DEFAULT_P0_OFFSET + DP_DEFAULT_P0_SIZE) { + if (PTR_ERR(msm_dp_catalog->aux_base) =3D=3D -EINVAL) { + if (msm_dp_catalog->ahb_len < DP_DEFAULT_P0_OFFSET + DP_DEFAULT_P0_SIZE= ) { DRM_ERROR("legacy memory region not large enough\n"); return -EINVAL; } =20 - dss->ahb.len =3D DP_DEFAULT_AHB_SIZE; - dss->aux.base =3D dss->ahb.base + DP_DEFAULT_AUX_OFFSET; - dss->aux.len =3D DP_DEFAULT_AUX_SIZE; - dss->link.base =3D dss->ahb.base + DP_DEFAULT_LINK_OFFSET; - dss->link.len =3D DP_DEFAULT_LINK_SIZE; - dss->p0.base =3D dss->ahb.base + DP_DEFAULT_P0_OFFSET; - dss->p0.len =3D DP_DEFAULT_P0_SIZE; + msm_dp_catalog->ahb_len =3D DP_DEFAULT_AHB_SIZE; + msm_dp_catalog->aux_base =3D msm_dp_catalog->ahb_base + DP_DEFAULT_AUX_= OFFSET; + msm_dp_catalog->aux_len =3D DP_DEFAULT_AUX_SIZE; + msm_dp_catalog->link_base =3D msm_dp_catalog->ahb_base + + DP_DEFAULT_LINK_OFFSET; + msm_dp_catalog->link_len =3D DP_DEFAULT_LINK_SIZE; + msm_dp_catalog->p0_base =3D msm_dp_catalog->ahb_base + DP_DEFAULT_P0_OF= FSET; + msm_dp_catalog->p0_len =3D DP_DEFAULT_P0_SIZE; } else { - DRM_ERROR("unable to remap aux region: %pe\n", dss->aux.base); - return PTR_ERR(dss->aux.base); + DRM_ERROR("unable to remap aux region: %pe\n", msm_dp_catalog->aux_base= ); + return PTR_ERR(msm_dp_catalog->aux_base); } } else { - dss->link.base =3D msm_dp_ioremap(pdev, 2, &dss->link.len); - if (IS_ERR(dss->link.base)) { - DRM_ERROR("unable to remap link region: %pe\n", dss->link.base); - return PTR_ERR(dss->link.base); + msm_dp_catalog->link_base =3D msm_dp_ioremap(pdev, 2, &msm_dp_catalog->l= ink_len); + if (IS_ERR(msm_dp_catalog->link_base)) { + DRM_ERROR("unable to remap link region: %pe\n", msm_dp_catalog->link_ba= se); + return PTR_ERR(msm_dp_catalog->link_base); } =20 - dss->p0.base =3D msm_dp_ioremap(pdev, 3, &dss->p0.len); - if (IS_ERR(dss->p0.base)) { - DRM_ERROR("unable to remap p0 region: %pe\n", dss->p0.base); - return PTR_ERR(dss->p0.base); + msm_dp_catalog->p0_base =3D msm_dp_ioremap(pdev, 3, &msm_dp_catalog->p0_= len); + if (IS_ERR(msm_dp_catalog->p0_base)) { + DRM_ERROR("unable to remap p0 region: %pe\n", msm_dp_catalog->p0_base); + return PTR_ERR(msm_dp_catalog->p0_base); } } =20 @@ -1118,72 +1030,62 @@ struct msm_dp_catalog *msm_dp_catalog_get(struct de= vice *dev) void msm_dp_catalog_write_audio_stream(struct msm_dp_catalog *msm_dp_catal= og, struct dp_sdp_header *sdp_hdr) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); u32 header[2]; =20 msm_dp_utils_pack_sdp_header(sdp_hdr, header); =20 - msm_dp_write_link(catalog, MMSS_DP_AUDIO_STREAM_0, header[0]); - msm_dp_write_link(catalog, MMSS_DP_AUDIO_STREAM_1, header[1]); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_STREAM_0, header[0]); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_STREAM_1, header[1]); } =20 void msm_dp_catalog_write_audio_timestamp(struct msm_dp_catalog *msm_dp_ca= talog, struct dp_sdp_header *sdp_hdr) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); u32 header[2]; =20 msm_dp_utils_pack_sdp_header(sdp_hdr, header); =20 - msm_dp_write_link(catalog, MMSS_DP_AUDIO_TIMESTAMP_0, header[0]); - msm_dp_write_link(catalog, MMSS_DP_AUDIO_TIMESTAMP_1, header[1]); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_TIMESTAMP_0, header[0]); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_TIMESTAMP_1, header[1]); } =20 void msm_dp_catalog_write_audio_infoframe(struct msm_dp_catalog *msm_dp_ca= talog, struct dp_sdp_header *sdp_hdr) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); u32 header[2]; =20 msm_dp_utils_pack_sdp_header(sdp_hdr, header); =20 - msm_dp_write_link(catalog, MMSS_DP_AUDIO_INFOFRAME_0, header[0]); - msm_dp_write_link(catalog, MMSS_DP_AUDIO_INFOFRAME_1, header[1]); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_INFOFRAME_0, header[0]); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_INFOFRAME_1, header[1]); } =20 void msm_dp_catalog_write_audio_copy_mgmt(struct msm_dp_catalog *msm_dp_ca= talog, struct dp_sdp_header *sdp_hdr) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); u32 header[2]; =20 msm_dp_utils_pack_sdp_header(sdp_hdr, header); =20 - msm_dp_write_link(catalog, MMSS_DP_AUDIO_COPYMANAGEMENT_0, header[0]); - msm_dp_write_link(catalog, MMSS_DP_AUDIO_COPYMANAGEMENT_1, header[1]); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_COPYMANAGEMENT_0, header[= 0]); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_COPYMANAGEMENT_1, header[= 1]); } =20 void msm_dp_catalog_write_audio_isrc(struct msm_dp_catalog *msm_dp_catalog, struct dp_sdp_header *sdp_hdr) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); struct dp_sdp_header tmp =3D *sdp_hdr; u32 header[2]; u32 reg; =20 /* XXX: is it necessary to preserve this field? */ - reg =3D msm_dp_read_link(catalog, MMSS_DP_AUDIO_ISRC_1); + reg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_AUDIO_ISRC_1); tmp.HB3 =3D FIELD_GET(HEADER_3_MASK, reg); =20 msm_dp_utils_pack_sdp_header(&tmp, header); =20 - msm_dp_write_link(catalog, MMSS_DP_AUDIO_ISRC_0, header[0]); - msm_dp_write_link(catalog, MMSS_DP_AUDIO_ISRC_1, header[1]); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_ISRC_0, header[0]); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_ISRC_1, header[1]); } =20 void msm_dp_catalog_audio_config_acr(struct msm_dp_catalog *msm_dp_catalog= , u32 select) @@ -1202,7 +1104,7 @@ void msm_dp_catalog_audio_config_acr(struct msm_dp_ca= talog *msm_dp_catalog, u32 drm_dbg_dp(catalog->drm_dev, "select: %#x, acr_ctrl: %#x\n", select, acr_ctrl); =20 - msm_dp_write_link(catalog, MMSS_DP_AUDIO_ACR_CTRL, acr_ctrl); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_ACR_CTRL, acr_ctrl); } =20 void msm_dp_catalog_audio_enable(struct msm_dp_catalog *msm_dp_catalog, bo= ol enable) @@ -1216,7 +1118,7 @@ void msm_dp_catalog_audio_enable(struct msm_dp_catalo= g *msm_dp_catalog, bool ena catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, msm_dp_catalog); =20 - audio_ctrl =3D msm_dp_read_link(catalog, MMSS_DP_AUDIO_CFG); + audio_ctrl =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_AUDIO_CFG); =20 if (enable) audio_ctrl |=3D BIT(0); @@ -1225,7 +1127,7 @@ void msm_dp_catalog_audio_enable(struct msm_dp_catalo= g *msm_dp_catalog, bool ena =20 drm_dbg_dp(catalog->drm_dev, "dp_audio_cfg =3D 0x%x\n", audio_ctrl); =20 - msm_dp_write_link(catalog, MMSS_DP_AUDIO_CFG, audio_ctrl); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_CFG, audio_ctrl); /* make sure audio engine is disabled */ wmb(); } @@ -1242,7 +1144,7 @@ void msm_dp_catalog_audio_config_sdp(struct msm_dp_ca= talog *msm_dp_catalog) catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, msm_dp_catalog); =20 - sdp_cfg =3D msm_dp_read_link(catalog, MMSS_DP_SDP_CFG); + sdp_cfg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG); /* AUDIO_TIMESTAMP_SDP_EN */ sdp_cfg |=3D BIT(1); /* AUDIO_STREAM_SDP_EN */ @@ -1256,9 +1158,9 @@ void msm_dp_catalog_audio_config_sdp(struct msm_dp_ca= talog *msm_dp_catalog) =20 drm_dbg_dp(catalog->drm_dev, "sdp_cfg =3D 0x%x\n", sdp_cfg); =20 - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG, sdp_cfg); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, sdp_cfg); =20 - sdp_cfg2 =3D msm_dp_read_link(catalog, MMSS_DP_SDP_CFG2); + sdp_cfg2 =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2); /* IFRM_REGSRC -> Do not use reg values */ sdp_cfg2 &=3D ~BIT(0); /* AUDIO_STREAM_HB3_REGSRC-> Do not use reg values */ @@ -1266,7 +1168,7 @@ void msm_dp_catalog_audio_config_sdp(struct msm_dp_ca= talog *msm_dp_catalog) =20 drm_dbg_dp(catalog->drm_dev, "sdp_cfg2 =3D 0x%x\n", sdp_cfg2); =20 - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG2, sdp_cfg2); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, sdp_cfg2); } =20 void msm_dp_catalog_audio_sfe_level(struct msm_dp_catalog *msm_dp_catalog,= u32 safe_to_exit_level) @@ -1280,7 +1182,7 @@ void msm_dp_catalog_audio_sfe_level(struct msm_dp_cat= alog *msm_dp_catalog, u32 s catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, msm_dp_catalog); =20 - mainlink_levels =3D msm_dp_read_link(catalog, REG_DP_MAINLINK_LEVELS); + mainlink_levels =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_LEVE= LS); mainlink_levels &=3D 0xFE0; mainlink_levels |=3D safe_to_exit_level; =20 @@ -1288,5 +1190,5 @@ void msm_dp_catalog_audio_sfe_level(struct msm_dp_cat= alog *msm_dp_catalog, u32 s "mainlink_level =3D 0x%x, safe_to_exit_level =3D 0x%x\n", mainlink_levels, safe_to_exit_level); =20 - msm_dp_write_link(catalog, REG_DP_MAINLINK_LEVELS, mainlink_levels); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_LEVELS, mainlink_levels= ); } diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/d= p_catalog.h index 379fa4fef9ceb63b20c4aec2fca1e09003dc738b..5a757671d7310b43e7ca0155ffd= c276c83d1e8bc 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -34,6 +34,18 @@ struct msm_dp_catalog { bool wide_bus_en; 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Reviewed-by: Stephen Boyd Tested-by: Stephen Boyd # sc7180-trogdor Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_catalog.c | 65 ---------------------------------= ---- drivers/gpu/drm/msm/dp/dp_catalog.h | 62 +++++++++++++++++++++++++++++++++= ++ 2 files changed, 62 insertions(+), 65 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/d= p_catalog.c index 74ab86035f3b98b498756673229218558b6713c3..a22efb1e83d04cc5c9bc768a275= df9cfb4752a2f 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -81,71 +81,6 @@ void msm_dp_catalog_snapshot(struct msm_dp_catalog *msm_= dp_catalog, struct msm_d msm_dp_catalog->p0_len, msm_dp_catalog->p0_base, "dp_p0"); } =20 -static inline u32 msm_dp_read_aux(struct msm_dp_catalog *msm_dp_catalog, u= 32 offset) -{ - return readl_relaxed(msm_dp_catalog->aux_base + offset); -} - -static inline void msm_dp_write_aux(struct msm_dp_catalog *msm_dp_catalog, - u32 offset, u32 data) -{ - /* - * To make sure aux reg writes happens before any other operation, - * this function uses writel() instread of writel_relaxed() - */ - writel(data, msm_dp_catalog->aux_base + offset); -} - -static inline u32 msm_dp_read_ahb(const struct msm_dp_catalog *msm_dp_cata= log, u32 offset) -{ - return readl_relaxed(msm_dp_catalog->ahb_base + offset); -} - -static inline void msm_dp_write_ahb(struct msm_dp_catalog *msm_dp_catalog, - u32 offset, u32 data) -{ - /* - * To make sure phy reg writes happens before any other operation, - * this function uses writel() instread of writel_relaxed() - */ - writel(data, msm_dp_catalog->ahb_base + offset); -} - -static inline void msm_dp_write_p0(struct msm_dp_catalog *msm_dp_catalog, - u32 offset, u32 data) -{ - /* - * To make sure interface reg writes happens before any other operation, - * this function uses writel() instread of writel_relaxed() - */ - writel(data, msm_dp_catalog->p0_base + offset); -} - -static inline u32 msm_dp_read_p0(struct msm_dp_catalog *msm_dp_catalog, - u32 offset) -{ - /* - * To make sure interface reg writes happens before any other operation, - * this function uses writel() instread of writel_relaxed() - */ - return readl_relaxed(msm_dp_catalog->p0_base + offset); -} - -static inline u32 msm_dp_read_link(struct msm_dp_catalog *msm_dp_catalog, = u32 offset) -{ - return readl_relaxed(msm_dp_catalog->link_base + offset); -} - -static inline void msm_dp_write_link(struct msm_dp_catalog *msm_dp_catalog, - u32 offset, u32 data) -{ - /* - * To make sure link reg writes happens before any other operation, - * this function uses writel() instread of writel_relaxed() - */ - writel(data, msm_dp_catalog->link_base + offset); -} - /* aux related catalog functions */ u32 msm_dp_catalog_aux_read_data(struct msm_dp_catalog *msm_dp_catalog) { diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/d= p_catalog.h index 5a757671d7310b43e7ca0155ffdc276c83d1e8bc..10fd0086132092be88bb698e531= 24f87a906de70 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -48,6 +48,68 @@ struct msm_dp_catalog { size_t p0_len; }; =20 +/* IO */ +static inline u32 msm_dp_read_aux(struct msm_dp_catalog *msm_dp_catalog, u= 32 offset) +{ + return readl_relaxed(msm_dp_catalog->aux_base + offset); +} + +static inline void msm_dp_write_aux(struct msm_dp_catalog *msm_dp_catalog, + u32 offset, u32 data) +{ + /* + * To make sure aux reg writes happens before any other operation, + * this function uses writel() instread of writel_relaxed() + */ + writel(data, msm_dp_catalog->aux_base + offset); +} + +static inline u32 msm_dp_read_ahb(const struct msm_dp_catalog *msm_dp_cata= log, u32 offset) +{ + return readl_relaxed(msm_dp_catalog->ahb_base + offset); +} + +static inline void msm_dp_write_ahb(struct msm_dp_catalog *msm_dp_catalog, + u32 offset, u32 data) +{ + /* + * To make sure phy reg writes happens before any other operation, + * this function uses writel() instread of writel_relaxed() + */ + writel(data, msm_dp_catalog->ahb_base + offset); +} + +static inline void msm_dp_write_p0(struct msm_dp_catalog *msm_dp_catalog, + u32 offset, u32 data) +{ + /* + * To make sure interface reg writes happens before any other operation, + * this function uses writel() instread of writel_relaxed() + */ + writel(data, msm_dp_catalog->p0_base + offset); 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Reviewed-by: Stephen Boyd Tested-by: Stephen Boyd # sc7180-trogdor Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_aux.c | 96 +++++++++++++++++++++++++++++++--= ---- drivers/gpu/drm/msm/dp/dp_catalog.c | 96 ---------------------------------= ---- drivers/gpu/drm/msm/dp/dp_catalog.h | 9 ---- 3 files changed, 82 insertions(+), 119 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_aux.c b/drivers/gpu/drm/msm/dp/dp_au= x.c index bc8d46abfc619d669dce339477d58fb0c464a3ea..cdcab948ae7086964d9e913dada= dacc333f46231 100644 --- a/drivers/gpu/drm/msm/dp/dp_aux.c +++ b/drivers/gpu/drm/msm/dp/dp_aux.c @@ -4,6 +4,7 @@ */ =20 #include +#include #include #include =20 @@ -45,6 +46,71 @@ struct msm_dp_aux_private { struct drm_dp_aux msm_dp_aux; }; =20 +static void msm_dp_aux_clear_hw_interrupts(struct msm_dp_aux_private *aux) +{ + struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; + + msm_dp_read_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_STATUS); + msm_dp_write_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x1f); + msm_dp_write_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x9f); + msm_dp_write_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0); +} + +/* + * NOTE: resetting AUX controller will also clear any pending HPD related = interrupts + */ +static void msm_dp_aux_reset(struct msm_dp_aux_private *aux) +{ + struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; + u32 aux_ctrl; + + aux_ctrl =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_AUX_CTRL); + + aux_ctrl |=3D DP_AUX_CTRL_RESET; + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_CTRL, aux_ctrl); + usleep_range(1000, 1100); /* h/w recommended delay */ + + aux_ctrl &=3D ~DP_AUX_CTRL_RESET; + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_CTRL, aux_ctrl); +} + +static void msm_dp_aux_enable(struct msm_dp_aux_private *aux) +{ + struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; + u32 aux_ctrl; + + aux_ctrl =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_AUX_CTRL); + + msm_dp_write_aux(msm_dp_catalog, REG_DP_TIMEOUT_COUNT, 0xffff); + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_LIMITS, 0xffff); + + aux_ctrl |=3D DP_AUX_CTRL_ENABLE; + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_CTRL, aux_ctrl); +} + +static void msm_dp_aux_disable(struct msm_dp_aux_private *aux) +{ + struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; + u32 aux_ctrl; + + aux_ctrl =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_AUX_CTRL); + aux_ctrl &=3D ~DP_AUX_CTRL_ENABLE; + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_CTRL, aux_ctrl); +} + +static int msm_dp_aux_wait_for_hpd_connect_state(struct msm_dp_aux_private= *aux, + unsigned long wait_us) +{ + struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; + u32 state; + + /* poll for hpd connected status every 2ms and timeout after wait_us */ + return readl_poll_timeout(msm_dp_catalog->aux_base + + REG_DP_DP_HPD_INT_STATUS, + state, state & DP_DP_HPD_STATE_STATUS_CONNECTED, + min(wait_us, 2000), wait_us); +} + #define MAX_AUX_RETRIES 5 =20 static ssize_t msm_dp_aux_write(struct msm_dp_aux_private *aux, @@ -88,11 +154,11 @@ static ssize_t msm_dp_aux_write(struct msm_dp_aux_priv= ate *aux, /* index =3D 0, write */ if (i =3D=3D 0) reg |=3D DP_AUX_DATA_INDEX_WRITE; - msm_dp_catalog_aux_write_data(aux->catalog, reg); + msm_dp_write_aux(aux->catalog, REG_DP_AUX_DATA, reg); } =20 - msm_dp_catalog_aux_clear_trans(aux->catalog, false); - msm_dp_catalog_aux_clear_hw_interrupts(aux->catalog); + msm_dp_write_aux(aux->catalog, REG_DP_AUX_TRANS_CTRL, 0); + msm_dp_aux_clear_hw_interrupts(aux); =20 reg =3D 0; /* Transaction number =3D=3D 1 */ if (!aux->native) { /* i2c */ @@ -106,7 +172,7 @@ static ssize_t msm_dp_aux_write(struct msm_dp_aux_priva= te *aux, } =20 reg |=3D DP_AUX_TRANS_CTRL_GO; - msm_dp_catalog_aux_write_trans(aux->catalog, reg); + msm_dp_write_aux(aux->catalog, REG_DP_AUX_TRANS_CTRL, reg); =20 return len; } @@ -139,20 +205,22 @@ static ssize_t msm_dp_aux_cmd_fifo_rx(struct msm_dp_a= ux_private *aux, u32 i, actual_i; u32 len =3D msg->size; =20 - msm_dp_catalog_aux_clear_trans(aux->catalog, true); + data =3D msm_dp_read_aux(aux->catalog, REG_DP_AUX_TRANS_CTRL); + data &=3D ~DP_AUX_TRANS_CTRL_GO; + msm_dp_write_aux(aux->catalog, REG_DP_AUX_TRANS_CTRL, data); =20 data =3D DP_AUX_DATA_INDEX_WRITE; /* INDEX_WRITE */ data |=3D DP_AUX_DATA_READ; /* read */ =20 - msm_dp_catalog_aux_write_data(aux->catalog, data); + msm_dp_write_aux(aux->catalog, REG_DP_AUX_DATA, data); =20 dp =3D msg->buffer; =20 /* discard first byte */ - data =3D msm_dp_catalog_aux_read_data(aux->catalog); + data =3D msm_dp_read_aux(aux->catalog, REG_DP_AUX_DATA); =20 for (i =3D 0; i < len; i++) { - data =3D msm_dp_catalog_aux_read_data(aux->catalog); + data =3D msm_dp_read_aux(aux->catalog, REG_DP_AUX_DATA); *dp++ =3D (u8)((data >> DP_AUX_DATA_OFFSET) & 0xff); =20 actual_i =3D (data >> DP_AUX_DATA_INDEX_OFFSET) & 0xFF; @@ -336,7 +404,7 @@ static ssize_t msm_dp_aux_transfer(struct drm_dp_aux *m= sm_dp_aux, } /* reset aux if link is in connected state */ if (msm_dp_catalog_link_is_connected(aux->catalog)) - msm_dp_catalog_aux_reset(aux->catalog); + msm_dp_aux_reset(aux); } else { aux->retry_cnt =3D 0; switch (aux->aux_error_num) { @@ -403,7 +471,7 @@ irqreturn_t msm_dp_aux_isr(struct drm_dp_aux *msm_dp_au= x) =20 if (isr & DP_INTR_AUX_ERROR) { aux->aux_error_num =3D DP_AUX_ERR_PHY; - msm_dp_catalog_aux_clear_hw_interrupts(aux->catalog); + msm_dp_aux_clear_hw_interrupts(aux); } else if (isr & DP_INTR_NACK_DEFER) { aux->aux_error_num =3D DP_AUX_ERR_NACK_DEFER; } else if (isr & DP_INTR_WRONG_ADDR) { @@ -444,7 +512,7 @@ void msm_dp_aux_reconfig(struct drm_dp_aux *msm_dp_aux) aux =3D container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); =20 phy_calibrate(aux->phy); - msm_dp_catalog_aux_reset(aux->catalog); + msm_dp_aux_reset(aux); } =20 void msm_dp_aux_init(struct drm_dp_aux *msm_dp_aux) @@ -460,7 +528,7 @@ void msm_dp_aux_init(struct drm_dp_aux *msm_dp_aux) =20 mutex_lock(&aux->mutex); =20 - msm_dp_catalog_aux_enable(aux->catalog, true); + msm_dp_aux_enable(aux); aux->retry_cnt =3D 0; aux->initted =3D true; =20 @@ -476,7 +544,7 @@ void msm_dp_aux_deinit(struct drm_dp_aux *msm_dp_aux) mutex_lock(&aux->mutex); =20 aux->initted =3D false; - msm_dp_catalog_aux_enable(aux->catalog, false); + msm_dp_aux_disable(aux); =20 mutex_unlock(&aux->mutex); } @@ -517,7 +585,7 @@ static int msm_dp_wait_hpd_asserted(struct drm_dp_aux *= msm_dp_aux, if (ret) return ret; =20 - ret =3D msm_dp_catalog_aux_wait_for_hpd_connect_state(aux->catalog, wait_= us); + ret =3D msm_dp_aux_wait_for_hpd_connect_state(aux, wait_us); pm_runtime_put_sync(aux->dev); =20 return ret; diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/d= p_catalog.c index a22efb1e83d04cc5c9bc768a275df9cfb4752a2f..10dfbe94b627855b5a0e3cd4a3d= 77498d8d43ab8 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -81,102 +81,6 @@ void msm_dp_catalog_snapshot(struct msm_dp_catalog *msm= _dp_catalog, struct msm_d msm_dp_catalog->p0_len, msm_dp_catalog->p0_base, "dp_p0"); } =20 -/* aux related catalog functions */ -u32 msm_dp_catalog_aux_read_data(struct msm_dp_catalog *msm_dp_catalog) -{ - return msm_dp_read_aux(msm_dp_catalog, REG_DP_AUX_DATA); -} - -int msm_dp_catalog_aux_write_data(struct msm_dp_catalog *msm_dp_catalog, u= 32 data) -{ - msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_DATA, data); - return 0; -} - -int msm_dp_catalog_aux_write_trans(struct msm_dp_catalog *msm_dp_catalog, = u32 data) -{ - msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_TRANS_CTRL, data); - return 0; -} - -int msm_dp_catalog_aux_clear_trans(struct msm_dp_catalog *msm_dp_catalog, = bool read) -{ - u32 data; - - if (read) { - data =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_AUX_TRANS_CTRL); - data &=3D ~DP_AUX_TRANS_CTRL_GO; - msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_TRANS_CTRL, data); - } else { - msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_TRANS_CTRL, 0); - } - return 0; -} - -int msm_dp_catalog_aux_clear_hw_interrupts(struct msm_dp_catalog *msm_dp_c= atalog) -{ - msm_dp_read_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_STATUS); - msm_dp_write_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x1f); - msm_dp_write_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x9f); - msm_dp_write_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0); - return 0; -} - -/** - * msm_dp_catalog_aux_reset() - reset AUX controller - * - * @msm_dp_catalog: DP catalog structure - * - * return: void - * - * This function reset AUX controller - * - * NOTE: reset AUX controller will also clear any pending HPD related inte= rrupts - *=20 - */ -void msm_dp_catalog_aux_reset(struct msm_dp_catalog *msm_dp_catalog) -{ - u32 aux_ctrl; - - aux_ctrl =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_AUX_CTRL); - - aux_ctrl |=3D DP_AUX_CTRL_RESET; - msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_CTRL, aux_ctrl); - usleep_range(1000, 1100); /* h/w recommended delay */ - - aux_ctrl &=3D ~DP_AUX_CTRL_RESET; - msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_CTRL, aux_ctrl); -} - -void msm_dp_catalog_aux_enable(struct msm_dp_catalog *msm_dp_catalog, bool= enable) -{ - u32 aux_ctrl; - - aux_ctrl =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_AUX_CTRL); - - if (enable) { - msm_dp_write_aux(msm_dp_catalog, REG_DP_TIMEOUT_COUNT, 0xffff); - msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_LIMITS, 0xffff); - aux_ctrl |=3D DP_AUX_CTRL_ENABLE; - } else { - aux_ctrl &=3D ~DP_AUX_CTRL_ENABLE; - } - - msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_CTRL, aux_ctrl); -} - -int msm_dp_catalog_aux_wait_for_hpd_connect_state(struct msm_dp_catalog *m= sm_dp_catalog, - unsigned long wait_us) -{ - u32 state; - - /* poll for hpd connected status every 2ms and timeout after wait_us */ - return readl_poll_timeout(msm_dp_catalog->aux_base + - REG_DP_DP_HPD_INT_STATUS, - state, state & DP_DP_HPD_STATE_STATUS_CONNECTED, - min(wait_us, 2000), wait_us); -} - u32 msm_dp_catalog_aux_get_irq(struct msm_dp_catalog *msm_dp_catalog) { u32 intr, intr_ack; diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/d= p_catalog.h index 10fd0086132092be88bb698e53124f87a906de70..d120a4872d444a4f8eb1e638d0e= 293033bf1334c 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -114,15 +114,6 @@ static inline void msm_dp_write_link(struct msm_dp_cat= alog *msm_dp_catalog, void msm_dp_catalog_snapshot(struct msm_dp_catalog *msm_dp_catalog, struct= msm_disp_state *disp_state); =20 /* AUX APIs */ -u32 msm_dp_catalog_aux_read_data(struct msm_dp_catalog *msm_dp_catalog); -int msm_dp_catalog_aux_write_data(struct msm_dp_catalog *msm_dp_catalog, u= 32 data); -int msm_dp_catalog_aux_write_trans(struct msm_dp_catalog *msm_dp_catalog, = u32 data); -int msm_dp_catalog_aux_clear_trans(struct msm_dp_catalog *msm_dp_catalog, = bool read); -int msm_dp_catalog_aux_clear_hw_interrupts(struct msm_dp_catalog *msm_dp_c= atalog); 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Reviewed-by: Stephen Boyd Tested-by: Stephen Boyd # sc7180-trogdor Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_catalog.c | 195 --------------------------------- drivers/gpu/drm/msm/dp/dp_catalog.h | 11 -- drivers/gpu/drm/msm/dp/dp_ctrl.c | 6 +- drivers/gpu/drm/msm/dp/dp_panel.c | 209 ++++++++++++++++++++++++++++++++= ++-- drivers/gpu/drm/msm/dp/dp_panel.h | 5 + 5 files changed, 206 insertions(+), 220 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/d= p_catalog.c index 10dfbe94b627855b5a0e3cd4a3d77498d8d43ab8..e9db5585c1325fe5e067526f567= e39387d5a4f47 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -23,8 +23,6 @@ #define DP_INTERRUPT_STATUS_ACK_SHIFT 1 #define DP_INTERRUPT_STATUS_MASK_SHIFT 2 =20 -#define DP_INTF_CONFIG_DATABUS_WIDEN BIT(4) - #define DP_INTERRUPT_STATUS1 \ (DP_INTR_AUX_XFER_DONE| \ DP_INTR_WRONG_ADDR | DP_INTR_TIMEOUT | \ @@ -590,199 +588,6 @@ u32 msm_dp_catalog_ctrl_read_phy_pattern(struct msm_d= p_catalog *msm_dp_catalog) return msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_READY); } =20 -/* panel related catalog functions */ -int msm_dp_catalog_panel_timing_cfg(struct msm_dp_catalog *msm_dp_catalog,= u32 total, - u32 sync_start, u32 width_blanking, u32 msm_dp_active) -{ - u32 reg; - - msm_dp_write_link(msm_dp_catalog, REG_DP_TOTAL_HOR_VER, total); - msm_dp_write_link(msm_dp_catalog, REG_DP_START_HOR_VER_FROM_SYNC, sync_st= art); - msm_dp_write_link(msm_dp_catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, widt= h_blanking); - msm_dp_write_link(msm_dp_catalog, REG_DP_ACTIVE_HOR_VER, msm_dp_active); - - reg =3D msm_dp_read_p0(msm_dp_catalog, MMSS_DP_INTF_CONFIG); - - if (msm_dp_catalog->wide_bus_en) - reg |=3D DP_INTF_CONFIG_DATABUS_WIDEN; - else - reg &=3D ~DP_INTF_CONFIG_DATABUS_WIDEN; - - - DRM_DEBUG_DP("wide_bus_en=3D%d reg=3D%#x\n", msm_dp_catalog->wide_bus_en,= reg); - - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_CONFIG, reg); - return 0; -} - -static void msm_dp_catalog_panel_send_vsc_sdp(struct msm_dp_catalog *msm_d= p_catalog, struct dp_sdp *vsc_sdp) -{ - u32 header[2]; - u32 val; - int i; - - msm_dp_utils_pack_sdp_header(&vsc_sdp->sdp_header, header); - - msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_0, header[0]); - msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_1, header[1]); - - for (i =3D 0; i < sizeof(vsc_sdp->db); i +=3D 4) { - val =3D ((vsc_sdp->db[i]) | (vsc_sdp->db[i + 1] << 8) | (vsc_sdp->db[i += 2] << 16) | - (vsc_sdp->db[i + 3] << 24)); - msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_2 + i, val); - } -} - -static void msm_dp_catalog_panel_update_sdp(struct msm_dp_catalog *msm_dp_= catalog) -{ - u32 hw_revision; - - hw_revision =3D msm_dp_catalog->hw_revision; - - if (hw_revision < DP_HW_VERSION_1_2 && - hw_revision >=3D DP_HW_VERSION_1_0) { - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, 0x01); - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, 0x00); - } -} - -void msm_dp_catalog_panel_enable_vsc_sdp(struct msm_dp_catalog *msm_dp_cat= alog, struct dp_sdp *vsc_sdp) -{ - struct msm_dp_catalog_private *catalog; - u32 cfg, cfg2, misc; - - catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, m= sm_dp_catalog); - - cfg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG); - cfg2 =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2); - misc =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MISC1_MISC0); - - cfg |=3D GEN0_SDP_EN; - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, cfg); - - cfg2 |=3D GENERIC0_SDPSIZE_VALID; - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, cfg2); - - msm_dp_catalog_panel_send_vsc_sdp(msm_dp_catalog, vsc_sdp); - - /* indicates presence of VSC (BIT(6) of MISC1) */ - misc |=3D DP_MISC1_VSC_SDP; - - drm_dbg_dp(catalog->drm_dev, "vsc sdp enable=3D1\n"); - - pr_debug("misc settings =3D 0x%x\n", misc); - msm_dp_write_link(msm_dp_catalog, REG_DP_MISC1_MISC0, misc); - - msm_dp_catalog_panel_update_sdp(msm_dp_catalog); -} - -void msm_dp_catalog_panel_disable_vsc_sdp(struct msm_dp_catalog *msm_dp_ca= talog) -{ - struct msm_dp_catalog_private *catalog; - u32 cfg, cfg2, misc; - - catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, m= sm_dp_catalog); - - cfg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG); - cfg2 =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2); - misc =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MISC1_MISC0); - - cfg &=3D ~GEN0_SDP_EN; - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, cfg); - - cfg2 &=3D ~GENERIC0_SDPSIZE_VALID; - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, cfg2); - - /* switch back to MSA */ - misc &=3D ~DP_MISC1_VSC_SDP; - - drm_dbg_dp(catalog->drm_dev, "vsc sdp enable=3D0\n"); - - pr_debug("misc settings =3D 0x%x\n", misc); - msm_dp_write_link(msm_dp_catalog, REG_DP_MISC1_MISC0, misc); - - msm_dp_catalog_panel_update_sdp(msm_dp_catalog); -} - -void msm_dp_catalog_panel_tpg_enable(struct msm_dp_catalog *msm_dp_catalog, - struct drm_display_mode *drm_mode) -{ - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - u32 hsync_period, vsync_period; - u32 display_v_start, display_v_end; - u32 hsync_start_x, hsync_end_x; - u32 v_sync_width; - u32 hsync_ctl; - u32 display_hctl; - - /* TPG config parameters*/ - hsync_period =3D drm_mode->htotal; - vsync_period =3D drm_mode->vtotal; - - display_v_start =3D ((drm_mode->vtotal - drm_mode->vsync_start) * - hsync_period); - display_v_end =3D ((vsync_period - (drm_mode->vsync_start - - drm_mode->vdisplay)) - * hsync_period) - 1; - - display_v_start +=3D drm_mode->htotal - drm_mode->hsync_start; - display_v_end -=3D (drm_mode->hsync_start - drm_mode->hdisplay); - - hsync_start_x =3D drm_mode->htotal - drm_mode->hsync_start; - hsync_end_x =3D hsync_period - (drm_mode->hsync_start - - drm_mode->hdisplay) - 1; - - v_sync_width =3D drm_mode->vsync_end - drm_mode->vsync_start; - - hsync_ctl =3D (hsync_period << 16) | - (drm_mode->hsync_end - drm_mode->hsync_start); - display_hctl =3D (hsync_end_x << 16) | hsync_start_x; - - - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_perio= d * - hsync_period); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync= _width * - hsync_period); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_ACTIVE_HCTL, 0); - msm_dp_write_p0(msm_dp_catalog, MMSS_INTF_DISPLAY_V_START_F0, display_v_s= tart); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_= end); - msm_dp_write_p0(msm_dp_catalog, MMSS_INTF_DISPLAY_V_START_F1, 0); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_POLARITY_CTL, 0); - - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_TPG_MAIN_CONTROL, - DP_TPG_CHECKERED_RECT_PATTERN); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_TPG_VIDEO_CONFIG, - DP_TPG_VIDEO_CONFIG_BPP_8BIT | - DP_TPG_VIDEO_CONFIG_RGB); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_BIST_ENABLE, - DP_BIST_ENABLE_DPBIST_EN); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_TIMING_ENGINE_EN, - DP_TIMING_ENGINE_EN_EN); - drm_dbg_dp(catalog->drm_dev, "%s: enabled tpg\n", __func__); -} - -void msm_dp_catalog_panel_tpg_disable(struct msm_dp_catalog *msm_dp_catalo= g) -{ - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_TPG_MAIN_CONTROL, 0x0); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_BIST_ENABLE, 0x0); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_TIMING_ENGINE_EN, 0x0); -} - -void msm_dp_catalog_panel_clear_dsc_dto(struct msm_dp_catalog *msm_dp_cata= log) -{ - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_DSC_DTO, 0x0); -} - static void __iomem *msm_dp_ioremap(struct platform_device *pdev, int idx,= size_t *len) { struct resource *res; diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/d= p_catalog.h index d120a4872d444a4f8eb1e638d0e293033bf1334c..60f08fe888cb110e3fc3dfb1d76= 3a57bd5bf47f6 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -148,17 +148,6 @@ void msm_dp_catalog_ctrl_send_phy_pattern(struct msm_d= p_catalog *msm_dp_catalog, u32 pattern); u32 msm_dp_catalog_ctrl_read_phy_pattern(struct msm_dp_catalog *msm_dp_cat= alog); =20 -/* DP Panel APIs */ -int msm_dp_catalog_panel_timing_cfg(struct msm_dp_catalog *msm_dp_catalog,= u32 total, - u32 sync_start, u32 width_blanking, u32 msm_dp_active); -void msm_dp_catalog_panel_enable_vsc_sdp(struct msm_dp_catalog *msm_dp_cat= alog, struct dp_sdp *vsc_sdp); -void msm_dp_catalog_panel_disable_vsc_sdp(struct msm_dp_catalog *msm_dp_ca= talog); -void msm_dp_catalog_panel_tpg_enable(struct msm_dp_catalog *msm_dp_catalog, - struct drm_display_mode *drm_mode); -void msm_dp_catalog_panel_tpg_disable(struct msm_dp_catalog *msm_dp_catalo= g); - -void msm_dp_catalog_panel_clear_dsc_dto(struct msm_dp_catalog *msm_dp_cata= log); - struct msm_dp_catalog *msm_dp_catalog_get(struct device *dev); =20 /* DP Audio APIs */ diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 4c0a19e14492dde92e5707ffe520681aba1ca5c0..17f645495c4a3e6603fee688090= a6ffb3f263cf0 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2050,7 +2050,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl, bool force_link_train pixel_rate_orig, ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420); =20 - msm_dp_catalog_panel_clear_dsc_dto(ctrl->catalog); + msm_dp_panel_clear_dsc_dto(ctrl->panel); =20 msm_dp_ctrl_setup_tr_unit(ctrl); =20 @@ -2076,7 +2076,7 @@ void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl *= msm_dp_ctrl) ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); phy =3D ctrl->phy; =20 - msm_dp_catalog_panel_disable_vsc_sdp(ctrl->catalog); + msm_dp_panel_disable_vsc_sdp(ctrl->panel); =20 /* set dongle to D3 (power off) mode */ msm_dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true); @@ -2131,7 +2131,7 @@ void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl) ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); phy =3D ctrl->phy; =20 - msm_dp_catalog_panel_disable_vsc_sdp(ctrl->catalog); + msm_dp_panel_disable_vsc_sdp(ctrl->panel); =20 msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); =20 diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index 4e8ab75c771b1e3a2d62f75e9993e1062118482b..53eaa9d3629ceae0bc127a60505= 6419bdc4ac7a2 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -4,6 +4,7 @@ */ =20 #include "dp_panel.h" +#include "dp_reg.h" #include "dp_utils.h" =20 #include @@ -11,6 +12,8 @@ #include #include =20 +#define DP_INTF_CONFIG_DATABUS_WIDEN BIT(4) + #define DP_MAX_NUM_DP_LANES 4 #define DP_LINK_RATE_HBR2 540000 /* kbytes */ =20 @@ -252,9 +255,87 @@ void msm_dp_panel_handle_sink_request(struct msm_dp_pa= nel *msm_dp_panel) } } =20 +static void msm_dp_panel_tpg_enable(struct msm_dp_panel *msm_dp_panel, + struct drm_display_mode *drm_mode) +{ + struct msm_dp_panel_private *panel =3D + container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); + struct msm_dp_catalog *catalog =3D panel->catalog; + u32 hsync_period, vsync_period; + u32 display_v_start, display_v_end; + u32 hsync_start_x, hsync_end_x; + u32 v_sync_width; + u32 hsync_ctl; + u32 display_hctl; + + /* TPG config parameters*/ + hsync_period =3D drm_mode->htotal; + vsync_period =3D drm_mode->vtotal; + + display_v_start =3D ((drm_mode->vtotal - drm_mode->vsync_start) * + hsync_period); + display_v_end =3D ((vsync_period - (drm_mode->vsync_start - + drm_mode->vdisplay)) + * hsync_period) - 1; + + display_v_start +=3D drm_mode->htotal - drm_mode->hsync_start; + display_v_end -=3D (drm_mode->hsync_start - drm_mode->hdisplay); + + hsync_start_x =3D drm_mode->htotal - drm_mode->hsync_start; + hsync_end_x =3D hsync_period - (drm_mode->hsync_start - + drm_mode->hdisplay) - 1; + + v_sync_width =3D drm_mode->vsync_end - drm_mode->vsync_start; + + hsync_ctl =3D (hsync_period << 16) | + (drm_mode->hsync_end - drm_mode->hsync_start); + display_hctl =3D (hsync_end_x << 16) | hsync_start_x; + + + msm_dp_write_p0(catalog, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); + msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period * + hsync_period); + msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width * + hsync_period); + msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); + msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); + msm_dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); + msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_HCTL, 0); + msm_dp_write_p0(catalog, MMSS_INTF_DISPLAY_V_START_F0, display_v_start); + msm_dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end); + msm_dp_write_p0(catalog, MMSS_INTF_DISPLAY_V_START_F1, 0); + msm_dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); + msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); + msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); + msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); + msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); + msm_dp_write_p0(catalog, MMSS_DP_INTF_POLARITY_CTL, 0); + + msm_dp_write_p0(catalog, MMSS_DP_TPG_MAIN_CONTROL, + DP_TPG_CHECKERED_RECT_PATTERN); + msm_dp_write_p0(catalog, MMSS_DP_TPG_VIDEO_CONFIG, + DP_TPG_VIDEO_CONFIG_BPP_8BIT | + DP_TPG_VIDEO_CONFIG_RGB); + msm_dp_write_p0(catalog, MMSS_DP_BIST_ENABLE, + DP_BIST_ENABLE_DPBIST_EN); + msm_dp_write_p0(catalog, MMSS_DP_TIMING_ENGINE_EN, + DP_TIMING_ENGINE_EN_EN); + drm_dbg_dp(panel->drm_dev, "%s: enabled tpg\n", __func__); +} + +static void msm_dp_panel_tpg_disable(struct msm_dp_panel *msm_dp_panel) +{ + struct msm_dp_panel_private *panel =3D + container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); + struct msm_dp_catalog *catalog =3D panel->catalog; + + msm_dp_write_p0(catalog, MMSS_DP_TPG_MAIN_CONTROL, 0x0); + msm_dp_write_p0(catalog, MMSS_DP_BIST_ENABLE, 0x0); + msm_dp_write_p0(catalog, MMSS_DP_TIMING_ENGINE_EN, 0x0); +} + void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enabl= e) { - struct msm_dp_catalog *catalog; struct msm_dp_panel_private *panel; =20 if (!msm_dp_panel) { @@ -263,7 +344,6 @@ void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_d= p_panel, bool enable) } =20 panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_= panel); - catalog =3D panel->catalog; =20 if (!panel->panel_on) { drm_dbg_dp(panel->drm_dev, @@ -272,18 +352,113 @@ void msm_dp_panel_tpg_config(struct msm_dp_panel *ms= m_dp_panel, bool enable) } =20 if (!enable) { - msm_dp_catalog_panel_tpg_disable(catalog); + msm_dp_panel_tpg_disable(msm_dp_panel); return; } =20 - drm_dbg_dp(panel->drm_dev, "calling catalog tpg_enable\n"); - msm_dp_catalog_panel_tpg_enable(catalog, &panel->msm_dp_panel.msm_dp_mode= .drm_mode); + drm_dbg_dp(panel->drm_dev, "calling panel's tpg_enable\n"); + msm_dp_panel_tpg_enable(msm_dp_panel, &panel->msm_dp_panel.msm_dp_mode.dr= m_mode); +} + +void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *msm_dp_panel) +{ + struct msm_dp_panel_private *panel =3D + container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); + struct msm_dp_catalog *catalog =3D panel->catalog; + + msm_dp_write_p0(catalog, MMSS_DP_DSC_DTO, 0x0); +} + +static void msm_dp_panel_send_vsc_sdp(struct msm_dp_panel_private *panel, = struct dp_sdp *vsc_sdp) +{ + struct msm_dp_catalog *msm_dp_catalog =3D panel->catalog; + u32 header[2]; + u32 val; + int i; + + msm_dp_utils_pack_sdp_header(&vsc_sdp->sdp_header, header); + + msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_0, header[0]); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_1, header[1]); + + for (i =3D 0; i < sizeof(vsc_sdp->db); i +=3D 4) { + val =3D ((vsc_sdp->db[i]) | (vsc_sdp->db[i + 1] << 8) | (vsc_sdp->db[i += 2] << 16) | + (vsc_sdp->db[i + 3] << 24)); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_2 + i, val); + } +} + +static void msm_dp_panel_update_sdp(struct msm_dp_panel_private *panel) +{ + u32 hw_revision =3D panel->catalog->hw_revision; + + if (hw_revision >=3D DP_HW_VERSION_1_0 && + hw_revision < DP_HW_VERSION_1_2) { + msm_dp_write_link(panel->catalog, MMSS_DP_SDP_CFG3, UPDATE_SDP); + msm_dp_write_link(panel->catalog, MMSS_DP_SDP_CFG3, 0x0); + } +} + +void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct= dp_sdp *vsc_sdp) +{ + struct msm_dp_panel_private *panel =3D + container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); + struct msm_dp_catalog *msm_dp_catalog =3D panel->catalog; + u32 cfg, cfg2, misc; + + cfg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG); + cfg2 =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2); + misc =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MISC1_MISC0); + + cfg |=3D GEN0_SDP_EN; + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, cfg); + + cfg2 |=3D GENERIC0_SDPSIZE_VALID; + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, cfg2); + + msm_dp_panel_send_vsc_sdp(panel, vsc_sdp); + + /* indicates presence of VSC (BIT(6) of MISC1) */ + misc |=3D DP_MISC1_VSC_SDP; + + drm_dbg_dp(panel->drm_dev, "vsc sdp enable=3D1\n"); + + pr_debug("misc settings =3D 0x%x\n", misc); + msm_dp_write_link(msm_dp_catalog, REG_DP_MISC1_MISC0, misc); + + msm_dp_panel_update_sdp(panel); +} + +void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel) +{ + struct msm_dp_panel_private *panel =3D + container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); + struct msm_dp_catalog *msm_dp_catalog =3D panel->catalog; + u32 cfg, cfg2, misc; + + cfg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG); + cfg2 =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2); + misc =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MISC1_MISC0); + + cfg &=3D ~GEN0_SDP_EN; + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, cfg); + + cfg2 &=3D ~GENERIC0_SDPSIZE_VALID; + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, cfg2); + + /* switch back to MSA */ + misc &=3D ~DP_MISC1_VSC_SDP; + + drm_dbg_dp(panel->drm_dev, "vsc sdp enable=3D0\n"); + + pr_debug("misc settings =3D 0x%x\n", misc); + msm_dp_write_link(msm_dp_catalog, REG_DP_MISC1_MISC0, misc); + + msm_dp_panel_update_sdp(panel); } =20 static int msm_dp_panel_setup_vsc_sdp_yuv_420(struct msm_dp_panel *msm_dp_= panel) { - struct msm_dp_catalog *catalog; - struct msm_dp_panel_private *panel; struct msm_dp_display_mode *msm_dp_mode; struct drm_dp_vsc_sdp vsc_sdp_data; struct dp_sdp vsc_sdp; @@ -294,8 +469,6 @@ static int msm_dp_panel_setup_vsc_sdp_yuv_420(struct ms= m_dp_panel *msm_dp_panel) return -EINVAL; } =20 - panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_= panel); - catalog =3D panel->catalog; msm_dp_mode =3D &msm_dp_panel->msm_dp_mode; =20 memset(&vsc_sdp_data, 0, sizeof(vsc_sdp_data)); @@ -322,7 +495,7 @@ static int msm_dp_panel_setup_vsc_sdp_yuv_420(struct ms= m_dp_panel *msm_dp_panel) return len; } =20 - msm_dp_catalog_panel_enable_vsc_sdp(catalog, &vsc_sdp); + msm_dp_panel_enable_vsc_sdp(msm_dp_panel, &vsc_sdp); =20 return 0; } @@ -337,6 +510,7 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp= _panel) u32 sync_start; u32 msm_dp_active; u32 total; + u32 reg; =20 panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_= panel); catalog =3D panel->catalog; @@ -382,7 +556,20 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_d= p_panel) =20 msm_dp_active =3D data; =20 - msm_dp_catalog_panel_timing_cfg(catalog, total, sync_start, width_blankin= g, msm_dp_active); + msm_dp_write_link(catalog, REG_DP_TOTAL_HOR_VER, total); + msm_dp_write_link(catalog, REG_DP_START_HOR_VER_FROM_SYNC, sync_start); + msm_dp_write_link(catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, width_blank= ing); + msm_dp_write_link(catalog, REG_DP_ACTIVE_HOR_VER, msm_dp_active); + + reg =3D msm_dp_read_p0(catalog, MMSS_DP_INTF_CONFIG); + if (catalog->wide_bus_en) + reg |=3D DP_INTF_CONFIG_DATABUS_WIDEN; + else + reg &=3D ~DP_INTF_CONFIG_DATABUS_WIDEN; + + drm_dbg_dp(panel->drm_dev, "wide_bus_en=3D%d reg=3D%#x\n", catalog->wide_= bus_en, reg); + + msm_dp_write_p0(catalog, MMSS_DP_INTF_CONFIG, reg); =20 if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) msm_dp_panel_setup_vsc_sdp_yuv_420(msm_dp_panel); diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_= panel.h index 4906f4f09f2451cfed3c1007f38b4db7dfdb1d90..8dde55b3a5ab64c0c12d69cb2dd= 5b5c733c83432 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -57,6 +57,11 @@ int msm_dp_panel_get_modes(struct msm_dp_panel *msm_dp_p= anel, void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel); 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Inline functions with simple register access patterns. Reviewed-by: Stephen Boyd Tested-by: Stephen Boyd # sc7180-trogdor Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_audio.c | 112 +++++++++++++++++++++--- drivers/gpu/drm/msm/dp/dp_catalog.c | 166 --------------------------------= ---- drivers/gpu/drm/msm/dp/dp_catalog.h | 16 ---- 3 files changed, 98 insertions(+), 196 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_audio.c b/drivers/gpu/drm/msm/dp/dp_= audio.c index f8bfb908f9b4bf93ad5480f0785e3aed23dde160..09f871a001073ae698708b31fa8= 030ec7cf20242 100644 --- a/drivers/gpu/drm/msm/dp/dp_audio.c +++ b/drivers/gpu/drm/msm/dp/dp_audio.c @@ -31,67 +31,129 @@ struct msm_dp_audio_private { =20 static void msm_dp_audio_stream_sdp(struct msm_dp_audio_private *audio) { + struct msm_dp_catalog *catalog =3D audio->catalog; struct dp_sdp_header sdp_hdr =3D { .HB0 =3D 0x00, .HB1 =3D 0x02, .HB2 =3D 0x00, .HB3 =3D audio->channels - 1, }; + u32 header[2]; + + msm_dp_utils_pack_sdp_header(&sdp_hdr, header); =20 - msm_dp_catalog_write_audio_stream(audio->catalog, &sdp_hdr); + msm_dp_write_link(catalog, MMSS_DP_AUDIO_STREAM_0, header[0]); + msm_dp_write_link(catalog, MMSS_DP_AUDIO_STREAM_1, header[1]); } =20 static void msm_dp_audio_timestamp_sdp(struct msm_dp_audio_private *audio) { + struct msm_dp_catalog *catalog =3D audio->catalog; struct dp_sdp_header sdp_hdr =3D { .HB0 =3D 0x00, .HB1 =3D 0x01, .HB2 =3D 0x17, .HB3 =3D 0x0 | (0x11 << 2), }; + u32 header[2]; =20 - msm_dp_catalog_write_audio_timestamp(audio->catalog, &sdp_hdr); + msm_dp_utils_pack_sdp_header(&sdp_hdr, header); + + msm_dp_write_link(catalog, MMSS_DP_AUDIO_TIMESTAMP_0, header[0]); + msm_dp_write_link(catalog, MMSS_DP_AUDIO_TIMESTAMP_1, header[1]); } =20 static void msm_dp_audio_infoframe_sdp(struct msm_dp_audio_private *audio) { + struct msm_dp_catalog *catalog =3D audio->catalog; struct dp_sdp_header sdp_hdr =3D { .HB0 =3D 0x00, .HB1 =3D 0x84, .HB2 =3D 0x1b, .HB3 =3D 0x0 | (0x11 << 2), }; + u32 header[2]; + + msm_dp_utils_pack_sdp_header(&sdp_hdr, header); =20 - msm_dp_catalog_write_audio_infoframe(audio->catalog, &sdp_hdr); + msm_dp_write_link(catalog, MMSS_DP_AUDIO_INFOFRAME_0, header[0]); + msm_dp_write_link(catalog, MMSS_DP_AUDIO_INFOFRAME_1, header[1]); } =20 static void msm_dp_audio_copy_management_sdp(struct msm_dp_audio_private *= audio) { + struct msm_dp_catalog *catalog =3D audio->catalog; struct dp_sdp_header sdp_hdr =3D { .HB0 =3D 0x00, .HB1 =3D 0x05, .HB2 =3D 0x0f, .HB3 =3D 0x00, }; + u32 header[2]; + + msm_dp_utils_pack_sdp_header(&sdp_hdr, header); =20 - msm_dp_catalog_write_audio_copy_mgmt(audio->catalog, &sdp_hdr); + msm_dp_write_link(catalog, MMSS_DP_AUDIO_COPYMANAGEMENT_0, header[0]); + msm_dp_write_link(catalog, MMSS_DP_AUDIO_COPYMANAGEMENT_1, header[1]); } =20 static void msm_dp_audio_isrc_sdp(struct msm_dp_audio_private *audio) { + struct msm_dp_catalog *catalog =3D audio->catalog; struct dp_sdp_header sdp_hdr =3D { .HB0 =3D 0x00, .HB1 =3D 0x06, .HB2 =3D 0x0f, .HB3 =3D 0x00, }; + u32 header[2]; + u32 reg; + + /* XXX: is it necessary to preserve this field? */ + reg =3D msm_dp_read_link(catalog, MMSS_DP_AUDIO_ISRC_1); + sdp_hdr.HB3 =3D FIELD_GET(HEADER_3_MASK, reg); + + msm_dp_utils_pack_sdp_header(&sdp_hdr, header); + + msm_dp_write_link(catalog, MMSS_DP_AUDIO_ISRC_0, header[0]); + msm_dp_write_link(catalog, MMSS_DP_AUDIO_ISRC_1, header[1]); +} =20 - msm_dp_catalog_write_audio_isrc(audio->catalog, &sdp_hdr); +static void msm_dp_audio_config_sdp(struct msm_dp_audio_private *audio) +{ + struct msm_dp_catalog *msm_dp_catalog =3D audio->catalog; + u32 sdp_cfg, sdp_cfg2; + + sdp_cfg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG); + /* AUDIO_TIMESTAMP_SDP_EN */ + sdp_cfg |=3D BIT(1); + /* AUDIO_STREAM_SDP_EN */ + sdp_cfg |=3D BIT(2); + /* AUDIO_COPY_MANAGEMENT_SDP_EN */ + sdp_cfg |=3D BIT(5); + /* AUDIO_ISRC_SDP_EN */ + sdp_cfg |=3D BIT(6); + /* AUDIO_INFOFRAME_SDP_EN */ + sdp_cfg |=3D BIT(20); + + drm_dbg_dp(audio->drm_dev, "sdp_cfg =3D 0x%x\n", sdp_cfg); + + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, sdp_cfg); + + sdp_cfg2 =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2); + /* IFRM_REGSRC -> Do not use reg values */ + sdp_cfg2 &=3D ~BIT(0); + /* AUDIO_STREAM_HB3_REGSRC-> Do not use reg values */ + sdp_cfg2 &=3D ~BIT(1); + + drm_dbg_dp(audio->drm_dev, "sdp_cfg2 =3D 0x%x\n", sdp_cfg2); + + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, sdp_cfg2); } =20 static void msm_dp_audio_setup_sdp(struct msm_dp_audio_private *audio) { - msm_dp_catalog_audio_config_sdp(audio->catalog); + msm_dp_audio_config_sdp(audio); =20 msm_dp_audio_stream_sdp(audio); msm_dp_audio_timestamp_sdp(audio); @@ -102,8 +164,7 @@ static void msm_dp_audio_setup_sdp(struct msm_dp_audio_= private *audio) =20 static void msm_dp_audio_setup_acr(struct msm_dp_audio_private *audio) { - u32 select =3D 0; - struct msm_dp_catalog *catalog =3D audio->catalog; + u32 select, acr_ctrl; =20 switch (audio->msm_dp_audio.bw_code) { case DP_LINK_BW_1_62: @@ -124,13 +185,17 @@ static void msm_dp_audio_setup_acr(struct msm_dp_audi= o_private *audio) break; } =20 - msm_dp_catalog_audio_config_acr(catalog, select); + acr_ctrl =3D select << 4 | BIT(31) | BIT(8) | BIT(14); + + drm_dbg_dp(audio->drm_dev, "select: %#x, acr_ctrl: %#x\n", + select, acr_ctrl); + + msm_dp_write_link(audio->catalog, MMSS_DP_AUDIO_ACR_CTRL, acr_ctrl); } =20 static void msm_dp_audio_safe_to_exit_level(struct msm_dp_audio_private *a= udio) { - struct msm_dp_catalog *catalog =3D audio->catalog; - u32 safe_to_exit_level =3D 0; + u32 safe_to_exit_level, mainlink_levels; =20 switch (audio->msm_dp_audio.lane_count) { case 1: @@ -150,14 +215,33 @@ static void msm_dp_audio_safe_to_exit_level(struct ms= m_dp_audio_private *audio) break; } =20 - msm_dp_catalog_audio_sfe_level(catalog, safe_to_exit_level); + mainlink_levels =3D msm_dp_read_link(audio->catalog, REG_DP_MAINLINK_LEVE= LS); + mainlink_levels &=3D 0xFE0; + mainlink_levels |=3D safe_to_exit_level; + + drm_dbg_dp(audio->drm_dev, + "mainlink_level =3D 0x%x, safe_to_exit_level =3D 0x%x\n", + mainlink_levels, safe_to_exit_level); + + msm_dp_write_link(audio->catalog, REG_DP_MAINLINK_LEVELS, mainlink_levels= ); } =20 static void msm_dp_audio_enable(struct msm_dp_audio_private *audio, bool e= nable) { - struct msm_dp_catalog *catalog =3D audio->catalog; + u32 audio_ctrl; + + audio_ctrl =3D msm_dp_read_link(audio->catalog, MMSS_DP_AUDIO_CFG); + + if (enable) + audio_ctrl |=3D BIT(0); + else + audio_ctrl &=3D ~BIT(0); + + drm_dbg_dp(audio->drm_dev, "dp_audio_cfg =3D 0x%x\n", audio_ctrl); =20 - msm_dp_catalog_audio_enable(catalog, enable); + msm_dp_write_link(audio->catalog, MMSS_DP_AUDIO_CFG, audio_ctrl); + /* make sure audio engine is disabled */ + wmb(); } =20 static struct msm_dp_audio_private *msm_dp_audio_get_data(struct msm_dp *m= sm_dp_display) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/d= p_catalog.c index e9db5585c1325fe5e067526f567e39387d5a4f47..332d168811c28f5c54069db9754= ecf69904d5b24 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -670,169 +670,3 @@ struct msm_dp_catalog *msm_dp_catalog_get(struct devi= ce *dev) =20 return &catalog->msm_dp_catalog; } - -void msm_dp_catalog_write_audio_stream(struct msm_dp_catalog *msm_dp_catal= og, - struct dp_sdp_header *sdp_hdr) -{ - u32 header[2]; - - msm_dp_utils_pack_sdp_header(sdp_hdr, header); - - msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_STREAM_0, header[0]); - msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_STREAM_1, header[1]); -} - -void msm_dp_catalog_write_audio_timestamp(struct msm_dp_catalog *msm_dp_ca= talog, - struct dp_sdp_header *sdp_hdr) -{ - u32 header[2]; - - msm_dp_utils_pack_sdp_header(sdp_hdr, header); - - msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_TIMESTAMP_0, header[0]); - msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_TIMESTAMP_1, header[1]); -} - -void msm_dp_catalog_write_audio_infoframe(struct msm_dp_catalog *msm_dp_ca= talog, - struct dp_sdp_header *sdp_hdr) -{ - u32 header[2]; - - msm_dp_utils_pack_sdp_header(sdp_hdr, header); - - msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_INFOFRAME_0, header[0]); - msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_INFOFRAME_1, header[1]); -} - -void msm_dp_catalog_write_audio_copy_mgmt(struct msm_dp_catalog *msm_dp_ca= talog, - struct dp_sdp_header *sdp_hdr) -{ - u32 header[2]; - - msm_dp_utils_pack_sdp_header(sdp_hdr, header); - - msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_COPYMANAGEMENT_0, header[= 0]); - msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_COPYMANAGEMENT_1, header[= 1]); -} - -void msm_dp_catalog_write_audio_isrc(struct msm_dp_catalog *msm_dp_catalog, - struct dp_sdp_header *sdp_hdr) -{ - struct dp_sdp_header tmp =3D *sdp_hdr; - u32 header[2]; - u32 reg; - - /* XXX: is it necessary to preserve this field? */ - reg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_AUDIO_ISRC_1); - tmp.HB3 =3D FIELD_GET(HEADER_3_MASK, reg); - - msm_dp_utils_pack_sdp_header(&tmp, header); - - msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_ISRC_0, header[0]); - msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_ISRC_1, header[1]); -} - -void msm_dp_catalog_audio_config_acr(struct msm_dp_catalog *msm_dp_catalog= , u32 select) -{ - struct msm_dp_catalog_private *catalog; - u32 acr_ctrl; - - if (!msm_dp_catalog) - return; - - catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - acr_ctrl =3D select << 4 | BIT(31) | BIT(8) | BIT(14); - - drm_dbg_dp(catalog->drm_dev, "select: %#x, acr_ctrl: %#x\n", - select, acr_ctrl); - - msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_ACR_CTRL, acr_ctrl); -} - -void msm_dp_catalog_audio_enable(struct msm_dp_catalog *msm_dp_catalog, bo= ol enable) -{ - struct msm_dp_catalog_private *catalog; - u32 audio_ctrl; - - if (!msm_dp_catalog) - return; - - catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - audio_ctrl =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_AUDIO_CFG); - - if (enable) - audio_ctrl |=3D BIT(0); - else - audio_ctrl &=3D ~BIT(0); - - drm_dbg_dp(catalog->drm_dev, "dp_audio_cfg =3D 0x%x\n", audio_ctrl); - - msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_CFG, audio_ctrl); - /* make sure audio engine is disabled */ - wmb(); -} - -void msm_dp_catalog_audio_config_sdp(struct msm_dp_catalog *msm_dp_catalog) -{ - struct msm_dp_catalog_private *catalog; - u32 sdp_cfg =3D 0; - u32 sdp_cfg2 =3D 0; - - if (!msm_dp_catalog) - return; - - catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - sdp_cfg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG); - /* AUDIO_TIMESTAMP_SDP_EN */ - sdp_cfg |=3D BIT(1); - /* AUDIO_STREAM_SDP_EN */ - sdp_cfg |=3D BIT(2); - /* AUDIO_COPY_MANAGEMENT_SDP_EN */ - sdp_cfg |=3D BIT(5); - /* AUDIO_ISRC_SDP_EN */ - sdp_cfg |=3D BIT(6); - /* AUDIO_INFOFRAME_SDP_EN */ - sdp_cfg |=3D BIT(20); - - drm_dbg_dp(catalog->drm_dev, "sdp_cfg =3D 0x%x\n", sdp_cfg); - - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, sdp_cfg); - - sdp_cfg2 =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2); - /* IFRM_REGSRC -> Do not use reg values */ - sdp_cfg2 &=3D ~BIT(0); - /* AUDIO_STREAM_HB3_REGSRC-> Do not use reg values */ - sdp_cfg2 &=3D ~BIT(1); - - drm_dbg_dp(catalog->drm_dev, "sdp_cfg2 =3D 0x%x\n", sdp_cfg2); - - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, sdp_cfg2); -} - -void msm_dp_catalog_audio_sfe_level(struct msm_dp_catalog *msm_dp_catalog,= u32 safe_to_exit_level) -{ - struct msm_dp_catalog_private *catalog; - u32 mainlink_levels; - - if (!msm_dp_catalog) - return; - - catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - mainlink_levels =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_LEVE= LS); - mainlink_levels &=3D 0xFE0; - mainlink_levels |=3D safe_to_exit_level; - - drm_dbg_dp(catalog->drm_dev, - "mainlink_level =3D 0x%x, safe_to_exit_level =3D 0x%x\n", - mainlink_levels, safe_to_exit_level); - - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_LEVELS, mainlink_levels= ); -} diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/d= p_catalog.h index 60f08fe888cb110e3fc3dfb1d763a57bd5bf47f6..9ebdc9bd865c566efb97cf0edbd= cd809e5a713e7 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -150,20 +150,4 @@ u32 msm_dp_catalog_ctrl_read_phy_pattern(struct msm_dp= _catalog *msm_dp_catalog); =20 struct msm_dp_catalog *msm_dp_catalog_get(struct device *dev); =20 -/* DP Audio APIs */ -void msm_dp_catalog_write_audio_stream(struct msm_dp_catalog *msm_dp_catal= og, - struct dp_sdp_header *sdp_hdr); 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The enable/disable functions have been split to the enable/disable or enter/exit pairs. The IRQ and HPD related functions are left in dp_catalog.c, pending later cleanup. Reviewed-by: Stephen Boyd Tested-by: Stephen Boyd # sc7180-trogdor Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_catalog.c | 390 +------------------------------ drivers/gpu/drm/msm/dp/dp_catalog.h | 23 +- drivers/gpu/drm/msm/dp/dp_ctrl.c | 450 ++++++++++++++++++++++++++++++++= ---- drivers/gpu/drm/msm/dp/dp_panel.c | 2 +- drivers/gpu/drm/msm/dp/dp_panel.h | 1 + 5 files changed, 415 insertions(+), 451 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/d= p_catalog.c index 332d168811c28f5c54069db9754ecf69904d5b24..7021effc7020073b8b7f633b962= 86e3996d78d6e 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -18,8 +18,6 @@ #define POLLING_SLEEP_US 1000 #define POLLING_TIMEOUT_US 10000 =20 -#define SCRAMBLER_RESET_COUNT_VALUE 0xFC - #define DP_INTERRUPT_STATUS_ACK_SHIFT 1 #define DP_INTERRUPT_STATUS_MASK_SHIFT 2 =20 @@ -94,262 +92,6 @@ u32 msm_dp_catalog_aux_get_irq(struct msm_dp_catalog *m= sm_dp_catalog) =20 } =20 -/* controller related catalog functions */ -void msm_dp_catalog_ctrl_update_transfer_unit(struct msm_dp_catalog *msm_d= p_catalog, - u32 msm_dp_tu, u32 valid_boundary, - u32 valid_boundary2) -{ - msm_dp_write_link(msm_dp_catalog, REG_DP_VALID_BOUNDARY, valid_boundary); - msm_dp_write_link(msm_dp_catalog, REG_DP_TU, msm_dp_tu); - msm_dp_write_link(msm_dp_catalog, REG_DP_VALID_BOUNDARY_2, valid_boundary= 2); -} - -void msm_dp_catalog_ctrl_state_ctrl(struct msm_dp_catalog *msm_dp_catalog,= u32 state) -{ - msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, state); -} - -void msm_dp_catalog_ctrl_config_ctrl(struct msm_dp_catalog *msm_dp_catalog= , u32 cfg) -{ - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - drm_dbg_dp(catalog->drm_dev, "DP_CONFIGURATION_CTRL=3D0x%x\n", cfg); - - msm_dp_write_link(msm_dp_catalog, REG_DP_CONFIGURATION_CTRL, cfg); -} - -void msm_dp_catalog_ctrl_lane_mapping(struct msm_dp_catalog *msm_dp_catalo= g) -{ - u32 ln_0 =3D 0, ln_1 =3D 1, ln_2 =3D 2, ln_3 =3D 3; /* One-to-One mapping= */ - u32 ln_mapping; - - ln_mapping =3D ln_0 << LANE0_MAPPING_SHIFT; - ln_mapping |=3D ln_1 << LANE1_MAPPING_SHIFT; - ln_mapping |=3D ln_2 << LANE2_MAPPING_SHIFT; - ln_mapping |=3D ln_3 << LANE3_MAPPING_SHIFT; - - msm_dp_write_link(msm_dp_catalog, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, - ln_mapping); -} - -void msm_dp_catalog_ctrl_psr_mainlink_enable(struct msm_dp_catalog *msm_dp= _catalog, - bool enable) -{ - u32 val; - - val =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); - - if (enable) - val |=3D DP_MAINLINK_CTRL_ENABLE; - else - val &=3D ~DP_MAINLINK_CTRL_ENABLE; - - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, val); -} - -void msm_dp_catalog_ctrl_mainlink_ctrl(struct msm_dp_catalog *msm_dp_catal= og, - bool enable) -{ - u32 mainlink_ctrl; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - drm_dbg_dp(catalog->drm_dev, "enable=3D%d\n", enable); - if (enable) { - /* - * To make sure link reg writes happens before other operation, - * msm_dp_write_link() function uses writel() - */ - mainlink_ctrl =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); - - mainlink_ctrl &=3D ~(DP_MAINLINK_CTRL_RESET | - DP_MAINLINK_CTRL_ENABLE); - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); - - mainlink_ctrl |=3D DP_MAINLINK_CTRL_RESET; - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); - - mainlink_ctrl &=3D ~DP_MAINLINK_CTRL_RESET; - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); - - mainlink_ctrl |=3D (DP_MAINLINK_CTRL_ENABLE | - DP_MAINLINK_FB_BOUNDARY_SEL); - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); - } else { - mainlink_ctrl =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); - mainlink_ctrl &=3D ~DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); - } -} - -void msm_dp_catalog_ctrl_config_misc(struct msm_dp_catalog *msm_dp_catalog, - u32 colorimetry_cfg, - u32 test_bits_depth) -{ - u32 misc_val; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - misc_val =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MISC1_MISC0); - - /* clear bpp bits */ - misc_val &=3D ~(0x07 << DP_MISC0_TEST_BITS_DEPTH_SHIFT); - misc_val |=3D colorimetry_cfg << DP_MISC0_COLORIMETRY_CFG_SHIFT; - misc_val |=3D test_bits_depth << DP_MISC0_TEST_BITS_DEPTH_SHIFT; - /* Configure clock to synchronous mode */ - misc_val |=3D DP_MISC0_SYNCHRONOUS_CLK; - - drm_dbg_dp(catalog->drm_dev, "misc settings =3D 0x%x\n", misc_val); - msm_dp_write_link(msm_dp_catalog, REG_DP_MISC1_MISC0, misc_val); -} - -void msm_dp_catalog_setup_peripheral_flush(struct msm_dp_catalog *msm_dp_c= atalog) -{ - u32 mainlink_ctrl; - - mainlink_ctrl =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); - - if (msm_dp_catalog->hw_revision >=3D DP_HW_VERSION_1_2) - mainlink_ctrl |=3D DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE; - else - mainlink_ctrl |=3D DP_MAINLINK_FLUSH_MODE_UPDATE_SDP; - - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); -} - -void msm_dp_catalog_ctrl_config_msa(struct msm_dp_catalog *msm_dp_catalog, - u32 rate, u32 stream_rate_khz, - bool is_ycbcr_420) -{ - u32 pixel_m, pixel_n; - u32 mvid, nvid, pixel_div =3D 0, dispcc_input_rate; - u32 const nvid_fixed =3D DP_LINK_CONSTANT_N_VALUE; - u32 const link_rate_hbr2 =3D 540000; - u32 const link_rate_hbr3 =3D 810000; - unsigned long den, num; - - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - if (rate =3D=3D link_rate_hbr3) - pixel_div =3D 6; - else if (rate =3D=3D 162000 || rate =3D=3D 270000) - pixel_div =3D 2; - else if (rate =3D=3D link_rate_hbr2) - pixel_div =3D 4; - else - DRM_ERROR("Invalid pixel mux divider\n"); - - dispcc_input_rate =3D (rate * 10) / pixel_div; - - rational_best_approximation(dispcc_input_rate, stream_rate_khz, - (unsigned long)(1 << 16) - 1, - (unsigned long)(1 << 16) - 1, &den, &num); - - den =3D ~(den - num); - den =3D den & 0xFFFF; - pixel_m =3D num; - pixel_n =3D den; - - mvid =3D (pixel_m & 0xFFFF) * 5; - nvid =3D (0xFFFF & (~pixel_n)) + (pixel_m & 0xFFFF); - - if (nvid < nvid_fixed) { - u32 temp; - - temp =3D (nvid_fixed / nvid) * nvid; - mvid =3D (nvid_fixed / nvid) * mvid; - nvid =3D temp; - } - - if (is_ycbcr_420) - mvid /=3D 2; - - if (link_rate_hbr2 =3D=3D rate) - nvid *=3D 2; - - if (link_rate_hbr3 =3D=3D rate) - nvid *=3D 3; - - drm_dbg_dp(catalog->drm_dev, "mvid=3D0x%x, nvid=3D0x%x\n", mvid, nvid); - msm_dp_write_link(msm_dp_catalog, REG_DP_SOFTWARE_MVID, mvid); - msm_dp_write_link(msm_dp_catalog, REG_DP_SOFTWARE_NVID, nvid); -} - -int msm_dp_catalog_ctrl_set_pattern_state_bit(struct msm_dp_catalog *msm_d= p_catalog, - u32 state_bit) -{ - int bit, ret; - u32 data; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - bit =3D BIT(state_bit - 1); - drm_dbg_dp(catalog->drm_dev, "hw: bit=3D%d train=3D%d\n", bit, state_bit); - msm_dp_catalog_ctrl_state_ctrl(msm_dp_catalog, bit); - - bit =3D BIT(state_bit - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT; - - /* Poll for mainlink ready status */ - ret =3D readx_poll_timeout(readl, msm_dp_catalog->link_base + - REG_DP_MAINLINK_READY, - data, data & bit, - POLLING_SLEEP_US, POLLING_TIMEOUT_US); - if (ret < 0) { - DRM_ERROR("set state_bit for link_train=3D%d failed\n", state_bit); - return ret; - } - return 0; -} - -/** - * msm_dp_catalog_ctrl_reset() - reset DP controller - * - * @msm_dp_catalog: DP catalog structure - * - * return: void - * - * This function reset the DP controller - * - * NOTE: reset DP controller will also clear any pending HPD related inter= rupts - *=20 - */ -void msm_dp_catalog_ctrl_reset(struct msm_dp_catalog *msm_dp_catalog) -{ - u32 sw_reset; - - sw_reset =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_SW_RESET); - - sw_reset |=3D DP_SW_RESET; - msm_dp_write_ahb(msm_dp_catalog, REG_DP_SW_RESET, sw_reset); - usleep_range(1000, 1100); /* h/w recommended delay */ - - sw_reset &=3D ~DP_SW_RESET; - msm_dp_write_ahb(msm_dp_catalog, REG_DP_SW_RESET, sw_reset); - - if (!msm_dp_catalog->hw_revision) - msm_dp_catalog->hw_revision =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_H= W_VERSION); -} - -bool msm_dp_catalog_ctrl_mainlink_ready(struct msm_dp_catalog *msm_dp_cata= log) -{ - u32 data; - int ret; - - /* Poll for mainlink ready status */ - ret =3D readl_poll_timeout(msm_dp_catalog->link_base + - REG_DP_MAINLINK_READY, - data, data & DP_MAINLINK_READY_FOR_VIDEO, - POLLING_SLEEP_US, POLLING_TIMEOUT_US); - if (ret < 0) { - DRM_ERROR("mainlink not ready\n"); - return false; - } - - return true; -} - void msm_dp_catalog_ctrl_enable_irq(struct msm_dp_catalog *msm_dp_catalog, bool enable) { @@ -402,43 +144,6 @@ void msm_dp_catalog_ctrl_hpd_disable(struct msm_dp_cat= alog *msm_dp_catalog) msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_CTRL, 0); } =20 -static void msm_dp_catalog_enable_sdp(struct msm_dp_catalog *msm_dp_catalo= g) -{ - /* trigger sdp */ - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, UPDATE_SDP); - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, 0x0); -} - -void msm_dp_catalog_ctrl_config_psr(struct msm_dp_catalog *msm_dp_catalog) -{ - u32 config; - - /* enable PSR1 function */ - config =3D msm_dp_read_link(msm_dp_catalog, REG_PSR_CONFIG); - config |=3D PSR1_SUPPORTED; - msm_dp_write_link(msm_dp_catalog, REG_PSR_CONFIG, config); - - msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4); - msm_dp_catalog_enable_sdp(msm_dp_catalog); -} - -void msm_dp_catalog_ctrl_set_psr(struct msm_dp_catalog *msm_dp_catalog, bo= ol enter) -{ - u32 cmd; - - cmd =3D msm_dp_read_link(msm_dp_catalog, REG_PSR_CMD); - - cmd &=3D ~(PSR_ENTER | PSR_EXIT); - - if (enter) - cmd |=3D PSR_ENTER; - else - cmd |=3D PSR_EXIT; - - msm_dp_catalog_enable_sdp(msm_dp_catalog); - msm_dp_write_link(msm_dp_catalog, REG_PSR_CMD, cmd); -} - u32 msm_dp_catalog_link_is_connected(struct msm_dp_catalog *msm_dp_catalog) { struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, @@ -484,6 +189,11 @@ u32 msm_dp_catalog_ctrl_read_psr_interrupt_status(stru= ct msm_dp_catalog *msm_dp_ return intr; } =20 +void msm_dp_catalog_ctrl_config_psr_interrupt(struct msm_dp_catalog *msm_d= p_catalog) +{ + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4); +} + int msm_dp_catalog_ctrl_get_interrupt(struct msm_dp_catalog *msm_dp_catalo= g) { u32 intr, intr_ack; @@ -498,96 +208,6 @@ int msm_dp_catalog_ctrl_get_interrupt(struct msm_dp_ca= talog *msm_dp_catalog) return intr; } =20 -void msm_dp_catalog_ctrl_phy_reset(struct msm_dp_catalog *msm_dp_catalog) -{ - msm_dp_write_ahb(msm_dp_catalog, REG_DP_PHY_CTRL, - DP_PHY_CTRL_SW_RESET | DP_PHY_CTRL_SW_RESET_PLL); - usleep_range(1000, 1100); /* h/w recommended delay */ - msm_dp_write_ahb(msm_dp_catalog, REG_DP_PHY_CTRL, 0x0); -} - -void msm_dp_catalog_ctrl_send_phy_pattern(struct msm_dp_catalog *msm_dp_ca= talog, - u32 pattern) -{ - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - u32 value =3D 0x0; - - /* Make sure to clear the current pattern before starting a new one */ - msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, 0x0); - - drm_dbg_dp(catalog->drm_dev, "pattern: %#x\n", pattern); - switch (pattern) { - case DP_PHY_TEST_PATTERN_D10_2: - msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_TRAINING_PATTERN1); - break; - case DP_PHY_TEST_PATTERN_ERROR_COUNT: - value &=3D ~(1 << 16); - msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, - value); - value |=3D SCRAMBLER_RESET_COUNT_VALUE; - msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, - value); - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_LEVELS, - DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); - msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); - break; - case DP_PHY_TEST_PATTERN_PRBS7: - msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_PRBS7); - break; - case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: - msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN); - /* 00111110000011111000001111100000 */ - msm_dp_write_link(msm_dp_catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0, - 0x3E0F83E0); - /* 00001111100000111110000011111000 */ - msm_dp_write_link(msm_dp_catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1, - 0x0F83E0F8); - /* 1111100000111110 */ - msm_dp_write_link(msm_dp_catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2, - 0x0000F83E); - break; - case DP_PHY_TEST_PATTERN_CP2520: - value =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); - value &=3D ~DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER; - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, value); - - value =3D DP_HBR2_ERM_PATTERN; - msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, - value); - value |=3D SCRAMBLER_RESET_COUNT_VALUE; - msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, - value); - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_LEVELS, - DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); - msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); - value =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); - value |=3D DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, value); - break; - case DP_PHY_TEST_PATTERN_SEL_MASK: - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, - DP_MAINLINK_CTRL_ENABLE); - msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_TRAINING_PATTERN4); - break; - default: - drm_dbg_dp(catalog->drm_dev, - "No valid test pattern requested: %#x\n", pattern); - break; - } -} - -u32 msm_dp_catalog_ctrl_read_phy_pattern(struct msm_dp_catalog *msm_dp_cat= alog) -{ - return msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_READY); -} - static void __iomem *msm_dp_ioremap(struct platform_device *pdev, int idx,= size_t *len) { struct resource *res; diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/d= p_catalog.h index 9ebdc9bd865c566efb97cf0edbdcd809e5a713e7..a7b11fc08ea595aad50f09ca8d4= 9696404514bad 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -33,7 +33,6 @@ =20 struct msm_dp_catalog { bool wide_bus_en; - u32 hw_revision; =20 void __iomem *ahb_base; size_t ahb_len; @@ -117,36 +116,16 @@ void msm_dp_catalog_snapshot(struct msm_dp_catalog *m= sm_dp_catalog, struct msm_d u32 msm_dp_catalog_aux_get_irq(struct msm_dp_catalog *msm_dp_catalog); =20 /* DP Controller APIs */ -void msm_dp_catalog_ctrl_state_ctrl(struct msm_dp_catalog *msm_dp_catalog,= u32 state); -void msm_dp_catalog_ctrl_config_ctrl(struct msm_dp_catalog *msm_dp_catalog= , u32 config); -void msm_dp_catalog_ctrl_lane_mapping(struct msm_dp_catalog *msm_dp_catalo= g); -void msm_dp_catalog_ctrl_mainlink_ctrl(struct msm_dp_catalog *msm_dp_catal= og, bool enable); -void msm_dp_catalog_ctrl_psr_mainlink_enable(struct msm_dp_catalog *msm_dp= _catalog, bool enable); -void msm_dp_catalog_setup_peripheral_flush(struct msm_dp_catalog *msm_dp_c= atalog); -void msm_dp_catalog_ctrl_config_misc(struct msm_dp_catalog *msm_dp_catalog= , u32 cc, u32 tb); -void msm_dp_catalog_ctrl_config_msa(struct msm_dp_catalog *msm_dp_catalog,= u32 rate, - u32 stream_rate_khz, bool is_ycbcr_420); -int msm_dp_catalog_ctrl_set_pattern_state_bit(struct msm_dp_catalog *msm_d= p_catalog, u32 pattern); -void msm_dp_catalog_ctrl_reset(struct msm_dp_catalog *msm_dp_catalog); -bool msm_dp_catalog_ctrl_mainlink_ready(struct msm_dp_catalog *msm_dp_cata= log); void msm_dp_catalog_ctrl_enable_irq(struct msm_dp_catalog *msm_dp_catalog,= bool enable); void msm_dp_catalog_hpd_config_intr(struct msm_dp_catalog *msm_dp_catalog, u32 intr_mask, bool en); void msm_dp_catalog_ctrl_hpd_enable(struct msm_dp_catalog *msm_dp_catalog); void msm_dp_catalog_ctrl_hpd_disable(struct msm_dp_catalog *msm_dp_catalog= ); -void msm_dp_catalog_ctrl_config_psr(struct msm_dp_catalog *msm_dp_catalog); -void msm_dp_catalog_ctrl_set_psr(struct msm_dp_catalog *msm_dp_catalog, bo= ol enter); u32 msm_dp_catalog_link_is_connected(struct msm_dp_catalog *msm_dp_catalog= ); u32 msm_dp_catalog_hpd_get_intr_status(struct msm_dp_catalog *msm_dp_catal= og); -void msm_dp_catalog_ctrl_phy_reset(struct msm_dp_catalog *msm_dp_catalog); int msm_dp_catalog_ctrl_get_interrupt(struct msm_dp_catalog *msm_dp_catalo= g); +void msm_dp_catalog_ctrl_config_psr_interrupt(struct msm_dp_catalog *msm_d= p_catalog); u32 msm_dp_catalog_ctrl_read_psr_interrupt_status(struct msm_dp_catalog *m= sm_dp_catalog); -void msm_dp_catalog_ctrl_update_transfer_unit(struct msm_dp_catalog *msm_d= p_catalog, - u32 msm_dp_tu, u32 valid_boundary, - u32 valid_boundary2); -void msm_dp_catalog_ctrl_send_phy_pattern(struct msm_dp_catalog *msm_dp_ca= talog, - u32 pattern); -u32 msm_dp_catalog_ctrl_read_phy_pattern(struct msm_dp_catalog *msm_dp_cat= alog); =20 struct msm_dp_catalog *msm_dp_catalog_get(struct device *dev); =20 diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 17f645495c4a3e6603fee688090a6ffb3f263cf0..7f676e53d098a11901ef4bcee32= 3d3ea79e53760 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -8,9 +8,11 @@ #include #include #include +#include #include #include #include +#include #include =20 #include @@ -21,6 +23,9 @@ #include "dp_ctrl.h" #include "dp_link.h" =20 +#define POLLING_SLEEP_US 1000 +#define POLLING_TIMEOUT_US 10000 + #define DP_KHZ_TO_HZ 1000 #define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES (30 * HZ / 1000) /* 30 ms = */ #define PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES (300 * HZ / 1000) /= * 300 ms */ @@ -95,6 +100,8 @@ struct msm_dp_ctrl_private { struct completion psr_op_comp; struct completion video_comp; =20 + u32 hw_revision; + bool core_clks_on; bool link_clks_on; bool stream_clks_on; @@ -119,6 +126,118 @@ static int msm_dp_aux_link_configure(struct drm_dp_au= x *aux, return 0; } =20 +/* + * NOTE: resetting DP controller will also clear any pending HPD related i= nterrupts + */ +static void msm_dp_ctrl_reset(struct msm_dp_ctrl_private *ctrl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 sw_reset; + + sw_reset =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_SW_RESET); + + sw_reset |=3D DP_SW_RESET; + msm_dp_write_ahb(msm_dp_catalog, REG_DP_SW_RESET, sw_reset); + usleep_range(1000, 1100); /* h/w recommended delay */ + + sw_reset &=3D ~DP_SW_RESET; + msm_dp_write_ahb(msm_dp_catalog, REG_DP_SW_RESET, sw_reset); + + if (!ctrl->hw_revision) { + ctrl->hw_revision =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_HW_VERSION); + ctrl->panel->hw_revision =3D ctrl->hw_revision; + } +} + +static void msm_dp_ctrl_psr_mainlink_enable(struct msm_dp_ctrl_private *ct= rl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 val; + + val =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); + val |=3D DP_MAINLINK_CTRL_ENABLE; + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, val); +} + +static void msm_dp_ctrl_psr_mainlink_disable(struct msm_dp_ctrl_private *c= trl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 val; + + val =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); + val &=3D ~DP_MAINLINK_CTRL_ENABLE; + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, val); +} + +static void msm_dp_ctrl_mainlink_enable(struct msm_dp_ctrl_private *ctrl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 mainlink_ctrl; + + drm_dbg_dp(ctrl->drm_dev, "enable\n"); + + mainlink_ctrl =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); + + mainlink_ctrl &=3D ~(DP_MAINLINK_CTRL_RESET | + DP_MAINLINK_CTRL_ENABLE); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + + mainlink_ctrl |=3D DP_MAINLINK_CTRL_RESET; + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + + mainlink_ctrl &=3D ~DP_MAINLINK_CTRL_RESET; + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + + mainlink_ctrl |=3D (DP_MAINLINK_CTRL_ENABLE | + DP_MAINLINK_FB_BOUNDARY_SEL); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); +} + +static void msm_dp_ctrl_mainlink_disable(struct msm_dp_ctrl_private *ctrl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 mainlink_ctrl; + + drm_dbg_dp(ctrl->drm_dev, "disable\n"); + + mainlink_ctrl =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); + mainlink_ctrl &=3D ~DP_MAINLINK_CTRL_ENABLE; + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); +} + +static void msm_dp_setup_peripheral_flush(struct msm_dp_ctrl_private *ctrl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 mainlink_ctrl; + + mainlink_ctrl =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); + + if (ctrl->hw_revision >=3D DP_HW_VERSION_1_2) + mainlink_ctrl |=3D DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE; + else + mainlink_ctrl |=3D DP_MAINLINK_FLUSH_MODE_UPDATE_SDP; + + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); +} + +static bool msm_dp_ctrl_mainlink_ready(struct msm_dp_ctrl_private *ctrl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 data; + int ret; + + /* Poll for mainlink ready status */ + ret =3D readl_poll_timeout(msm_dp_catalog->link_base + REG_DP_MAINLINK_RE= ADY, + data, data & DP_MAINLINK_READY_FOR_VIDEO, + POLLING_SLEEP_US, POLLING_TIMEOUT_US); + if (ret < 0) { + DRM_ERROR("mainlink not ready\n"); + return false; + } + + return true; +} + void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl) { struct msm_dp_ctrl_private *ctrl; @@ -126,7 +245,7 @@ void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_c= trl) ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); =20 reinit_completion(&ctrl->idle_comp); - msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_PUSH_IDLE); + msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_PUSH_ID= LE); =20 if (!wait_for_completion_timeout(&ctrl->idle_comp, IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES)) @@ -171,22 +290,50 @@ static void msm_dp_ctrl_config_ctrl(struct msm_dp_ctr= l_private *ctrl) if (ctrl->panel->psr_cap.version) config |=3D DP_CONFIGURATION_CTRL_SEND_VSC; =20 - msm_dp_catalog_ctrl_config_ctrl(ctrl->catalog, config); + drm_dbg_dp(ctrl->drm_dev, "DP_CONFIGURATION_CTRL=3D0x%x\n", config); + + msm_dp_write_link(ctrl->catalog, REG_DP_CONFIGURATION_CTRL, config); +} + +static void msm_dp_ctrl_lane_mapping(struct msm_dp_ctrl_private *ctrl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 ln_0 =3D 0, ln_1 =3D 1, ln_2 =3D 2, ln_3 =3D 3; /* One-to-One mapping= */ + u32 ln_mapping; + + ln_mapping =3D ln_0 << LANE0_MAPPING_SHIFT; + ln_mapping |=3D ln_1 << LANE1_MAPPING_SHIFT; + ln_mapping |=3D ln_2 << LANE2_MAPPING_SHIFT; + ln_mapping |=3D ln_3 << LANE3_MAPPING_SHIFT; + + msm_dp_write_link(msm_dp_catalog, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, + ln_mapping); } =20 static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private= *ctrl) { - u32 cc, tb; + u32 colorimetry_cfg, test_bits_depth, misc_val; =20 - msm_dp_catalog_ctrl_lane_mapping(ctrl->catalog); - msm_dp_catalog_setup_peripheral_flush(ctrl->catalog); + msm_dp_ctrl_lane_mapping(ctrl); + msm_dp_setup_peripheral_flush(ctrl); =20 msm_dp_ctrl_config_ctrl(ctrl); =20 - tb =3D msm_dp_link_get_test_bits_depth(ctrl->link, - ctrl->panel->msm_dp_mode.bpp); - cc =3D msm_dp_link_get_colorimetry_config(ctrl->link); - msm_dp_catalog_ctrl_config_misc(ctrl->catalog, cc, tb); + test_bits_depth =3D msm_dp_link_get_test_bits_depth(ctrl->link, ctrl->pan= el->msm_dp_mode.bpp); + colorimetry_cfg =3D msm_dp_link_get_colorimetry_config(ctrl->link); + + misc_val =3D msm_dp_read_link(ctrl->catalog, REG_DP_MISC1_MISC0); + + /* clear bpp bits */ + misc_val &=3D ~(0x07 << DP_MISC0_TEST_BITS_DEPTH_SHIFT); + misc_val |=3D colorimetry_cfg << DP_MISC0_COLORIMETRY_CFG_SHIFT; + misc_val |=3D test_bits_depth << DP_MISC0_TEST_BITS_DEPTH_SHIFT; + /* Configure clock to synchronous mode */ + misc_val |=3D DP_MISC0_SYNCHRONOUS_CLK; + + drm_dbg_dp(ctrl->drm_dev, "misc settings =3D 0x%x\n", misc_val); + msm_dp_write_link(ctrl->catalog, REG_DP_MISC1_MISC0, misc_val); + msm_dp_panel_timing_cfg(ctrl->panel); } =20 @@ -1003,8 +1150,9 @@ static void msm_dp_ctrl_setup_tr_unit(struct msm_dp_c= trl_private *ctrl) pr_debug("dp_tu=3D0x%x, valid_boundary=3D0x%x, valid_boundary2=3D0x%x\n", msm_dp_tu, valid_boundary, valid_boundary2); =20 - msm_dp_catalog_ctrl_update_transfer_unit(ctrl->catalog, - msm_dp_tu, valid_boundary, valid_boundary2); + msm_dp_write_link(ctrl->catalog, REG_DP_VALID_BOUNDARY, valid_boundary); + msm_dp_write_link(ctrl->catalog, REG_DP_TU, msm_dp_tu); + msm_dp_write_link(ctrl->catalog, REG_DP_VALID_BOUNDARY_2, valid_boundary2= ); } =20 static int msm_dp_ctrl_wait4video_ready(struct msm_dp_ctrl_private *ctrl) @@ -1113,6 +1261,30 @@ static bool msm_dp_ctrl_train_pattern_set(struct msm= _dp_ctrl_private *ctrl, return ret =3D=3D 1; } =20 +static int msm_dp_ctrl_set_pattern_state_bit(struct msm_dp_ctrl_private *c= trl, + u32 state_bit) +{ + int bit, ret; + u32 data; + + bit =3D BIT(state_bit - 1); + drm_dbg_dp(ctrl->drm_dev, "hw: bit=3D%d train=3D%d\n", bit, state_bit); + msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, bit); + + bit =3D BIT(state_bit - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT; + + /* Poll for mainlink ready status */ + ret =3D readx_poll_timeout(readl, ctrl->catalog->link_base + REG_DP_MAINL= INK_READY, + data, data & bit, + POLLING_SLEEP_US, POLLING_TIMEOUT_US); + if (ret < 0) { + DRM_ERROR("set state_bit for link_train=3D%d failed\n", state_bit); + return ret; + } + + return 0; +} + static int msm_dp_ctrl_link_train_1(struct msm_dp_ctrl_private *ctrl, int *training_step, enum drm_dp_phy dp_phy) { @@ -1124,11 +1296,11 @@ static int msm_dp_ctrl_link_train_1(struct msm_dp_c= trl_private *ctrl, delay_us =3D drm_dp_read_clock_recovery_delay(ctrl->aux, ctrl->panel->dpcd, dp_phy, false); =20 - msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); + msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, 0); =20 *training_step =3D DP_TRAINING_1; =20 - ret =3D msm_dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, 1); + ret =3D msm_dp_ctrl_set_pattern_state_bit(ctrl, 1); if (ret) return ret; msm_dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 | @@ -1242,7 +1414,7 @@ static int msm_dp_ctrl_link_train_2(struct msm_dp_ctr= l_private *ctrl, delay_us =3D drm_dp_read_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd, dp_phy, false); =20 - msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); + msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, 0); =20 *training_step =3D DP_TRAINING_2; =20 @@ -1257,7 +1429,7 @@ static int msm_dp_ctrl_link_train_2(struct msm_dp_ctr= l_private *ctrl, state_ctrl_bit =3D 2; } =20 - ret =3D msm_dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, state_ct= rl_bit); + ret =3D msm_dp_ctrl_set_pattern_state_bit(ctrl, state_ctrl_bit); if (ret) return ret; =20 @@ -1359,7 +1531,7 @@ static int msm_dp_ctrl_link_train(struct msm_dp_ctrl_= private *ctrl, } =20 end: - msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); + msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, 0); =20 return ret; } @@ -1369,7 +1541,7 @@ static int msm_dp_ctrl_setup_main_link(struct msm_dp_= ctrl_private *ctrl, { int ret =3D 0; =20 - msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); + msm_dp_ctrl_mainlink_enable(ctrl); =20 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) return ret; @@ -1508,7 +1680,7 @@ void msm_dp_ctrl_reset_irq_ctrl(struct msm_dp_ctrl *m= sm_dp_ctrl, bool enable) =20 ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); =20 - msm_dp_catalog_ctrl_reset(ctrl->catalog); + msm_dp_ctrl_reset(ctrl); =20 /* * all dp controller programmable registers will not @@ -1519,16 +1691,60 @@ void msm_dp_ctrl_reset_irq_ctrl(struct msm_dp_ctrl = *msm_dp_ctrl, bool enable) msm_dp_catalog_ctrl_enable_irq(ctrl->catalog, enable); } =20 +static void msm_dp_ctrl_enable_sdp(struct msm_dp_ctrl_private *ctrl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + + /* trigger sdp */ + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, UPDATE_SDP); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, 0x0); +} + +static void msm_dp_ctrl_psr_enter(struct msm_dp_ctrl_private *ctrl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 cmd; + + cmd =3D msm_dp_read_link(msm_dp_catalog, REG_PSR_CMD); + + cmd &=3D ~(PSR_ENTER | PSR_EXIT); + cmd |=3D PSR_ENTER; + + msm_dp_ctrl_enable_sdp(ctrl); + msm_dp_write_link(msm_dp_catalog, REG_PSR_CMD, cmd); +} + +static void msm_dp_ctrl_psr_exit(struct msm_dp_ctrl_private *ctrl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 cmd; + + cmd =3D msm_dp_read_link(msm_dp_catalog, REG_PSR_CMD); + + cmd &=3D ~(PSR_ENTER | PSR_EXIT); + cmd |=3D PSR_EXIT; + + msm_dp_ctrl_enable_sdp(ctrl); + msm_dp_write_link(msm_dp_catalog, REG_PSR_CMD, cmd); +} + void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm_dp_ctrl) { - u8 cfg; struct msm_dp_ctrl_private *ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 cfg; =20 if (!ctrl->panel->psr_cap.version) return; =20 - msm_dp_catalog_ctrl_config_psr(ctrl->catalog); + /* enable PSR1 function */ + cfg =3D msm_dp_read_link(msm_dp_catalog, REG_PSR_CONFIG); + cfg |=3D PSR1_SUPPORTED; + msm_dp_write_link(msm_dp_catalog, REG_PSR_CONFIG, cfg); + + msm_dp_catalog_ctrl_config_psr_interrupt(msm_dp_catalog); + msm_dp_ctrl_enable_sdp(ctrl); =20 cfg =3D DP_PSR_ENABLE; drm_dp_dpcd_write(ctrl->aux, DP_PSR_EN_CFG, &cfg, 1); @@ -1554,29 +1770,37 @@ void msm_dp_ctrl_set_psr(struct msm_dp_ctrl *msm_dp= _ctrl, bool enter) */ if (enter) { reinit_completion(&ctrl->psr_op_comp); - msm_dp_catalog_ctrl_set_psr(ctrl->catalog, true); + msm_dp_ctrl_psr_enter(ctrl); =20 if (!wait_for_completion_timeout(&ctrl->psr_op_comp, PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES)) { DRM_ERROR("PSR_ENTRY timedout\n"); - msm_dp_catalog_ctrl_set_psr(ctrl->catalog, false); + msm_dp_ctrl_psr_exit(ctrl); return; } =20 msm_dp_ctrl_push_idle(msm_dp_ctrl); - msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); + msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, 0); =20 - msm_dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, false); + msm_dp_ctrl_psr_mainlink_disable(ctrl); } else { - msm_dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, true); + msm_dp_ctrl_psr_mainlink_enable(ctrl); =20 - msm_dp_catalog_ctrl_set_psr(ctrl->catalog, false); - msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); + msm_dp_ctrl_psr_exit(ctrl); + msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_V= IDEO); msm_dp_ctrl_wait4video_ready(ctrl); - msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); + msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, 0); } } =20 +static void msm_dp_ctrl_phy_reset(struct msm_dp_ctrl_private *ctrl) +{ + msm_dp_write_ahb(ctrl->catalog, REG_DP_PHY_CTRL, + DP_PHY_CTRL_SW_RESET | DP_PHY_CTRL_SW_RESET_PLL); + usleep_range(1000, 1100); /* h/w recommended delay */ + msm_dp_write_ahb(ctrl->catalog, REG_DP_PHY_CTRL, 0x0); +} + void msm_dp_ctrl_phy_init(struct msm_dp_ctrl *msm_dp_ctrl) { struct msm_dp_ctrl_private *ctrl; @@ -1585,7 +1809,7 @@ void msm_dp_ctrl_phy_init(struct msm_dp_ctrl *msm_dp_= ctrl) ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); phy =3D ctrl->phy; =20 - msm_dp_catalog_ctrl_phy_reset(ctrl->catalog); + msm_dp_ctrl_phy_reset(ctrl); phy_init(phy); =20 drm_dbg_dp(ctrl->drm_dev, "phy=3D%p init=3D%d power_on=3D%d\n", @@ -1600,7 +1824,7 @@ void msm_dp_ctrl_phy_exit(struct msm_dp_ctrl *msm_dp_= ctrl) ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); phy =3D ctrl->phy; =20 - msm_dp_catalog_ctrl_phy_reset(ctrl->catalog); + msm_dp_ctrl_phy_reset(ctrl); phy_exit(phy); drm_dbg_dp(ctrl->drm_dev, "phy=3D%p init=3D%d power_on=3D%d\n", phy, phy->init_count, phy->power_count); @@ -1611,7 +1835,7 @@ static int msm_dp_ctrl_reinitialize_mainlink(struct m= sm_dp_ctrl_private *ctrl) struct phy *phy =3D ctrl->phy; int ret =3D 0; =20 - msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); + msm_dp_ctrl_mainlink_disable(ctrl); ctrl->phy_opts.dp.lanes =3D ctrl->link->link_params.num_lanes; phy_configure(phy, &ctrl->phy_opts); /* @@ -1642,9 +1866,9 @@ static int msm_dp_ctrl_deinitialize_mainlink(struct m= sm_dp_ctrl_private *ctrl) =20 phy =3D ctrl->phy; =20 - msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); + msm_dp_ctrl_mainlink_disable(ctrl); =20 - msm_dp_catalog_ctrl_reset(ctrl->catalog); + msm_dp_ctrl_reset(ctrl); =20 dev_pm_opp_set_rate(ctrl->dev, 0); msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); @@ -1676,13 +1900,97 @@ static int msm_dp_ctrl_link_maintenance(struct msm_= dp_ctrl_private *ctrl) =20 msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); =20 - msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); + msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VI= DEO); =20 ret =3D msm_dp_ctrl_wait4video_ready(ctrl); end: return ret; } =20 +#define SCRAMBLER_RESET_COUNT_VALUE 0xFC + +static void msm_dp_ctrl_send_phy_pattern(struct msm_dp_ctrl_private *ctrl, + u32 pattern) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 value =3D 0x0; + + /* Make sure to clear the current pattern before starting a new one */ + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, 0x0); + + drm_dbg_dp(ctrl->drm_dev, "pattern: %#x\n", pattern); + switch (pattern) { + case DP_PHY_TEST_PATTERN_D10_2: + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_TRAINING_PATTERN1); + break; + + case DP_PHY_TEST_PATTERN_ERROR_COUNT: + value &=3D ~(1 << 16); + msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + value); + value |=3D SCRAMBLER_RESET_COUNT_VALUE; + msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + value); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_LEVELS, + DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); + break; + + case DP_PHY_TEST_PATTERN_PRBS7: + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_PRBS7); + break; + + case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN); + /* 00111110000011111000001111100000 */ + msm_dp_write_link(msm_dp_catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0, + 0x3E0F83E0); + /* 00001111100000111110000011111000 */ + msm_dp_write_link(msm_dp_catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1, + 0x0F83E0F8); + /* 1111100000111110 */ + msm_dp_write_link(msm_dp_catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2, + 0x0000F83E); + break; + + case DP_PHY_TEST_PATTERN_CP2520: + value =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); + value &=3D ~DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER; + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, value); + + value =3D DP_HBR2_ERM_PATTERN; + msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + value); + value |=3D SCRAMBLER_RESET_COUNT_VALUE; + msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + value); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_LEVELS, + DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); + value =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); + value |=3D DP_MAINLINK_CTRL_ENABLE; + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, value); + break; + + case DP_PHY_TEST_PATTERN_SEL_MASK: + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, + DP_MAINLINK_CTRL_ENABLE); + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_TRAINING_PATTERN4); + break; + + default: + drm_dbg_dp(ctrl->drm_dev, + "No valid test pattern requested: %#x\n", pattern); + break; + } +} + static bool msm_dp_ctrl_send_phy_test_pattern(struct msm_dp_ctrl_private *= ctrl) { bool success =3D false; @@ -1697,11 +2005,11 @@ static bool msm_dp_ctrl_send_phy_test_pattern(struc= t msm_dp_ctrl_private *ctrl) DRM_ERROR("Failed to set v/p levels\n"); return false; } - msm_dp_catalog_ctrl_send_phy_pattern(ctrl->catalog, pattern_requested); + msm_dp_ctrl_send_phy_pattern(ctrl, pattern_requested); msm_dp_ctrl_update_phy_vx_px(ctrl, DP_PHY_DPRX); msm_dp_link_send_test_response(ctrl->link); =20 - pattern_sent =3D msm_dp_catalog_ctrl_read_phy_pattern(ctrl->catalog); + pattern_sent =3D msm_dp_read_link(ctrl->catalog, REG_DP_MAINLINK_READY); =20 switch (pattern_sent) { case MR_LINK_TRAINING1: @@ -1980,6 +2288,62 @@ static int msm_dp_ctrl_link_retrain(struct msm_dp_ct= rl_private *ctrl) return msm_dp_ctrl_setup_main_link(ctrl, &training_step); } =20 +static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl, + u32 rate, u32 stream_rate_khz, + bool is_ycbcr_420) +{ + u32 pixel_m, pixel_n; + u32 mvid, nvid, pixel_div =3D 0, dispcc_input_rate; + u32 const nvid_fixed =3D DP_LINK_CONSTANT_N_VALUE; + u32 const link_rate_hbr2 =3D 540000; + u32 const link_rate_hbr3 =3D 810000; + unsigned long den, num; + + if (rate =3D=3D link_rate_hbr3) + pixel_div =3D 6; + else if (rate =3D=3D 162000 || rate =3D=3D 270000) + pixel_div =3D 2; + else if (rate =3D=3D link_rate_hbr2) + pixel_div =3D 4; + else + DRM_ERROR("Invalid pixel mux divider\n"); + + dispcc_input_rate =3D (rate * 10) / pixel_div; + + rational_best_approximation(dispcc_input_rate, stream_rate_khz, + (unsigned long)(1 << 16) - 1, + (unsigned long)(1 << 16) - 1, &den, &num); + + den =3D ~(den - num); + den =3D den & 0xFFFF; + pixel_m =3D num; + pixel_n =3D den; + + mvid =3D (pixel_m & 0xFFFF) * 5; + nvid =3D (0xFFFF & (~pixel_n)) + (pixel_m & 0xFFFF); + + if (nvid < nvid_fixed) { + u32 temp; + + temp =3D (nvid_fixed / nvid) * nvid; + mvid =3D (nvid_fixed / nvid) * mvid; + nvid =3D temp; + } + + if (is_ycbcr_420) + mvid /=3D 2; + + if (link_rate_hbr2 =3D=3D rate) + nvid *=3D 2; + + if (link_rate_hbr3 =3D=3D rate) + nvid *=3D 3; + + drm_dbg_dp(ctrl->drm_dev, "mvid=3D0x%x, nvid=3D0x%x\n", mvid, nvid); + msm_dp_write_link(ctrl->catalog, REG_DP_SOFTWARE_MVID, mvid); + msm_dp_write_link(ctrl->catalog, REG_DP_SOFTWARE_NVID, nvid); +} + int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link= _train) { int ret =3D 0; @@ -2045,7 +2409,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl, bool force_link_train =20 msm_dp_ctrl_configure_source_params(ctrl); =20 - msm_dp_catalog_ctrl_config_msa(ctrl->catalog, + msm_dp_ctrl_config_msa(ctrl, ctrl->link->link_params.rate, pixel_rate_orig, ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420); @@ -2054,13 +2418,13 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_d= p_ctrl, bool force_link_train =20 msm_dp_ctrl_setup_tr_unit(ctrl); =20 - msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); + msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VI= DEO); =20 ret =3D msm_dp_ctrl_wait4video_ready(ctrl); if (ret) return ret; =20 - mainlink_ready =3D msm_dp_catalog_ctrl_mainlink_ready(ctrl->catalog); + mainlink_ready =3D msm_dp_ctrl_mainlink_ready(ctrl); drm_dbg_dp(ctrl->drm_dev, "mainlink %s\n", mainlink_ready ? "READY" : "NOT READY"); =20 @@ -2081,7 +2445,7 @@ void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl *= msm_dp_ctrl) /* set dongle to D3 (power off) mode */ msm_dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true); =20 - msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); + msm_dp_ctrl_mainlink_disable(ctrl); =20 if (ctrl->stream_clks_on) { clk_disable_unprepare(ctrl->pixel_clk); @@ -2109,7 +2473,7 @@ void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_= ctrl) ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); phy =3D ctrl->phy; =20 - msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); + msm_dp_ctrl_mainlink_disable(ctrl); =20 dev_pm_opp_set_rate(ctrl->dev, 0); msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); @@ -2133,9 +2497,9 @@ void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl) =20 msm_dp_panel_disable_vsc_sdp(ctrl->panel); =20 - msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); + msm_dp_ctrl_mainlink_disable(ctrl); =20 - msm_dp_catalog_ctrl_reset(ctrl->catalog); + msm_dp_ctrl_reset(ctrl); =20 if (ctrl->stream_clks_on) { clk_disable_unprepare(ctrl->pixel_clk); diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index 53eaa9d3629ceae0bc127a605056419bdc4ac7a2..ce7e710a0ded1fc2703dc16b1fa= 3bd61d47714cb 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -390,7 +390,7 @@ static void msm_dp_panel_send_vsc_sdp(struct msm_dp_pan= el_private *panel, struct =20 static void msm_dp_panel_update_sdp(struct msm_dp_panel_private *panel) { - u32 hw_revision =3D panel->catalog->hw_revision; + u32 hw_revision =3D panel->msm_dp_panel.hw_revision; =20 if (hw_revision >=3D DP_HW_VERSION_1_0 && hw_revision < DP_HW_VERSION_1_2) { diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_= panel.h index 8dde55b3a5ab64c0c12d69cb2dd5b5c733c83432..c348417bb07f33efdf1402a73c2= 7ff99e394e5a3 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -38,6 +38,7 @@ struct msm_dp_panel { struct msm_dp_panel_psr psr_cap; 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Reviewed-by: Stephen Boyd Tested-by: Stephen Boyd # sc7180-trogdor Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_aux.c | 94 +++++++++++++++++++++++++++++++++= +++- drivers/gpu/drm/msm/dp/dp_aux.h | 7 +++ drivers/gpu/drm/msm/dp/dp_catalog.c | 75 +---------------------------- drivers/gpu/drm/msm/dp/dp_catalog.h | 6 --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 4 +- drivers/gpu/drm/msm/dp/dp_display.c | 18 ++++--- drivers/gpu/drm/msm/dp/dp_panel.c | 2 +- 7 files changed, 113 insertions(+), 93 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_aux.c b/drivers/gpu/drm/msm/dp/dp_au= x.c index cdcab948ae7086964d9e913dadadacc333f46231..f8ea1754665afa37ff9dbaf3f88= 3d94c48bf07b8 100644 --- a/drivers/gpu/drm/msm/dp/dp_aux.c +++ b/drivers/gpu/drm/msm/dp/dp_aux.c @@ -403,7 +403,7 @@ static ssize_t msm_dp_aux_transfer(struct drm_dp_aux *m= sm_dp_aux, phy_calibrate(aux->phy); } /* reset aux if link is in connected state */ - if (msm_dp_catalog_link_is_connected(aux->catalog)) + if (msm_dp_aux_is_link_connected(msm_dp_aux)) msm_dp_aux_reset(aux); } else { aux->retry_cnt =3D 0; @@ -591,6 +591,98 @@ static int msm_dp_wait_hpd_asserted(struct drm_dp_aux = *msm_dp_aux, return ret; } =20 +void msm_dp_aux_hpd_enable(struct drm_dp_aux *msm_dp_aux) +{ + struct msm_dp_aux_private *aux =3D + container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); + struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; + u32 reg; + + /* Configure REFTIMER and enable it */ + reg =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER); + reg |=3D DP_DP_HPD_REFTIMER_ENABLE; + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER, reg); + + /* Enable HPD */ + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_E= N); +} + +void msm_dp_aux_hpd_disable(struct drm_dp_aux *msm_dp_aux) +{ + struct msm_dp_aux_private *aux =3D + container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); + struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; + u32 reg; + + reg =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER); + reg &=3D ~DP_DP_HPD_REFTIMER_ENABLE; + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER, reg); + + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_CTRL, 0); +} + +void msm_dp_aux_hpd_intr_enable(struct drm_dp_aux *msm_dp_aux) +{ + struct msm_dp_aux_private *aux =3D + container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); + struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; + u32 reg; + + reg =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK); + reg |=3D DP_DP_HPD_INT_MASK; + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK, + reg & DP_DP_HPD_INT_MASK); +} + +void msm_dp_aux_hpd_intr_disable(struct drm_dp_aux *msm_dp_aux) +{ + struct msm_dp_aux_private *aux =3D + container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); + struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; + u32 reg; + + reg =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK); + reg &=3D ~DP_DP_HPD_INT_MASK; + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK, + reg & DP_DP_HPD_INT_MASK); +} + +u32 msm_dp_aux_get_hpd_intr_status(struct drm_dp_aux *msm_dp_aux) +{ + struct msm_dp_aux_private *aux =3D + container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); + struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; + int isr, mask; + + isr =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_STATUS); + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_ACK, + (isr & DP_DP_HPD_INT_MASK)); + mask =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK); + + /* + * We only want to return interrupts that are unmasked to the caller. + * However, the interrupt status field also contains other + * informational bits about the HPD state status, so we only mask + * out the part of the register that tells us about which interrupts + * are pending. + */ + return isr & (mask | ~DP_DP_HPD_INT_MASK); +} + +u32 msm_dp_aux_is_link_connected(struct drm_dp_aux *msm_dp_aux) +{ + struct msm_dp_aux_private *aux =3D + container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); + struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; + u32 status; + + status =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_STATUS); + status >>=3D DP_DP_HPD_STATE_STATUS_BITS_SHIFT; + status &=3D DP_DP_HPD_STATE_STATUS_BITS_MASK; + + return status; +} + struct drm_dp_aux *msm_dp_aux_get(struct device *dev, struct msm_dp_catalo= g *catalog, struct phy *phy, bool is_edp) diff --git a/drivers/gpu/drm/msm/dp/dp_aux.h b/drivers/gpu/drm/msm/dp/dp_au= x.h index 39c5b4c8596ab28d822493a6b4d479f5f786cdee..624395a41ed0a75ead4826e78d0= 5ca21e8fb8967 100644 --- a/drivers/gpu/drm/msm/dp/dp_aux.h +++ b/drivers/gpu/drm/msm/dp/dp_aux.h @@ -17,6 +17,13 @@ void msm_dp_aux_init(struct drm_dp_aux *msm_dp_aux); void msm_dp_aux_deinit(struct drm_dp_aux *msm_dp_aux); void msm_dp_aux_reconfig(struct drm_dp_aux *msm_dp_aux); =20 +void msm_dp_aux_hpd_enable(struct drm_dp_aux *msm_dp_aux); +void msm_dp_aux_hpd_disable(struct drm_dp_aux *msm_dp_aux); +void msm_dp_aux_hpd_intr_enable(struct drm_dp_aux *msm_dp_aux); +void msm_dp_aux_hpd_intr_disable(struct drm_dp_aux *msm_dp_aux); +u32 msm_dp_aux_get_hpd_intr_status(struct drm_dp_aux *msm_dp_aux); +u32 msm_dp_aux_is_link_connected(struct drm_dp_aux *msm_dp_aux); + struct phy; struct drm_dp_aux *msm_dp_aux_get(struct device *dev, struct msm_dp_catalo= g *catalog, struct phy *phy, diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/d= p_catalog.c index 7021effc7020073b8b7f633b96286e3996d78d6e..9d6d59264a592cc3ae312b35e51= d48c11bd141e6 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -85,8 +85,8 @@ u32 msm_dp_catalog_aux_get_irq(struct msm_dp_catalog *msm= _dp_catalog) intr &=3D ~DP_INTERRUPT_STATUS1_MASK; intr_ack =3D (intr & DP_INTERRUPT_STATUS1) << DP_INTERRUPT_STATUS_ACK_SHIFT; - msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, intr_ack | - DP_INTERRUPT_STATUS1_MASK); + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, + intr_ack | DP_INTERRUPT_STATUS1_MASK); =20 return intr; =20 @@ -106,77 +106,6 @@ void msm_dp_catalog_ctrl_enable_irq(struct msm_dp_cata= log *msm_dp_catalog, } } =20 -void msm_dp_catalog_hpd_config_intr(struct msm_dp_catalog *msm_dp_catalog, - u32 intr_mask, bool en) -{ - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - u32 config =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK); - - config =3D (en ? config | intr_mask : config & ~intr_mask); - - drm_dbg_dp(catalog->drm_dev, "intr_mask=3D%#x config=3D%#x\n", - intr_mask, config); - msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK, - config & DP_DP_HPD_INT_MASK); -} - -void msm_dp_catalog_ctrl_hpd_enable(struct msm_dp_catalog *msm_dp_catalog) -{ - u32 reftimer =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER); - - /* Configure REFTIMER and enable it */ - reftimer |=3D DP_DP_HPD_REFTIMER_ENABLE; - msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER, reftimer); - - /* Enable HPD */ - msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_E= N); -} - -void msm_dp_catalog_ctrl_hpd_disable(struct msm_dp_catalog *msm_dp_catalog) -{ - u32 reftimer =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER); - - reftimer &=3D ~DP_DP_HPD_REFTIMER_ENABLE; - msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER, reftimer); - - msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_CTRL, 0); -} - -u32 msm_dp_catalog_link_is_connected(struct msm_dp_catalog *msm_dp_catalog) -{ - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - u32 status; - - status =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_STATUS); - drm_dbg_dp(catalog->drm_dev, "aux status: %#x\n", status); - status >>=3D DP_DP_HPD_STATE_STATUS_BITS_SHIFT; - status &=3D DP_DP_HPD_STATE_STATUS_BITS_MASK; - - return status; -} - -u32 msm_dp_catalog_hpd_get_intr_status(struct msm_dp_catalog *msm_dp_catal= og) -{ - int isr, mask; - - isr =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_STATUS); - msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_ACK, - (isr & DP_DP_HPD_INT_MASK)); - mask =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK); - - /* - * We only want to return interrupts that are unmasked to the caller. - * However, the interrupt status field also contains other - * informational bits about the HPD state status, so we only mask - * out the part of the register that tells us about which interrupts - * are pending. - */ - return isr & (mask | ~DP_DP_HPD_INT_MASK); -} - u32 msm_dp_catalog_ctrl_read_psr_interrupt_status(struct msm_dp_catalog *m= sm_dp_catalog) { u32 intr, intr_ack; diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/d= p_catalog.h index a7b11fc08ea595aad50f09ca8d49696404514bad..5196188059f3ade2b6cc260ee65= a7efb38844664 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -117,12 +117,6 @@ u32 msm_dp_catalog_aux_get_irq(struct msm_dp_catalog *= msm_dp_catalog); =20 /* DP Controller APIs */ void msm_dp_catalog_ctrl_enable_irq(struct msm_dp_catalog *msm_dp_catalog,= bool enable); -void msm_dp_catalog_hpd_config_intr(struct msm_dp_catalog *msm_dp_catalog, - u32 intr_mask, bool en); -void msm_dp_catalog_ctrl_hpd_enable(struct msm_dp_catalog *msm_dp_catalog); -void msm_dp_catalog_ctrl_hpd_disable(struct msm_dp_catalog *msm_dp_catalog= ); -u32 msm_dp_catalog_link_is_connected(struct msm_dp_catalog *msm_dp_catalog= ); -u32 msm_dp_catalog_hpd_get_intr_status(struct msm_dp_catalog *msm_dp_catal= og); int msm_dp_catalog_ctrl_get_interrupt(struct msm_dp_catalog *msm_dp_catalo= g); void msm_dp_catalog_ctrl_config_psr_interrupt(struct msm_dp_catalog *msm_d= p_catalog); u32 msm_dp_catalog_ctrl_read_psr_interrupt_status(struct msm_dp_catalog *m= sm_dp_catalog); diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 7f676e53d098a11901ef4bcee323d3ea79e53760..97a5f854f8344962c36e67d1cca= 480c1d5a3ef00 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2206,7 +2206,7 @@ int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ct= rl) break; } else if (training_step =3D=3D DP_TRAINING_1) { /* link train_1 failed */ - if (!msm_dp_catalog_link_is_connected(ctrl->catalog)) + if (!msm_dp_aux_is_link_connected(ctrl->aux)) break; =20 drm_dp_dpcd_read_link_status(ctrl->aux, link_status); @@ -2231,7 +2231,7 @@ int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ct= rl) } } else if (training_step =3D=3D DP_TRAINING_2) { /* link train_2 failed */ - if (!msm_dp_catalog_link_is_connected(ctrl->catalog)) + if (!msm_dp_aux_is_link_connected(ctrl->aux)) break; =20 drm_dp_dpcd_read_link_status(ctrl->aux, link_status); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 386c4669c831ebc0d4b567086cde8d818bcdd095..8b79eebe68cb40b7c640c559e8e= da400ee1b5f0a 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -1143,7 +1143,7 @@ static irqreturn_t msm_dp_display_irq_handler(int irq= , void *dev_id) return IRQ_NONE; } =20 - hpd_isr_status =3D msm_dp_catalog_hpd_get_intr_status(dp->catalog); + hpd_isr_status =3D msm_dp_aux_get_hpd_intr_status(dp->aux); =20 if (hpd_isr_status & 0x0F) { drm_dbg_dp(dp->drm_dev, "type=3D%d isr=3D0x%x\n", @@ -1358,7 +1358,7 @@ static int msm_dp_pm_runtime_suspend(struct device *d= ev) =20 if (dp->msm_dp_display.is_edp) { msm_dp_display_host_phy_exit(dp); - msm_dp_catalog_ctrl_hpd_disable(dp->catalog); + msm_dp_aux_hpd_disable(dp->aux); } msm_dp_display_host_deinit(dp); =20 @@ -1379,7 +1379,7 @@ static int msm_dp_pm_runtime_resume(struct device *de= v) */ msm_dp_display_host_init(dp); if (dp->msm_dp_display.is_edp) { - msm_dp_catalog_ctrl_hpd_enable(dp->catalog); + msm_dp_aux_hpd_enable(dp->aux); msm_dp_display_host_phy_init(dp); } =20 @@ -1666,10 +1666,8 @@ void msm_dp_bridge_hpd_enable(struct drm_bridge *bri= dge) return; } =20 - msm_dp_catalog_ctrl_hpd_enable(dp->catalog); - - /* enable HDP interrupts */ - msm_dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_INT_MASK, true); + msm_dp_aux_hpd_enable(dp->aux); + msm_dp_aux_hpd_intr_enable(dp->aux); =20 msm_dp_display->internal_hpd =3D true; mutex_unlock(&dp->event_mutex); @@ -1682,9 +1680,9 @@ void msm_dp_bridge_hpd_disable(struct drm_bridge *bri= dge) struct msm_dp_display_private *dp =3D container_of(msm_dp_display, struct= msm_dp_display_private, msm_dp_display); =20 mutex_lock(&dp->event_mutex); - /* disable HDP interrupts */ - msm_dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_INT_MASK, false); - msm_dp_catalog_ctrl_hpd_disable(dp->catalog); + + msm_dp_aux_hpd_intr_disable(dp->aux); + msm_dp_aux_hpd_disable(dp->aux); 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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-328084ca34csm14186881fa.30.2025.05.18.04.21.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 May 2025 04:21:56 -0700 (PDT) From: Dmitry Baryshkov Date: Sun, 18 May 2025 14:21:43 +0300 Subject: [PATCH v6 10/11] drm/msm/dp: move interrupt handling to dp_ctrl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250518-fd-dp-audio-fixup-v6-10-2f0ec3ec000d@oss.qualcomm.com> References: <20250518-fd-dp-audio-fixup-v6-0-2f0ec3ec000d@oss.qualcomm.com> In-Reply-To: <20250518-fd-dp-audio-fixup-v6-0-2f0ec3ec000d@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Paloma Arellano Cc: Douglas Anderson , Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=19061; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=cFB/1SPdrLDKUZGU0gY44Ya69wm6tzku95/Qa+NMhDg=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoKcLAc+RgcxPtqsHlrM82y02hcjl1KskhOAHg7 yK8thmIVMOJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaCnCwAAKCRCLPIo+Aiko 1UllB/9FA6xSNSn5kCXhwm6y+GNthIPcqWTGch21Klg/+j41mHzYk2U15m7e6cJqz1WT8HNjJNf ZQuzb7f7AoQV1TO6ZirDNHQeQayZfhlQkKQrrTvnKi1VpMfJHBLCxVJ7zLqktC8GgWPdl36ojkX 9cBx+31kCtfhNLpkV/x4TYmlSRSqVSLwvSCojT34kRMDHaqr3mu/956yoU1gGPEn/LznwS3Hfc7 jKGKovA0BTNAcJ2h9DHkY2YQjRW1YN5C99W/UdwwY0Lm3SHdrOi3AoOHC93C2hHTFraspoZKLbd YRArwRiMICGZJuXkWF0MTkNRKT1KKXOMdQ8OhOtZUNrhoTXb X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: d16dK-t3f9VsvcZ_ld_WtWFLeLaKr0ac X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE4MDEwOCBTYWx0ZWRfXz3ueoKzatE4m HU3MquZIircQNvn1NxGenVQuD5/R3/lJ7xvf/jYP/cARNfIr4uGA6U7WbGNATeLPwEop6DWhdcm 5vDf3Fwq2ttNJiCBXBW8sRvxiZHxcjNk80FXBN6wtKnSrLhlwvaD/ZTIWkWb72daKJ6fLaq62QE SnSUZhu8E5HP5Pn4/QydgUUlHd5A62uW3m5pwX+nOtbe9D7Bu+QWks/Afag+ebW79O7E8Nsa05m yiFHt7AWJdU8WLxllHo4bHvYjbvr71Z8UHTQYphV2/MKN7sUhcnZVCcNNhgBqfxCIQUol/zXvxz peJnOBoozbt0TsBh/DFI1Cq2e7RFxpebfH80Fr8xH+sWdEnO7gsY6PP916FGxsg0s8VcvM+Mixq fr6rilWqb2zdsoFuh9DpAqO134RbqzOiE263us72AFyYf09cc/byhX1ITjjebeIOwb3EgIr1 X-Authority-Analysis: v=2.4 cv=H8Pbw/Yi c=1 sm=1 tr=0 ts=6829c2da cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=KKAkSRfTAAAA:8 a=cm27Pg_UAAAA:8 a=cQV4YECOshyG1Dae9JAA:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: d16dK-t3f9VsvcZ_ld_WtWFLeLaKr0ac X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-18_06,2025-05-16_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 mlxlogscore=999 adultscore=0 phishscore=0 mlxscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 impostorscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505180108 From: Dmitry Baryshkov It makes it easier to keep all interrupts-related code in dp_ctrl submodule. Move all functions to dp_ctrl.c. Reviewed-by: Stephen Boyd Tested-by: Stephen Boyd # sc7180-trogdor Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_aux.c | 9 +-- drivers/gpu/drm/msm/dp/dp_aux.h | 2 +- drivers/gpu/drm/msm/dp/dp_catalog.c | 95 ------------------------ drivers/gpu/drm/msm/dp/dp_catalog.h | 26 ------- drivers/gpu/drm/msm/dp/dp_ctrl.c | 142 ++++++++++++++++++++++++++++++--= ---- drivers/gpu/drm/msm/dp/dp_ctrl.h | 5 +- drivers/gpu/drm/msm/dp/dp_display.c | 9 +-- drivers/gpu/drm/msm/dp/dp_reg.h | 17 +++++ 8 files changed, 145 insertions(+), 160 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_aux.c b/drivers/gpu/drm/msm/dp/dp_au= x.c index f8ea1754665afa37ff9dbaf3f883d94c48bf07b8..d7a38fa5d64d618af463416edf1= 3bef79d6b53ba 100644 --- a/drivers/gpu/drm/msm/dp/dp_aux.c +++ b/drivers/gpu/drm/msm/dp/dp_aux.c @@ -437,9 +437,8 @@ static ssize_t msm_dp_aux_transfer(struct drm_dp_aux *m= sm_dp_aux, return ret; } =20 -irqreturn_t msm_dp_aux_isr(struct drm_dp_aux *msm_dp_aux) +irqreturn_t msm_dp_aux_isr(struct drm_dp_aux *msm_dp_aux, u32 isr) { - u32 isr; struct msm_dp_aux_private *aux; =20 if (!msm_dp_aux) { @@ -449,12 +448,6 @@ irqreturn_t msm_dp_aux_isr(struct drm_dp_aux *msm_dp_a= ux) =20 aux =3D container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); =20 - isr =3D msm_dp_catalog_aux_get_irq(aux->catalog); - - /* no interrupts pending, return immediately */ - if (!isr) - return IRQ_NONE; - if (!aux->cmd_busy) { DRM_ERROR("Unexpected DP AUX IRQ %#010x when not busy\n", isr); return IRQ_NONE; diff --git a/drivers/gpu/drm/msm/dp/dp_aux.h b/drivers/gpu/drm/msm/dp/dp_au= x.h index 624395a41ed0a75ead4826e78d05ca21e8fb8967..83908c93b6a1baa6c4eb83a346b= 4498704008ca5 100644 --- a/drivers/gpu/drm/msm/dp/dp_aux.h +++ b/drivers/gpu/drm/msm/dp/dp_aux.h @@ -11,7 +11,7 @@ =20 int msm_dp_aux_register(struct drm_dp_aux *msm_dp_aux); void msm_dp_aux_unregister(struct drm_dp_aux *msm_dp_aux); -irqreturn_t msm_dp_aux_isr(struct drm_dp_aux *msm_dp_aux); +irqreturn_t msm_dp_aux_isr(struct drm_dp_aux *msm_dp_aux, u32 isr); void msm_dp_aux_enable_xfers(struct drm_dp_aux *msm_dp_aux, bool enabled); void msm_dp_aux_init(struct drm_dp_aux *msm_dp_aux); void msm_dp_aux_deinit(struct drm_dp_aux *msm_dp_aux); diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/d= p_catalog.c index 9d6d59264a592cc3ae312b35e51d48c11bd141e6..84adf3a38e4cf0619b15850c314= 16f1e67049a42 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -15,41 +15,6 @@ #include "dp_catalog.h" #include "dp_reg.h" =20 -#define POLLING_SLEEP_US 1000 -#define POLLING_TIMEOUT_US 10000 - -#define DP_INTERRUPT_STATUS_ACK_SHIFT 1 -#define DP_INTERRUPT_STATUS_MASK_SHIFT 2 - -#define DP_INTERRUPT_STATUS1 \ - (DP_INTR_AUX_XFER_DONE| \ - DP_INTR_WRONG_ADDR | DP_INTR_TIMEOUT | \ - DP_INTR_NACK_DEFER | DP_INTR_WRONG_DATA_CNT | \ - DP_INTR_I2C_NACK | DP_INTR_I2C_DEFER | \ - DP_INTR_PLL_UNLOCKED | DP_INTR_AUX_ERROR) - -#define DP_INTERRUPT_STATUS1_ACK \ - (DP_INTERRUPT_STATUS1 << DP_INTERRUPT_STATUS_ACK_SHIFT) -#define DP_INTERRUPT_STATUS1_MASK \ - (DP_INTERRUPT_STATUS1 << DP_INTERRUPT_STATUS_MASK_SHIFT) - -#define DP_INTERRUPT_STATUS2 \ - (DP_INTR_READY_FOR_VIDEO | DP_INTR_IDLE_PATTERN_SENT | \ - DP_INTR_FRAME_END | DP_INTR_CRC_UPDATED) - -#define DP_INTERRUPT_STATUS2_ACK \ - (DP_INTERRUPT_STATUS2 << DP_INTERRUPT_STATUS_ACK_SHIFT) -#define DP_INTERRUPT_STATUS2_MASK \ - (DP_INTERRUPT_STATUS2 << DP_INTERRUPT_STATUS_MASK_SHIFT) - -#define DP_INTERRUPT_STATUS4 \ - (PSR_UPDATE_INT | PSR_CAPTURE_INT | PSR_EXIT_INT | \ - PSR_UPDATE_ERROR_INT | PSR_WAKE_ERROR_INT) - -#define DP_INTERRUPT_MASK4 \ - (PSR_UPDATE_MASK | PSR_CAPTURE_MASK | PSR_EXIT_MASK | \ - PSR_UPDATE_ERROR_MASK | PSR_WAKE_ERROR_MASK) - #define DP_DEFAULT_AHB_OFFSET 0x0000 #define DP_DEFAULT_AHB_SIZE 0x0200 #define DP_DEFAULT_AUX_OFFSET 0x0200 @@ -77,66 +42,6 @@ void msm_dp_catalog_snapshot(struct msm_dp_catalog *msm_= dp_catalog, struct msm_d msm_dp_catalog->p0_len, msm_dp_catalog->p0_base, "dp_p0"); } =20 -u32 msm_dp_catalog_aux_get_irq(struct msm_dp_catalog *msm_dp_catalog) -{ - u32 intr, intr_ack; - - intr =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_INTR_STATUS); - intr &=3D ~DP_INTERRUPT_STATUS1_MASK; - intr_ack =3D (intr & DP_INTERRUPT_STATUS1) - << DP_INTERRUPT_STATUS_ACK_SHIFT; - msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, - intr_ack | DP_INTERRUPT_STATUS1_MASK); - - return intr; - -} - -void msm_dp_catalog_ctrl_enable_irq(struct msm_dp_catalog *msm_dp_catalog, - bool enable) -{ - if (enable) { - msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, - DP_INTERRUPT_STATUS1_MASK); - msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2, - DP_INTERRUPT_STATUS2_MASK); - } else { - msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, 0x00); - msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2, 0x00); - } -} - -u32 msm_dp_catalog_ctrl_read_psr_interrupt_status(struct msm_dp_catalog *m= sm_dp_catalog) -{ - u32 intr, intr_ack; - - intr =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_INTR_STATUS4); - intr_ack =3D (intr & DP_INTERRUPT_STATUS4) - << DP_INTERRUPT_STATUS_ACK_SHIFT; - msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS4, intr_ack); - - return intr; -} - -void msm_dp_catalog_ctrl_config_psr_interrupt(struct msm_dp_catalog *msm_d= p_catalog) -{ - msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4); -} - -int msm_dp_catalog_ctrl_get_interrupt(struct msm_dp_catalog *msm_dp_catalo= g) -{ - u32 intr, intr_ack; - - intr =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2); - intr &=3D ~DP_INTERRUPT_STATUS2_MASK; - intr_ack =3D (intr & DP_INTERRUPT_STATUS2) - << DP_INTERRUPT_STATUS_ACK_SHIFT; - msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2, - intr_ack | DP_INTERRUPT_STATUS2_MASK); - - return intr; -} - static void __iomem *msm_dp_ioremap(struct platform_device *pdev, int idx,= size_t *len) { struct resource *res; diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/d= p_catalog.h index 5196188059f3ade2b6cc260ee65a7efb38844664..ddbae0fcf5fc428b2d37cd1eab1= d5860a2f11a50 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -11,23 +11,6 @@ #include "dp_utils.h" #include "disp/msm_disp_snapshot.h" =20 -/* interrupts */ -#define DP_INTR_HPD BIT(0) -#define DP_INTR_AUX_XFER_DONE BIT(3) -#define DP_INTR_WRONG_ADDR BIT(6) -#define DP_INTR_TIMEOUT BIT(9) -#define DP_INTR_NACK_DEFER BIT(12) -#define DP_INTR_WRONG_DATA_CNT BIT(15) -#define DP_INTR_I2C_NACK BIT(18) -#define DP_INTR_I2C_DEFER BIT(21) -#define DP_INTR_PLL_UNLOCKED BIT(24) -#define DP_INTR_AUX_ERROR BIT(27) - -#define DP_INTR_READY_FOR_VIDEO BIT(0) -#define DP_INTR_IDLE_PATTERN_SENT BIT(3) -#define DP_INTR_FRAME_END BIT(6) -#define DP_INTR_CRC_UPDATED BIT(9) - #define DP_HW_VERSION_1_0 0x10000000 #define DP_HW_VERSION_1_2 0x10020000 =20 @@ -112,15 +95,6 @@ static inline void msm_dp_write_link(struct msm_dp_cata= log *msm_dp_catalog, /* Debug module */ void msm_dp_catalog_snapshot(struct msm_dp_catalog *msm_dp_catalog, struct= msm_disp_state *disp_state); =20 -/* AUX APIs */ -u32 msm_dp_catalog_aux_get_irq(struct msm_dp_catalog *msm_dp_catalog); - -/* DP Controller APIs */ -void msm_dp_catalog_ctrl_enable_irq(struct msm_dp_catalog *msm_dp_catalog,= bool enable); -int msm_dp_catalog_ctrl_get_interrupt(struct msm_dp_catalog *msm_dp_catalo= g); -void msm_dp_catalog_ctrl_config_psr_interrupt(struct msm_dp_catalog *msm_d= p_catalog); -u32 msm_dp_catalog_ctrl_read_psr_interrupt_status(struct msm_dp_catalog *m= sm_dp_catalog); - struct msm_dp_catalog *msm_dp_catalog_get(struct device *dev); =20 #endif /* _DP_CATALOG_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 97a5f854f8344962c36e67d1cca480c1d5a3ef00..82ed6da67b44e56015efe6ceb60= 38c79c16a9fa8 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -31,6 +31,38 @@ #define PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES (300 * HZ / 1000) /= * 300 ms */ #define WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES (HZ / 2) =20 +#define DP_INTERRUPT_STATUS_ACK_SHIFT 1 +#define DP_INTERRUPT_STATUS_MASK_SHIFT 2 + +#define DP_INTERRUPT_STATUS1 \ + (DP_INTR_AUX_XFER_DONE| \ + DP_INTR_WRONG_ADDR | DP_INTR_TIMEOUT | \ + DP_INTR_NACK_DEFER | DP_INTR_WRONG_DATA_CNT | \ + DP_INTR_I2C_NACK | DP_INTR_I2C_DEFER | \ + DP_INTR_PLL_UNLOCKED | DP_INTR_AUX_ERROR) + +#define DP_INTERRUPT_STATUS1_ACK \ + (DP_INTERRUPT_STATUS1 << DP_INTERRUPT_STATUS_ACK_SHIFT) +#define DP_INTERRUPT_STATUS1_MASK \ + (DP_INTERRUPT_STATUS1 << DP_INTERRUPT_STATUS_MASK_SHIFT) + +#define DP_INTERRUPT_STATUS2 \ + (DP_INTR_READY_FOR_VIDEO | DP_INTR_IDLE_PATTERN_SENT | \ + DP_INTR_FRAME_END | DP_INTR_CRC_UPDATED) + +#define DP_INTERRUPT_STATUS2_ACK \ + (DP_INTERRUPT_STATUS2 << DP_INTERRUPT_STATUS_ACK_SHIFT) +#define DP_INTERRUPT_STATUS2_MASK \ + (DP_INTERRUPT_STATUS2 << DP_INTERRUPT_STATUS_MASK_SHIFT) + +#define DP_INTERRUPT_STATUS4 \ + (PSR_UPDATE_INT | PSR_CAPTURE_INT | PSR_EXIT_INT | \ + PSR_UPDATE_ERROR_INT | PSR_WAKE_ERROR_INT) + +#define DP_INTERRUPT_MASK4 \ + (PSR_UPDATE_MASK | PSR_CAPTURE_MASK | PSR_EXIT_MASK | \ + PSR_UPDATE_ERROR_MASK | PSR_WAKE_ERROR_MASK) + #define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0) #define DP_CTRL_INTR_IDLE_PATTERN_SENT BIT(3) =20 @@ -129,8 +161,10 @@ static int msm_dp_aux_link_configure(struct drm_dp_aux= *aux, /* * NOTE: resetting DP controller will also clear any pending HPD related i= nterrupts */ -static void msm_dp_ctrl_reset(struct msm_dp_ctrl_private *ctrl) +void msm_dp_ctrl_reset(struct msm_dp_ctrl *msm_dp_ctrl) { + struct msm_dp_ctrl_private *ctrl =3D + container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; u32 sw_reset; =20 @@ -149,6 +183,79 @@ static void msm_dp_ctrl_reset(struct msm_dp_ctrl_priva= te *ctrl) } } =20 +static u32 msm_dp_ctrl_get_aux_interrupt(struct msm_dp_ctrl_private *ctrl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 intr, intr_ack; + + intr =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_INTR_STATUS); + intr &=3D ~DP_INTERRUPT_STATUS1_MASK; + intr_ack =3D (intr & DP_INTERRUPT_STATUS1) + << DP_INTERRUPT_STATUS_ACK_SHIFT; + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, + intr_ack | DP_INTERRUPT_STATUS1_MASK); + + return intr; + +} + +static u32 msm_dp_ctrl_get_interrupt(struct msm_dp_ctrl_private *ctrl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 intr, intr_ack; + + intr =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2); + intr &=3D ~DP_INTERRUPT_STATUS2_MASK; + intr_ack =3D (intr & DP_INTERRUPT_STATUS2) + << DP_INTERRUPT_STATUS_ACK_SHIFT; + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2, + intr_ack | DP_INTERRUPT_STATUS2_MASK); + + return intr; +} + +void msm_dp_ctrl_enable_irq(struct msm_dp_ctrl *msm_dp_ctrl) +{ + struct msm_dp_ctrl_private *ctrl =3D + container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, + DP_INTERRUPT_STATUS1_MASK); + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2, + DP_INTERRUPT_STATUS2_MASK); +} + +void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_ctrl) +{ + struct msm_dp_ctrl_private *ctrl =3D + container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, 0x00); + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2, 0x00); +} + +static u32 msm_dp_ctrl_get_psr_interrupt(struct msm_dp_ctrl_private *ctrl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 intr, intr_ack; + + intr =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_INTR_STATUS4); + intr_ack =3D (intr & DP_INTERRUPT_STATUS4) + << DP_INTERRUPT_STATUS_ACK_SHIFT; + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS4, intr_ack); + + return intr; +} + +static void msm_dp_ctrl_config_psr_interrupt(struct msm_dp_ctrl_private *c= trl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4); +} + static void msm_dp_ctrl_psr_mainlink_enable(struct msm_dp_ctrl_private *ct= rl) { struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; @@ -1674,23 +1781,6 @@ static int msm_dp_ctrl_enable_mainlink_clocks(struct= msm_dp_ctrl_private *ctrl) return ret; } =20 -void msm_dp_ctrl_reset_irq_ctrl(struct msm_dp_ctrl *msm_dp_ctrl, bool enab= le) -{ - struct msm_dp_ctrl_private *ctrl; - - ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); - - msm_dp_ctrl_reset(ctrl); - - /* - * all dp controller programmable registers will not - * be reset to default value after DP_SW_RESET - * therefore interrupt mask bits have to be updated - * to enable/disable interrupts - */ - msm_dp_catalog_ctrl_enable_irq(ctrl->catalog, enable); -} - static void msm_dp_ctrl_enable_sdp(struct msm_dp_ctrl_private *ctrl) { struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; @@ -1743,7 +1833,7 @@ void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm_d= p_ctrl) cfg |=3D PSR1_SUPPORTED; msm_dp_write_link(msm_dp_catalog, REG_PSR_CONFIG, cfg); =20 - msm_dp_catalog_ctrl_config_psr_interrupt(msm_dp_catalog); + msm_dp_ctrl_config_psr_interrupt(ctrl); msm_dp_ctrl_enable_sdp(ctrl); =20 cfg =3D DP_PSR_ENABLE; @@ -1868,7 +1958,7 @@ static int msm_dp_ctrl_deinitialize_mainlink(struct m= sm_dp_ctrl_private *ctrl) =20 msm_dp_ctrl_mainlink_disable(ctrl); =20 - msm_dp_ctrl_reset(ctrl); + msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl); =20 dev_pm_opp_set_rate(ctrl->dev, 0); msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); @@ -2499,7 +2589,7 @@ void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl) =20 msm_dp_ctrl_mainlink_disable(ctrl); =20 - msm_dp_ctrl_reset(ctrl); + msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl); =20 if (ctrl->stream_clks_on) { clk_disable_unprepare(ctrl->pixel_clk); @@ -2526,7 +2616,7 @@ irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_d= p_ctrl) ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); =20 if (ctrl->panel->psr_cap.version) { - isr =3D msm_dp_catalog_ctrl_read_psr_interrupt_status(ctrl->catalog); + isr =3D msm_dp_ctrl_get_psr_interrupt(ctrl); =20 if (isr) complete(&ctrl->psr_op_comp); @@ -2541,8 +2631,7 @@ irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_d= p_ctrl) drm_dbg_dp(ctrl->drm_dev, "PSR frame capture done\n"); } =20 - isr =3D msm_dp_catalog_ctrl_get_interrupt(ctrl->catalog); - + isr =3D msm_dp_ctrl_get_interrupt(ctrl); =20 if (isr & DP_CTRL_INTR_READY_FOR_VIDEO) { drm_dbg_dp(ctrl->drm_dev, "dp_video_ready\n"); @@ -2556,6 +2645,11 @@ irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_= dp_ctrl) ret =3D IRQ_HANDLED; } =20 + /* DP aux isr */ + isr =3D msm_dp_ctrl_get_aux_interrupt(ctrl); + if (isr) + ret |=3D msm_dp_aux_isr(ctrl->aux, isr); + return ret; } =20 diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index b7abfedbf5749c25877a0b8ba3af3d8ed4b23d67..10a4b7cf0335a584b4db67baca8= 82620d7bab74c 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -30,7 +30,7 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, s= truct msm_dp_link *link struct msm_dp_catalog *catalog, struct phy *phy); =20 -void msm_dp_ctrl_reset_irq_ctrl(struct msm_dp_ctrl *msm_dp_ctrl, bool enab= le); +void msm_dp_ctrl_reset(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_phy_init(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_phy_exit(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_irq_phy_exit(struct msm_dp_ctrl *msm_dp_ctrl); @@ -41,4 +41,7 @@ void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm_dp_ct= rl); int msm_dp_ctrl_core_clk_enable(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_core_clk_disable(struct msm_dp_ctrl *msm_dp_ctrl); =20 +void msm_dp_ctrl_enable_irq(struct msm_dp_ctrl *msm_dp_ctrl); +void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_ctrl); + #endif /* _DP_CTRL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 8b79eebe68cb40b7c640c559e8eda400ee1b5f0a..e0ce410c6b26e10c36fff530b6b= 07e537c7ed759 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -457,7 +457,8 @@ static void msm_dp_display_host_init(struct msm_dp_disp= lay_private *dp) dp->phy_initialized); =20 msm_dp_ctrl_core_clk_enable(dp->ctrl); - msm_dp_ctrl_reset_irq_ctrl(dp->ctrl, true); + msm_dp_ctrl_reset(dp->ctrl); + msm_dp_ctrl_enable_irq(dp->ctrl); msm_dp_aux_init(dp->aux); dp->core_initialized =3D true; } @@ -468,7 +469,8 @@ static void msm_dp_display_host_deinit(struct msm_dp_di= splay_private *dp) dp->msm_dp_display.connector_type, dp->core_initialized, dp->phy_initialized); =20 - msm_dp_ctrl_reset_irq_ctrl(dp->ctrl, false); + msm_dp_ctrl_reset(dp->ctrl); + msm_dp_ctrl_disable_irq(dp->ctrl); msm_dp_aux_deinit(dp->aux); msm_dp_ctrl_core_clk_disable(dp->ctrl); dp->core_initialized =3D false; @@ -1170,9 +1172,6 @@ static irqreturn_t msm_dp_display_irq_handler(int irq= , void *dev_id) /* DP controller isr */ ret |=3D msm_dp_ctrl_isr(dp->ctrl); =20 - /* DP aux isr */ - ret |=3D msm_dp_aux_isr(dp->aux); - return ret; } =20 diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_re= g.h index 3835c7f5cb984406f8fc52ea765ef2315e0d175b..d17e077ded73251624b5fb1bfbd= 8f213b4a86d65 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -21,8 +21,25 @@ =20 #define REG_DP_CLK_CTRL (0x00000018) #define REG_DP_CLK_ACTIVE (0x0000001C) + #define REG_DP_INTR_STATUS (0x00000020) +#define DP_INTR_HPD BIT(0) +#define DP_INTR_AUX_XFER_DONE BIT(3) +#define DP_INTR_WRONG_ADDR BIT(6) +#define DP_INTR_TIMEOUT BIT(9) +#define DP_INTR_NACK_DEFER BIT(12) +#define DP_INTR_WRONG_DATA_CNT BIT(15) +#define DP_INTR_I2C_NACK BIT(18) +#define DP_INTR_I2C_DEFER BIT(21) +#define DP_INTR_PLL_UNLOCKED BIT(24) +#define DP_INTR_AUX_ERROR BIT(27) + #define REG_DP_INTR_STATUS2 (0x00000024) +#define DP_INTR_READY_FOR_VIDEO BIT(0) +#define DP_INTR_IDLE_PATTERN_SENT BIT(3) +#define DP_INTR_FRAME_END BIT(6) +#define DP_INTR_CRC_UPDATED BIT(9) + #define REG_DP_INTR_STATUS3 (0x00000028) =20 #define REG_DP_INTR_STATUS4 (0x0000002C) --=20 2.39.5 From nobody Sun Dec 14 19:12:24 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4DD021ABC2 for ; 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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-328084ca34csm14186881fa.30.2025.05.18.04.21.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 May 2025 04:21:59 -0700 (PDT) From: Dmitry Baryshkov Date: Sun, 18 May 2025 14:21:44 +0300 Subject: [PATCH v6 11/11] drm/msm/dp: drop the msm_dp_catalog module Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250518-fd-dp-audio-fixup-v6-11-2f0ec3ec000d@oss.qualcomm.com> References: <20250518-fd-dp-audio-fixup-v6-0-2f0ec3ec000d@oss.qualcomm.com> In-Reply-To: <20250518-fd-dp-audio-fixup-v6-0-2f0ec3ec000d@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Paloma Arellano Cc: Douglas Anderson , Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=78946; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=0JkwTGZeVMyL24cSeJz+zAVwJTTJ0EXM2Y8tVgnWmZ8=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoKcLAgWA4r7syYL9WkFzlac7ts2o480VfkRvg8 p3XLbKV8m6JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaCnCwAAKCRCLPIo+Aiko 1TfBB/9iQhJE7sTKE2zpbMT+xBKMo9K1ntCc2NXXwLrYf//WPwX3UrJoVHTqtnf1uBFZRqpeOBQ lgM+mWYdnnF7BPDpiuHBZlb6xoF/8DfekOZSxVzBettiyM8I4iq3WNgM4pVJQ891WgFaz/DO61z 6bdVe9dBwhFuFrQ8a0cCmrIbJcv8mp7TaKWtu+TrIf6QIRU7KIpflHbYIPqVwctdUCyJ/2FV35R 7HC5Gti3S5v6o2FiyIZIfjrGn99IRaPJ0qxxbkg16BKLFriQgFcLCzI8Hd00m6d841dTE7u3IXc bzfgGaOlVRkGUf6gfBXBKJayWHlSLgHzOB3aXAB80JVfyvXO X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: k9AM1gLXcqwcP9gTA1wesCojLhxVQi04 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE4MDEwOCBTYWx0ZWRfXx5JDLJErU5Io ZGGcl462ulJuiH75aNSrZ3maDCMNZ++8P+9BNy3O7RVpD4PwKqeb4nGozlaIddbRchA3sd41Q+w SBQeq9k7bkzUVVe+GiqdFDxC8+3oNYJDoBwOjvFjrQorFhpNwfh4aXLjdGqA1C/0cg8WKBSJgOk 5ySEPd4WiynOoNWhdRUeoLr+dw5ca616x+gAKtauNjfccjpSi3IMKEFc0sa70EMgbZ1dQL8tMJt VvQTmeKIF86OrknsBi2SSrrJVRkZ4kn+m5jDxFob1wiN80RVQ8vGVP8onlEgK7NqDXtz4tOGhet +1Z5HIu0vu/6KpkrD7J6kWE8QxAen4uwzRx5ws2Tyc9XM9DGJJFjhmFJmpTKC82d6NWmEnsXxpK ag1GjaiNn0SuKfzMF2MF+DnLSPJ5fP5Fn9QZ/wkegzNc2G+w3V4hvGcZnyMQc+NXvaLVt8Mp X-Authority-Analysis: v=2.4 cv=H8Pbw/Yi c=1 sm=1 tr=0 ts=6829c2df cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=KKAkSRfTAAAA:8 a=cm27Pg_UAAAA:8 a=EUspDBNiAAAA:8 a=l76XXDAN4ChfmoQA3-8A:9 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: k9AM1gLXcqwcP9gTA1wesCojLhxVQi04 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-18_06,2025-05-16_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 mlxlogscore=999 adultscore=0 phishscore=0 mlxscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 impostorscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505180108 From: Dmitry Baryshkov Now as the msm_dp_catalog module became nearly empty, drop it, accessing registers directly from the corresponding submodules. Reviewed-by: Stephen Boyd Tested-by: Stephen Boyd # sc7180-trogdor Signed-off-by: Dmitry Baryshkov Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/Makefile | 1 - drivers/gpu/drm/msm/dp/dp_audio.c | 70 ++++++----- drivers/gpu/drm/msm/dp/dp_audio.h | 7 +- drivers/gpu/drm/msm/dp/dp_aux.c | 113 +++++++++--------- drivers/gpu/drm/msm/dp/dp_aux.h | 6 +- drivers/gpu/drm/msm/dp/dp_catalog.c | 126 -------------------- drivers/gpu/drm/msm/dp/dp_catalog.h | 100 ---------------- drivers/gpu/drm/msm/dp/dp_ctrl.c | 231 +++++++++++++++++++-------------= ---- drivers/gpu/drm/msm/dp/dp_ctrl.h | 12 +- drivers/gpu/drm/msm/dp/dp_debug.c | 1 - drivers/gpu/drm/msm/dp/dp_display.c | 123 +++++++++++++++---- drivers/gpu/drm/msm/dp/dp_link.c | 1 + drivers/gpu/drm/msm/dp/dp_panel.c | 157 ++++++++++++++---------- drivers/gpu/drm/msm/dp/dp_panel.h | 7 +- drivers/gpu/drm/msm/dp/dp_reg.h | 2 + 15 files changed, 435 insertions(+), 522 deletions(-) diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 7a2ada6e2d74a902879e4f12a78ed475e5209ec2..b6b6f2d0867d548e8d2c1be9fd9= 8a0f1ceadb111 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -135,7 +135,6 @@ msm-display-$(CONFIG_DEBUG_FS) +=3D \ dp/dp_debug.o =20 msm-display-$(CONFIG_DRM_MSM_DP)+=3D dp/dp_aux.o \ - dp/dp_catalog.o \ dp/dp_ctrl.o \ dp/dp_display.o \ dp/dp_drm.o \ diff --git a/drivers/gpu/drm/msm/dp/dp_audio.c b/drivers/gpu/drm/msm/dp/dp_= audio.c index 09f871a001073ae698708b31fa8030ec7cf20242..959cf53be4b8a90eb7cc87c80f5= 0f2b220b35762 100644 --- a/drivers/gpu/drm/msm/dp/dp_audio.c +++ b/drivers/gpu/drm/msm/dp/dp_audio.c @@ -11,7 +11,6 @@ #include #include =20 -#include "dp_catalog.h" #include "dp_audio.h" #include "dp_drm.h" #include "dp_panel.h" @@ -22,16 +21,30 @@ struct msm_dp_audio_private { struct platform_device *pdev; struct drm_device *drm_dev; - struct msm_dp_catalog *catalog; + void __iomem *link_base; =20 u32 channels; =20 struct msm_dp_audio msm_dp_audio; }; =20 +static inline u32 msm_dp_read_link(struct msm_dp_audio_private *audio, u32= offset) +{ + return readl_relaxed(audio->link_base + offset); +} + +static inline void msm_dp_write_link(struct msm_dp_audio_private *audio, + u32 offset, u32 data) +{ + /* + * To make sure link reg writes happens before any other operation, + * this function uses writel() instread of writel_relaxed() + */ + writel(data, audio->link_base + offset); +} + static void msm_dp_audio_stream_sdp(struct msm_dp_audio_private *audio) { - struct msm_dp_catalog *catalog =3D audio->catalog; struct dp_sdp_header sdp_hdr =3D { .HB0 =3D 0x00, .HB1 =3D 0x02, @@ -42,13 +55,12 @@ static void msm_dp_audio_stream_sdp(struct msm_dp_audio= _private *audio) =20 msm_dp_utils_pack_sdp_header(&sdp_hdr, header); =20 - msm_dp_write_link(catalog, MMSS_DP_AUDIO_STREAM_0, header[0]); - msm_dp_write_link(catalog, MMSS_DP_AUDIO_STREAM_1, header[1]); + msm_dp_write_link(audio, MMSS_DP_AUDIO_STREAM_0, header[0]); + msm_dp_write_link(audio, MMSS_DP_AUDIO_STREAM_1, header[1]); } =20 static void msm_dp_audio_timestamp_sdp(struct msm_dp_audio_private *audio) { - struct msm_dp_catalog *catalog =3D audio->catalog; struct dp_sdp_header sdp_hdr =3D { .HB0 =3D 0x00, .HB1 =3D 0x01, @@ -59,13 +71,12 @@ static void msm_dp_audio_timestamp_sdp(struct msm_dp_au= dio_private *audio) =20 msm_dp_utils_pack_sdp_header(&sdp_hdr, header); =20 - msm_dp_write_link(catalog, MMSS_DP_AUDIO_TIMESTAMP_0, header[0]); - msm_dp_write_link(catalog, MMSS_DP_AUDIO_TIMESTAMP_1, header[1]); + msm_dp_write_link(audio, MMSS_DP_AUDIO_TIMESTAMP_0, header[0]); + msm_dp_write_link(audio, MMSS_DP_AUDIO_TIMESTAMP_1, header[1]); } =20 static void msm_dp_audio_infoframe_sdp(struct msm_dp_audio_private *audio) { - struct msm_dp_catalog *catalog =3D audio->catalog; struct dp_sdp_header sdp_hdr =3D { .HB0 =3D 0x00, .HB1 =3D 0x84, @@ -76,13 +87,12 @@ static void msm_dp_audio_infoframe_sdp(struct msm_dp_au= dio_private *audio) =20 msm_dp_utils_pack_sdp_header(&sdp_hdr, header); =20 - msm_dp_write_link(catalog, MMSS_DP_AUDIO_INFOFRAME_0, header[0]); - msm_dp_write_link(catalog, MMSS_DP_AUDIO_INFOFRAME_1, header[1]); + msm_dp_write_link(audio, MMSS_DP_AUDIO_INFOFRAME_0, header[0]); + msm_dp_write_link(audio, MMSS_DP_AUDIO_INFOFRAME_1, header[1]); } =20 static void msm_dp_audio_copy_management_sdp(struct msm_dp_audio_private *= audio) { - struct msm_dp_catalog *catalog =3D audio->catalog; struct dp_sdp_header sdp_hdr =3D { .HB0 =3D 0x00, .HB1 =3D 0x05, @@ -93,13 +103,12 @@ static void msm_dp_audio_copy_management_sdp(struct ms= m_dp_audio_private *audio) =20 msm_dp_utils_pack_sdp_header(&sdp_hdr, header); =20 - msm_dp_write_link(catalog, MMSS_DP_AUDIO_COPYMANAGEMENT_0, header[0]); - msm_dp_write_link(catalog, MMSS_DP_AUDIO_COPYMANAGEMENT_1, header[1]); + msm_dp_write_link(audio, MMSS_DP_AUDIO_COPYMANAGEMENT_0, header[0]); + msm_dp_write_link(audio, MMSS_DP_AUDIO_COPYMANAGEMENT_1, header[1]); } =20 static void msm_dp_audio_isrc_sdp(struct msm_dp_audio_private *audio) { - struct msm_dp_catalog *catalog =3D audio->catalog; struct dp_sdp_header sdp_hdr =3D { .HB0 =3D 0x00, .HB1 =3D 0x06, @@ -110,21 +119,20 @@ static void msm_dp_audio_isrc_sdp(struct msm_dp_audio= _private *audio) u32 reg; =20 /* XXX: is it necessary to preserve this field? */ - reg =3D msm_dp_read_link(catalog, MMSS_DP_AUDIO_ISRC_1); + reg =3D msm_dp_read_link(audio, MMSS_DP_AUDIO_ISRC_1); sdp_hdr.HB3 =3D FIELD_GET(HEADER_3_MASK, reg); =20 msm_dp_utils_pack_sdp_header(&sdp_hdr, header); =20 - msm_dp_write_link(catalog, MMSS_DP_AUDIO_ISRC_0, header[0]); - msm_dp_write_link(catalog, MMSS_DP_AUDIO_ISRC_1, header[1]); + msm_dp_write_link(audio, MMSS_DP_AUDIO_ISRC_0, header[0]); + msm_dp_write_link(audio, MMSS_DP_AUDIO_ISRC_1, header[1]); } =20 static void msm_dp_audio_config_sdp(struct msm_dp_audio_private *audio) { - struct msm_dp_catalog *msm_dp_catalog =3D audio->catalog; u32 sdp_cfg, sdp_cfg2; =20 - sdp_cfg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG); + sdp_cfg =3D msm_dp_read_link(audio, MMSS_DP_SDP_CFG); /* AUDIO_TIMESTAMP_SDP_EN */ sdp_cfg |=3D BIT(1); /* AUDIO_STREAM_SDP_EN */ @@ -138,9 +146,9 @@ static void msm_dp_audio_config_sdp(struct msm_dp_audio= _private *audio) =20 drm_dbg_dp(audio->drm_dev, "sdp_cfg =3D 0x%x\n", sdp_cfg); =20 - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, sdp_cfg); + msm_dp_write_link(audio, MMSS_DP_SDP_CFG, sdp_cfg); =20 - sdp_cfg2 =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2); + sdp_cfg2 =3D msm_dp_read_link(audio, MMSS_DP_SDP_CFG2); /* IFRM_REGSRC -> Do not use reg values */ sdp_cfg2 &=3D ~BIT(0); /* AUDIO_STREAM_HB3_REGSRC-> Do not use reg values */ @@ -148,7 +156,7 @@ static void msm_dp_audio_config_sdp(struct msm_dp_audio= _private *audio) =20 drm_dbg_dp(audio->drm_dev, "sdp_cfg2 =3D 0x%x\n", sdp_cfg2); =20 - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, sdp_cfg2); + msm_dp_write_link(audio, MMSS_DP_SDP_CFG2, sdp_cfg2); } =20 static void msm_dp_audio_setup_sdp(struct msm_dp_audio_private *audio) @@ -190,7 +198,7 @@ static void msm_dp_audio_setup_acr(struct msm_dp_audio_= private *audio) drm_dbg_dp(audio->drm_dev, "select: %#x, acr_ctrl: %#x\n", select, acr_ctrl); =20 - msm_dp_write_link(audio->catalog, MMSS_DP_AUDIO_ACR_CTRL, acr_ctrl); + msm_dp_write_link(audio, MMSS_DP_AUDIO_ACR_CTRL, acr_ctrl); } =20 static void msm_dp_audio_safe_to_exit_level(struct msm_dp_audio_private *a= udio) @@ -215,7 +223,7 @@ static void msm_dp_audio_safe_to_exit_level(struct msm_= dp_audio_private *audio) break; } =20 - mainlink_levels =3D msm_dp_read_link(audio->catalog, REG_DP_MAINLINK_LEVE= LS); + mainlink_levels =3D msm_dp_read_link(audio, REG_DP_MAINLINK_LEVELS); mainlink_levels &=3D 0xFE0; mainlink_levels |=3D safe_to_exit_level; =20 @@ -223,14 +231,14 @@ static void msm_dp_audio_safe_to_exit_level(struct ms= m_dp_audio_private *audio) "mainlink_level =3D 0x%x, safe_to_exit_level =3D 0x%x\n", mainlink_levels, safe_to_exit_level); =20 - msm_dp_write_link(audio->catalog, REG_DP_MAINLINK_LEVELS, mainlink_levels= ); + msm_dp_write_link(audio, REG_DP_MAINLINK_LEVELS, mainlink_levels); } =20 static void msm_dp_audio_enable(struct msm_dp_audio_private *audio, bool e= nable) { u32 audio_ctrl; =20 - audio_ctrl =3D msm_dp_read_link(audio->catalog, MMSS_DP_AUDIO_CFG); + audio_ctrl =3D msm_dp_read_link(audio, MMSS_DP_AUDIO_CFG); =20 if (enable) audio_ctrl |=3D BIT(0); @@ -239,7 +247,7 @@ static void msm_dp_audio_enable(struct msm_dp_audio_pri= vate *audio, bool enable) =20 drm_dbg_dp(audio->drm_dev, "dp_audio_cfg =3D 0x%x\n", audio_ctrl); =20 - msm_dp_write_link(audio->catalog, MMSS_DP_AUDIO_CFG, audio_ctrl); + msm_dp_write_link(audio, MMSS_DP_AUDIO_CFG, audio_ctrl); /* make sure audio engine is disabled */ wmb(); } @@ -330,13 +338,13 @@ void msm_dp_audio_shutdown(struct drm_connector *conn= ector, } =20 struct msm_dp_audio *msm_dp_audio_get(struct platform_device *pdev, - struct msm_dp_catalog *catalog) + void __iomem *link_base) { int rc =3D 0; struct msm_dp_audio_private *audio; struct msm_dp_audio *msm_dp_audio; =20 - if (!pdev || !catalog) { + if (!pdev) { DRM_ERROR("invalid input\n"); rc =3D -EINVAL; goto error; @@ -349,7 +357,7 @@ struct msm_dp_audio *msm_dp_audio_get(struct platform_d= evice *pdev, } =20 audio->pdev =3D pdev; - audio->catalog =3D catalog; + audio->link_base =3D link_base; =20 msm_dp_audio =3D &audio->msm_dp_audio; =20 diff --git a/drivers/gpu/drm/msm/dp/dp_audio.h b/drivers/gpu/drm/msm/dp/dp_= audio.h index 58fc14693e48bff2b57ef7278983e5f21ee80ac7..842278516c9955ea8cf59d715b0= f55963cfefbff 100644 --- a/drivers/gpu/drm/msm/dp/dp_audio.h +++ b/drivers/gpu/drm/msm/dp/dp_audio.h @@ -8,9 +8,10 @@ =20 #include =20 -#include "dp_catalog.h" #include =20 +struct drm_bridge; + /** * struct msm_dp_audio * @lane_count: number of lanes configured in current session @@ -27,13 +28,13 @@ struct msm_dp_audio { * Creates and instance of dp audio. * * @pdev: caller's platform device instance. - * @catalog: an instance of msm_dp_catalog module. + * @link_base: pointer to the msm_dp_link resource. * * Returns the error code in case of failure, otherwize * an instance of newly created msm_dp_module. */ struct msm_dp_audio *msm_dp_audio_get(struct platform_device *pdev, - struct msm_dp_catalog *catalog); + void __iomem *link_base); =20 /** * msm_dp_audio_put() diff --git a/drivers/gpu/drm/msm/dp/dp_aux.c b/drivers/gpu/drm/msm/dp/dp_au= x.c index d7a38fa5d64d618af463416edf13bef79d6b53ba..3825a2fb48e213862f5755a8e53= 269e09053dc29 100644 --- a/drivers/gpu/drm/msm/dp/dp_aux.c +++ b/drivers/gpu/drm/msm/dp/dp_aux.c @@ -23,7 +23,7 @@ enum msm_dp_aux_err { =20 struct msm_dp_aux_private { struct device *dev; - struct msm_dp_catalog *catalog; + void __iomem *aux_base; =20 struct phy *phy; =20 @@ -46,14 +46,27 @@ struct msm_dp_aux_private { struct drm_dp_aux msm_dp_aux; }; =20 -static void msm_dp_aux_clear_hw_interrupts(struct msm_dp_aux_private *aux) +static inline u32 msm_dp_read_aux(struct msm_dp_aux_private *aux, u32 offs= et) +{ + return readl_relaxed(aux->aux_base + offset); +} + +static inline void msm_dp_write_aux(struct msm_dp_aux_private *aux, + u32 offset, u32 data) { - struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; + /* + * To make sure aux reg writes happens before any other operation, + * this function uses writel() instread of writel_relaxed() + */ + writel(data, aux->aux_base + offset); +} =20 - msm_dp_read_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_STATUS); - msm_dp_write_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x1f); - msm_dp_write_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x9f); - msm_dp_write_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0); +static void msm_dp_aux_clear_hw_interrupts(struct msm_dp_aux_private *aux) +{ + msm_dp_read_aux(aux, REG_DP_PHY_AUX_INTERRUPT_STATUS); + msm_dp_write_aux(aux, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x1f); + msm_dp_write_aux(aux, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x9f); + msm_dp_write_aux(aux, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0); } =20 /* @@ -61,51 +74,47 @@ static void msm_dp_aux_clear_hw_interrupts(struct msm_d= p_aux_private *aux) */ static void msm_dp_aux_reset(struct msm_dp_aux_private *aux) { - struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; u32 aux_ctrl; =20 - aux_ctrl =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_AUX_CTRL); + aux_ctrl =3D msm_dp_read_aux(aux, REG_DP_AUX_CTRL); =20 aux_ctrl |=3D DP_AUX_CTRL_RESET; - msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_CTRL, aux_ctrl); + msm_dp_write_aux(aux, REG_DP_AUX_CTRL, aux_ctrl); usleep_range(1000, 1100); /* h/w recommended delay */ =20 aux_ctrl &=3D ~DP_AUX_CTRL_RESET; - msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_CTRL, aux_ctrl); + msm_dp_write_aux(aux, REG_DP_AUX_CTRL, aux_ctrl); } =20 static void msm_dp_aux_enable(struct msm_dp_aux_private *aux) { - struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; u32 aux_ctrl; =20 - aux_ctrl =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_AUX_CTRL); + aux_ctrl =3D msm_dp_read_aux(aux, REG_DP_AUX_CTRL); =20 - msm_dp_write_aux(msm_dp_catalog, REG_DP_TIMEOUT_COUNT, 0xffff); - msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_LIMITS, 0xffff); + msm_dp_write_aux(aux, REG_DP_TIMEOUT_COUNT, 0xffff); + msm_dp_write_aux(aux, REG_DP_AUX_LIMITS, 0xffff); =20 aux_ctrl |=3D DP_AUX_CTRL_ENABLE; - msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_CTRL, aux_ctrl); + msm_dp_write_aux(aux, REG_DP_AUX_CTRL, aux_ctrl); } =20 static void msm_dp_aux_disable(struct msm_dp_aux_private *aux) { - struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; u32 aux_ctrl; =20 - aux_ctrl =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_AUX_CTRL); + aux_ctrl =3D msm_dp_read_aux(aux, REG_DP_AUX_CTRL); aux_ctrl &=3D ~DP_AUX_CTRL_ENABLE; - msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_CTRL, aux_ctrl); + msm_dp_write_aux(aux, REG_DP_AUX_CTRL, aux_ctrl); } =20 static int msm_dp_aux_wait_for_hpd_connect_state(struct msm_dp_aux_private= *aux, unsigned long wait_us) { - struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; u32 state; =20 /* poll for hpd connected status every 2ms and timeout after wait_us */ - return readl_poll_timeout(msm_dp_catalog->aux_base + + return readl_poll_timeout(aux->aux_base + REG_DP_DP_HPD_INT_STATUS, state, state & DP_DP_HPD_STATE_STATUS_CONNECTED, min(wait_us, 2000), wait_us); @@ -154,10 +163,10 @@ static ssize_t msm_dp_aux_write(struct msm_dp_aux_pri= vate *aux, /* index =3D 0, write */ if (i =3D=3D 0) reg |=3D DP_AUX_DATA_INDEX_WRITE; - msm_dp_write_aux(aux->catalog, REG_DP_AUX_DATA, reg); + msm_dp_write_aux(aux, REG_DP_AUX_DATA, reg); } =20 - msm_dp_write_aux(aux->catalog, REG_DP_AUX_TRANS_CTRL, 0); + msm_dp_write_aux(aux, REG_DP_AUX_TRANS_CTRL, 0); msm_dp_aux_clear_hw_interrupts(aux); =20 reg =3D 0; /* Transaction number =3D=3D 1 */ @@ -172,7 +181,7 @@ static ssize_t msm_dp_aux_write(struct msm_dp_aux_priva= te *aux, } =20 reg |=3D DP_AUX_TRANS_CTRL_GO; - msm_dp_write_aux(aux->catalog, REG_DP_AUX_TRANS_CTRL, reg); + msm_dp_write_aux(aux, REG_DP_AUX_TRANS_CTRL, reg); =20 return len; } @@ -205,22 +214,22 @@ static ssize_t msm_dp_aux_cmd_fifo_rx(struct msm_dp_a= ux_private *aux, u32 i, actual_i; u32 len =3D msg->size; =20 - data =3D msm_dp_read_aux(aux->catalog, REG_DP_AUX_TRANS_CTRL); + data =3D msm_dp_read_aux(aux, REG_DP_AUX_TRANS_CTRL); data &=3D ~DP_AUX_TRANS_CTRL_GO; - msm_dp_write_aux(aux->catalog, REG_DP_AUX_TRANS_CTRL, data); + msm_dp_write_aux(aux, REG_DP_AUX_TRANS_CTRL, data); =20 data =3D DP_AUX_DATA_INDEX_WRITE; /* INDEX_WRITE */ data |=3D DP_AUX_DATA_READ; /* read */ =20 - msm_dp_write_aux(aux->catalog, REG_DP_AUX_DATA, data); + msm_dp_write_aux(aux, REG_DP_AUX_DATA, data); =20 dp =3D msg->buffer; =20 /* discard first byte */ - data =3D msm_dp_read_aux(aux->catalog, REG_DP_AUX_DATA); + data =3D msm_dp_read_aux(aux, REG_DP_AUX_DATA); =20 for (i =3D 0; i < len; i++) { - data =3D msm_dp_read_aux(aux->catalog, REG_DP_AUX_DATA); + data =3D msm_dp_read_aux(aux, REG_DP_AUX_DATA); *dp++ =3D (u8)((data >> DP_AUX_DATA_OFFSET) & 0xff); =20 actual_i =3D (data >> DP_AUX_DATA_INDEX_OFFSET) & 0xFF; @@ -588,42 +597,39 @@ void msm_dp_aux_hpd_enable(struct drm_dp_aux *msm_dp_= aux) { struct msm_dp_aux_private *aux =3D container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); - struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; u32 reg; =20 /* Configure REFTIMER and enable it */ - reg =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER); + reg =3D msm_dp_read_aux(aux, REG_DP_DP_HPD_REFTIMER); reg |=3D DP_DP_HPD_REFTIMER_ENABLE; - msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER, reg); + msm_dp_write_aux(aux, REG_DP_DP_HPD_REFTIMER, reg); =20 /* Enable HPD */ - msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_E= N); + msm_dp_write_aux(aux, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_EN); } =20 void msm_dp_aux_hpd_disable(struct drm_dp_aux *msm_dp_aux) { struct msm_dp_aux_private *aux =3D container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); - struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; u32 reg; =20 - reg =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER); + reg =3D msm_dp_read_aux(aux, REG_DP_DP_HPD_REFTIMER); reg &=3D ~DP_DP_HPD_REFTIMER_ENABLE; - msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER, reg); + msm_dp_write_aux(aux, REG_DP_DP_HPD_REFTIMER, reg); =20 - msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_CTRL, 0); + msm_dp_write_aux(aux, REG_DP_DP_HPD_CTRL, 0); } =20 void msm_dp_aux_hpd_intr_enable(struct drm_dp_aux *msm_dp_aux) { struct msm_dp_aux_private *aux =3D container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); - struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; u32 reg; =20 - reg =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK); + reg =3D msm_dp_read_aux(aux, REG_DP_DP_HPD_INT_MASK); reg |=3D DP_DP_HPD_INT_MASK; - msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK, + msm_dp_write_aux(aux, REG_DP_DP_HPD_INT_MASK, reg & DP_DP_HPD_INT_MASK); } =20 @@ -631,12 +637,11 @@ void msm_dp_aux_hpd_intr_disable(struct drm_dp_aux *m= sm_dp_aux) { struct msm_dp_aux_private *aux =3D container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); - struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; u32 reg; =20 - reg =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK); + reg =3D msm_dp_read_aux(aux, REG_DP_DP_HPD_INT_MASK); reg &=3D ~DP_DP_HPD_INT_MASK; - msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK, + msm_dp_write_aux(aux, REG_DP_DP_HPD_INT_MASK, reg & DP_DP_HPD_INT_MASK); } =20 @@ -644,13 +649,12 @@ u32 msm_dp_aux_get_hpd_intr_status(struct drm_dp_aux = *msm_dp_aux) { struct msm_dp_aux_private *aux =3D container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); - struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; int isr, mask; =20 - isr =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_STATUS); - msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_ACK, + isr =3D msm_dp_read_aux(aux, REG_DP_DP_HPD_INT_STATUS); + msm_dp_write_aux(aux, REG_DP_DP_HPD_INT_ACK, (isr & DP_DP_HPD_INT_MASK)); - mask =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK); + mask =3D msm_dp_read_aux(aux, REG_DP_DP_HPD_INT_MASK); =20 /* * We only want to return interrupts that are unmasked to the caller. @@ -666,27 +670,22 @@ u32 msm_dp_aux_is_link_connected(struct drm_dp_aux *m= sm_dp_aux) { struct msm_dp_aux_private *aux =3D container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); - struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; u32 status; =20 - status =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_STATUS); + status =3D msm_dp_read_aux(aux, REG_DP_DP_HPD_INT_STATUS); status >>=3D DP_DP_HPD_STATE_STATUS_BITS_SHIFT; status &=3D DP_DP_HPD_STATE_STATUS_BITS_MASK; =20 return status; } =20 -struct drm_dp_aux *msm_dp_aux_get(struct device *dev, struct msm_dp_catalo= g *catalog, +struct drm_dp_aux *msm_dp_aux_get(struct device *dev, struct phy *phy, - bool is_edp) + bool is_edp, + void __iomem *aux_base) { struct msm_dp_aux_private *aux; =20 - if (!catalog) { - DRM_ERROR("invalid input\n"); - return ERR_PTR(-ENODEV); - } - aux =3D devm_kzalloc(dev, sizeof(*aux), GFP_KERNEL); if (!aux) return ERR_PTR(-ENOMEM); @@ -697,9 +696,9 @@ struct drm_dp_aux *msm_dp_aux_get(struct device *dev, s= truct msm_dp_catalog *cat mutex_init(&aux->mutex); =20 aux->dev =3D dev; - aux->catalog =3D catalog; aux->phy =3D phy; aux->retry_cnt =3D 0; + aux->aux_base =3D aux_base; =20 /* * Use the drm_dp_aux_init() to use the aux adapter diff --git a/drivers/gpu/drm/msm/dp/dp_aux.h b/drivers/gpu/drm/msm/dp/dp_au= x.h index 83908c93b6a1baa6c4eb83a346b4498704008ca5..4be02e8b4d0baec8e8c14e5325c= 44f446204f4f5 100644 --- a/drivers/gpu/drm/msm/dp/dp_aux.h +++ b/drivers/gpu/drm/msm/dp/dp_aux.h @@ -6,7 +6,6 @@ #ifndef _DP_AUX_H_ #define _DP_AUX_H_ =20 -#include "dp_catalog.h" #include =20 int msm_dp_aux_register(struct drm_dp_aux *msm_dp_aux); @@ -25,9 +24,10 @@ u32 msm_dp_aux_get_hpd_intr_status(struct drm_dp_aux *ms= m_dp_aux); u32 msm_dp_aux_is_link_connected(struct drm_dp_aux *msm_dp_aux); =20 struct phy; -struct drm_dp_aux *msm_dp_aux_get(struct device *dev, struct msm_dp_catalo= g *catalog, +struct drm_dp_aux *msm_dp_aux_get(struct device *dev, struct phy *phy, - bool is_edp); + bool is_edp, + void __iomem *aux_base); void msm_dp_aux_put(struct drm_dp_aux *aux); =20 #endif /*__DP_AUX_H_*/ diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/d= p_catalog.c deleted file mode 100644 index 84adf3a38e4cf0619b15850c31416f1e67049a42..000000000000000000000000000= 0000000000000 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ /dev/null @@ -1,126 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. - */ - -#define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__ - -#include -#include -#include -#include -#include -#include - -#include "dp_catalog.h" -#include "dp_reg.h" - -#define DP_DEFAULT_AHB_OFFSET 0x0000 -#define DP_DEFAULT_AHB_SIZE 0x0200 -#define DP_DEFAULT_AUX_OFFSET 0x0200 -#define DP_DEFAULT_AUX_SIZE 0x0200 -#define DP_DEFAULT_LINK_OFFSET 0x0400 -#define DP_DEFAULT_LINK_SIZE 0x0C00 -#define DP_DEFAULT_P0_OFFSET 0x1000 -#define DP_DEFAULT_P0_SIZE 0x0400 - -struct msm_dp_catalog_private { - struct device *dev; - struct drm_device *drm_dev; - struct msm_dp_catalog msm_dp_catalog; -}; - -void msm_dp_catalog_snapshot(struct msm_dp_catalog *msm_dp_catalog, struct= msm_disp_state *disp_state) -{ - msm_disp_snapshot_add_block(disp_state, - msm_dp_catalog->ahb_len, msm_dp_catalog->ahb_base, "dp_ahb"); - msm_disp_snapshot_add_block(disp_state, - msm_dp_catalog->aux_len, msm_dp_catalog->aux_base, "dp_aux"); - msm_disp_snapshot_add_block(disp_state, - msm_dp_catalog->link_len, msm_dp_catalog->link_base, "dp_link"); - msm_disp_snapshot_add_block(disp_state, - msm_dp_catalog->p0_len, msm_dp_catalog->p0_base, "dp_p0"); -} - -static void __iomem *msm_dp_ioremap(struct platform_device *pdev, int idx,= size_t *len) -{ - struct resource *res; - void __iomem *base; - - base =3D devm_platform_get_and_ioremap_resource(pdev, idx, &res); - if (!IS_ERR(base)) - *len =3D resource_size(res); - - return base; -} - -static int msm_dp_catalog_get_io(struct msm_dp_catalog_private *catalog) -{ - struct msm_dp_catalog *msm_dp_catalog =3D &catalog->msm_dp_catalog; - struct platform_device *pdev =3D to_platform_device(catalog->dev); - - msm_dp_catalog->ahb_base =3D msm_dp_ioremap(pdev, 0, &msm_dp_catalog->ahb= _len); - if (IS_ERR(msm_dp_catalog->ahb_base)) - return PTR_ERR(msm_dp_catalog->ahb_base); - - msm_dp_catalog->aux_base =3D msm_dp_ioremap(pdev, 1, &msm_dp_catalog->aux= _len); - if (IS_ERR(msm_dp_catalog->aux_base)) { - /* - * The initial binding had a single reg, but in order to - * support variation in the sub-region sizes this was split. - * msm_dp_ioremap() will fail with -EINVAL here if only a single - * reg is specified, so fill in the sub-region offsets and - * lengths based on this single region. - */ - if (PTR_ERR(msm_dp_catalog->aux_base) =3D=3D -EINVAL) { - if (msm_dp_catalog->ahb_len < DP_DEFAULT_P0_OFFSET + DP_DEFAULT_P0_SIZE= ) { - DRM_ERROR("legacy memory region not large enough\n"); - return -EINVAL; - } - - msm_dp_catalog->ahb_len =3D DP_DEFAULT_AHB_SIZE; - msm_dp_catalog->aux_base =3D msm_dp_catalog->ahb_base + DP_DEFAULT_AUX_= OFFSET; - msm_dp_catalog->aux_len =3D DP_DEFAULT_AUX_SIZE; - msm_dp_catalog->link_base =3D msm_dp_catalog->ahb_base + - DP_DEFAULT_LINK_OFFSET; - msm_dp_catalog->link_len =3D DP_DEFAULT_LINK_SIZE; - msm_dp_catalog->p0_base =3D msm_dp_catalog->ahb_base + DP_DEFAULT_P0_OF= FSET; - msm_dp_catalog->p0_len =3D DP_DEFAULT_P0_SIZE; - } else { - DRM_ERROR("unable to remap aux region: %pe\n", msm_dp_catalog->aux_base= ); - return PTR_ERR(msm_dp_catalog->aux_base); - } - } else { - msm_dp_catalog->link_base =3D msm_dp_ioremap(pdev, 2, &msm_dp_catalog->l= ink_len); - if (IS_ERR(msm_dp_catalog->link_base)) { - DRM_ERROR("unable to remap link region: %pe\n", msm_dp_catalog->link_ba= se); - return PTR_ERR(msm_dp_catalog->link_base); - } - - msm_dp_catalog->p0_base =3D msm_dp_ioremap(pdev, 3, &msm_dp_catalog->p0_= len); - if (IS_ERR(msm_dp_catalog->p0_base)) { - DRM_ERROR("unable to remap p0 region: %pe\n", msm_dp_catalog->p0_base); - return PTR_ERR(msm_dp_catalog->p0_base); - } - } - - return 0; -} - -struct msm_dp_catalog *msm_dp_catalog_get(struct device *dev) -{ - struct msm_dp_catalog_private *catalog; - int ret; - - catalog =3D devm_kzalloc(dev, sizeof(*catalog), GFP_KERNEL); - if (!catalog) - return ERR_PTR(-ENOMEM); - - catalog->dev =3D dev; - - ret =3D msm_dp_catalog_get_io(catalog); - if (ret) - return ERR_PTR(ret); - - return &catalog->msm_dp_catalog; -} diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/d= p_catalog.h deleted file mode 100644 index ddbae0fcf5fc428b2d37cd1eab1d5860a2f11a50..000000000000000000000000000= 0000000000000 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. - */ - -#ifndef _DP_CATALOG_H_ -#define _DP_CATALOG_H_ - -#include - -#include "dp_utils.h" -#include "disp/msm_disp_snapshot.h" - -#define DP_HW_VERSION_1_0 0x10000000 -#define DP_HW_VERSION_1_2 0x10020000 - -struct msm_dp_catalog { - bool wide_bus_en; - - void __iomem *ahb_base; - size_t ahb_len; - - void __iomem *aux_base; - size_t aux_len; - - void __iomem *link_base; - size_t link_len; - - void __iomem *p0_base; - size_t p0_len; -}; - -/* IO */ -static inline u32 msm_dp_read_aux(struct msm_dp_catalog *msm_dp_catalog, u= 32 offset) -{ - return readl_relaxed(msm_dp_catalog->aux_base + offset); -} - -static inline void msm_dp_write_aux(struct msm_dp_catalog *msm_dp_catalog, - u32 offset, u32 data) -{ - /* - * To make sure aux reg writes happens before any other operation, - * this function uses writel() instread of writel_relaxed() - */ - writel(data, msm_dp_catalog->aux_base + offset); -} - -static inline u32 msm_dp_read_ahb(const struct msm_dp_catalog *msm_dp_cata= log, u32 offset) -{ - return readl_relaxed(msm_dp_catalog->ahb_base + offset); -} - -static inline void msm_dp_write_ahb(struct msm_dp_catalog *msm_dp_catalog, - u32 offset, u32 data) -{ - /* - * To make sure phy reg writes happens before any other operation, - * this function uses writel() instread of writel_relaxed() - */ - writel(data, msm_dp_catalog->ahb_base + offset); -} - -static inline void msm_dp_write_p0(struct msm_dp_catalog *msm_dp_catalog, - u32 offset, u32 data) -{ - /* - * To make sure interface reg writes happens before any other operation, - * this function uses writel() instread of writel_relaxed() - */ - writel(data, msm_dp_catalog->p0_base + offset); -} - -static inline u32 msm_dp_read_p0(struct msm_dp_catalog *msm_dp_catalog, - u32 offset) -{ - return readl_relaxed(msm_dp_catalog->p0_base + offset); -} - -static inline u32 msm_dp_read_link(struct msm_dp_catalog *msm_dp_catalog, = u32 offset) -{ - return readl_relaxed(msm_dp_catalog->link_base + offset); -} - -static inline void msm_dp_write_link(struct msm_dp_catalog *msm_dp_catalog, - u32 offset, u32 data) -{ - /* - * To make sure link reg writes happens before any other operation, - * this function uses writel() instread of writel_relaxed() - */ - writel(data, msm_dp_catalog->link_base + offset); -} - -/* Debug module */ -void msm_dp_catalog_snapshot(struct msm_dp_catalog *msm_dp_catalog, struct= msm_disp_state *disp_state); - -struct msm_dp_catalog *msm_dp_catalog_get(struct device *dev); - -#endif /* _DP_CATALOG_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 82ed6da67b44e56015efe6ceb6038c79c16a9fa8..c42fd2c17a328f6deae211c9cd5= 7cc7416a9365a 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -6,6 +6,7 @@ #define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__ =20 #include +#include #include #include #include @@ -16,6 +17,7 @@ #include =20 #include +#include #include #include =20 @@ -114,7 +116,8 @@ struct msm_dp_ctrl_private { struct drm_dp_aux *aux; struct msm_dp_panel *panel; struct msm_dp_link *link; - struct msm_dp_catalog *catalog; + void __iomem *ahb_base; + void __iomem *link_base; =20 struct phy *phy; =20 @@ -139,6 +142,36 @@ struct msm_dp_ctrl_private { bool stream_clks_on; }; =20 +static inline u32 msm_dp_read_ahb(const struct msm_dp_ctrl_private *ctrl, = u32 offset) +{ + return readl_relaxed(ctrl->ahb_base + offset); +} + +static inline void msm_dp_write_ahb(struct msm_dp_ctrl_private *ctrl, + u32 offset, u32 data) +{ + /* + * To make sure phy reg writes happens before any other operation, + * this function uses writel() instread of writel_relaxed() + */ + writel(data, ctrl->ahb_base + offset); +} + +static inline u32 msm_dp_read_link(struct msm_dp_ctrl_private *ctrl, u32 o= ffset) +{ + return readl_relaxed(ctrl->link_base + offset); +} + +static inline void msm_dp_write_link(struct msm_dp_ctrl_private *ctrl, + u32 offset, u32 data) +{ + /* + * To make sure link reg writes happens before any other operation, + * this function uses writel() instread of writel_relaxed() + */ + writel(data, ctrl->link_base + offset); +} + static int msm_dp_aux_link_configure(struct drm_dp_aux *aux, struct msm_dp_link_info *link) { @@ -165,34 +198,32 @@ void msm_dp_ctrl_reset(struct msm_dp_ctrl *msm_dp_ctr= l) { struct msm_dp_ctrl_private *ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); - struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; u32 sw_reset; =20 - sw_reset =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_SW_RESET); + sw_reset =3D msm_dp_read_ahb(ctrl, REG_DP_SW_RESET); =20 sw_reset |=3D DP_SW_RESET; - msm_dp_write_ahb(msm_dp_catalog, REG_DP_SW_RESET, sw_reset); + msm_dp_write_ahb(ctrl, REG_DP_SW_RESET, sw_reset); usleep_range(1000, 1100); /* h/w recommended delay */ =20 sw_reset &=3D ~DP_SW_RESET; - msm_dp_write_ahb(msm_dp_catalog, REG_DP_SW_RESET, sw_reset); + msm_dp_write_ahb(ctrl, REG_DP_SW_RESET, sw_reset); =20 if (!ctrl->hw_revision) { - ctrl->hw_revision =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_HW_VERSION); + ctrl->hw_revision =3D msm_dp_read_ahb(ctrl, REG_DP_HW_VERSION); ctrl->panel->hw_revision =3D ctrl->hw_revision; } } =20 static u32 msm_dp_ctrl_get_aux_interrupt(struct msm_dp_ctrl_private *ctrl) { - struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; u32 intr, intr_ack; =20 - intr =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_INTR_STATUS); + intr =3D msm_dp_read_ahb(ctrl, REG_DP_INTR_STATUS); intr &=3D ~DP_INTERRUPT_STATUS1_MASK; intr_ack =3D (intr & DP_INTERRUPT_STATUS1) << DP_INTERRUPT_STATUS_ACK_SHIFT; - msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, + msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS, intr_ack | DP_INTERRUPT_STATUS1_MASK); =20 return intr; @@ -201,14 +232,13 @@ static u32 msm_dp_ctrl_get_aux_interrupt(struct msm_d= p_ctrl_private *ctrl) =20 static u32 msm_dp_ctrl_get_interrupt(struct msm_dp_ctrl_private *ctrl) { - struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; u32 intr, intr_ack; =20 - intr =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2); + intr =3D msm_dp_read_ahb(ctrl, REG_DP_INTR_STATUS2); intr &=3D ~DP_INTERRUPT_STATUS2_MASK; intr_ack =3D (intr & DP_INTERRUPT_STATUS2) << DP_INTERRUPT_STATUS_ACK_SHIFT; - msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2, + msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS2, intr_ack | DP_INTERRUPT_STATUS2_MASK); =20 return intr; @@ -218,11 +248,10 @@ void msm_dp_ctrl_enable_irq(struct msm_dp_ctrl *msm_d= p_ctrl) { struct msm_dp_ctrl_private *ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); - struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; =20 - msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, + msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS, DP_INTERRUPT_STATUS1_MASK); - msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2, + msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS2, DP_INTERRUPT_STATUS2_MASK); } =20 @@ -230,111 +259,101 @@ void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *ms= m_dp_ctrl) { struct msm_dp_ctrl_private *ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); - struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; =20 - msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, 0x00); - msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2, 0x00); + msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS, 0x00); + msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS2, 0x00); } =20 static u32 msm_dp_ctrl_get_psr_interrupt(struct msm_dp_ctrl_private *ctrl) { - struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; u32 intr, intr_ack; =20 - intr =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_INTR_STATUS4); + intr =3D msm_dp_read_ahb(ctrl, REG_DP_INTR_STATUS4); intr_ack =3D (intr & DP_INTERRUPT_STATUS4) << DP_INTERRUPT_STATUS_ACK_SHIFT; - msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS4, intr_ack); + msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS4, intr_ack); =20 return intr; } =20 static void msm_dp_ctrl_config_psr_interrupt(struct msm_dp_ctrl_private *c= trl) { - struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; - - msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4); + msm_dp_write_ahb(ctrl, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4); } =20 static void msm_dp_ctrl_psr_mainlink_enable(struct msm_dp_ctrl_private *ct= rl) { - struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; u32 val; =20 - val =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); + val =3D msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); val |=3D DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, val); + msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, val); } =20 static void msm_dp_ctrl_psr_mainlink_disable(struct msm_dp_ctrl_private *c= trl) { - struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; u32 val; =20 - val =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); + val =3D msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); val &=3D ~DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, val); + msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, val); } =20 static void msm_dp_ctrl_mainlink_enable(struct msm_dp_ctrl_private *ctrl) { - struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; u32 mainlink_ctrl; =20 drm_dbg_dp(ctrl->drm_dev, "enable\n"); =20 - mainlink_ctrl =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); + mainlink_ctrl =3D msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); =20 mainlink_ctrl &=3D ~(DP_MAINLINK_CTRL_RESET | DP_MAINLINK_CTRL_ENABLE); - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); =20 mainlink_ctrl |=3D DP_MAINLINK_CTRL_RESET; - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); =20 mainlink_ctrl &=3D ~DP_MAINLINK_CTRL_RESET; - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); =20 mainlink_ctrl |=3D (DP_MAINLINK_CTRL_ENABLE | DP_MAINLINK_FB_BOUNDARY_SEL); - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } =20 static void msm_dp_ctrl_mainlink_disable(struct msm_dp_ctrl_private *ctrl) { - struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; u32 mainlink_ctrl; =20 drm_dbg_dp(ctrl->drm_dev, "disable\n"); =20 - mainlink_ctrl =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); + mainlink_ctrl =3D msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); mainlink_ctrl &=3D ~DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } =20 static void msm_dp_setup_peripheral_flush(struct msm_dp_ctrl_private *ctrl) { - struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; u32 mainlink_ctrl; =20 - mainlink_ctrl =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); + mainlink_ctrl =3D msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); =20 if (ctrl->hw_revision >=3D DP_HW_VERSION_1_2) mainlink_ctrl |=3D DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE; else mainlink_ctrl |=3D DP_MAINLINK_FLUSH_MODE_UPDATE_SDP; =20 - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } =20 static bool msm_dp_ctrl_mainlink_ready(struct msm_dp_ctrl_private *ctrl) { - struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; u32 data; int ret; =20 /* Poll for mainlink ready status */ - ret =3D readl_poll_timeout(msm_dp_catalog->link_base + REG_DP_MAINLINK_RE= ADY, + ret =3D readl_poll_timeout(ctrl->link_base + REG_DP_MAINLINK_READY, data, data & DP_MAINLINK_READY_FOR_VIDEO, POLLING_SLEEP_US, POLLING_TIMEOUT_US); if (ret < 0) { @@ -352,7 +371,7 @@ void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_c= trl) ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); =20 reinit_completion(&ctrl->idle_comp); - msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_PUSH_ID= LE); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_PUSH_IDLE); =20 if (!wait_for_completion_timeout(&ctrl->idle_comp, IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES)) @@ -399,12 +418,11 @@ static void msm_dp_ctrl_config_ctrl(struct msm_dp_ctr= l_private *ctrl) =20 drm_dbg_dp(ctrl->drm_dev, "DP_CONFIGURATION_CTRL=3D0x%x\n", config); =20 - msm_dp_write_link(ctrl->catalog, REG_DP_CONFIGURATION_CTRL, config); + msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); } =20 static void msm_dp_ctrl_lane_mapping(struct msm_dp_ctrl_private *ctrl) { - struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; u32 ln_0 =3D 0, ln_1 =3D 1, ln_2 =3D 2, ln_3 =3D 3; /* One-to-One mapping= */ u32 ln_mapping; =20 @@ -413,7 +431,7 @@ static void msm_dp_ctrl_lane_mapping(struct msm_dp_ctrl= _private *ctrl) ln_mapping |=3D ln_2 << LANE2_MAPPING_SHIFT; ln_mapping |=3D ln_3 << LANE3_MAPPING_SHIFT; =20 - msm_dp_write_link(msm_dp_catalog, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, + msm_dp_write_link(ctrl, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, ln_mapping); } =20 @@ -429,7 +447,7 @@ static void msm_dp_ctrl_configure_source_params(struct = msm_dp_ctrl_private *ctrl test_bits_depth =3D msm_dp_link_get_test_bits_depth(ctrl->link, ctrl->pan= el->msm_dp_mode.bpp); colorimetry_cfg =3D msm_dp_link_get_colorimetry_config(ctrl->link); =20 - misc_val =3D msm_dp_read_link(ctrl->catalog, REG_DP_MISC1_MISC0); + misc_val =3D msm_dp_read_link(ctrl, REG_DP_MISC1_MISC0); =20 /* clear bpp bits */ misc_val &=3D ~(0x07 << DP_MISC0_TEST_BITS_DEPTH_SHIFT); @@ -439,9 +457,9 @@ static void msm_dp_ctrl_configure_source_params(struct = msm_dp_ctrl_private *ctrl misc_val |=3D DP_MISC0_SYNCHRONOUS_CLK; =20 drm_dbg_dp(ctrl->drm_dev, "misc settings =3D 0x%x\n", misc_val); - msm_dp_write_link(ctrl->catalog, REG_DP_MISC1_MISC0, misc_val); + msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0, misc_val); =20 - msm_dp_panel_timing_cfg(ctrl->panel); + msm_dp_panel_timing_cfg(ctrl->panel, ctrl->msm_dp_ctrl.wide_bus_en); } =20 /* @@ -1257,9 +1275,9 @@ static void msm_dp_ctrl_setup_tr_unit(struct msm_dp_c= trl_private *ctrl) pr_debug("dp_tu=3D0x%x, valid_boundary=3D0x%x, valid_boundary2=3D0x%x\n", msm_dp_tu, valid_boundary, valid_boundary2); =20 - msm_dp_write_link(ctrl->catalog, REG_DP_VALID_BOUNDARY, valid_boundary); - msm_dp_write_link(ctrl->catalog, REG_DP_TU, msm_dp_tu); - msm_dp_write_link(ctrl->catalog, REG_DP_VALID_BOUNDARY_2, valid_boundary2= ); + msm_dp_write_link(ctrl, REG_DP_VALID_BOUNDARY, valid_boundary); + msm_dp_write_link(ctrl, REG_DP_TU, msm_dp_tu); + msm_dp_write_link(ctrl, REG_DP_VALID_BOUNDARY_2, valid_boundary2); } =20 static int msm_dp_ctrl_wait4video_ready(struct msm_dp_ctrl_private *ctrl) @@ -1376,12 +1394,12 @@ static int msm_dp_ctrl_set_pattern_state_bit(struct= msm_dp_ctrl_private *ctrl, =20 bit =3D BIT(state_bit - 1); drm_dbg_dp(ctrl->drm_dev, "hw: bit=3D%d train=3D%d\n", bit, state_bit); - msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, bit); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, bit); =20 bit =3D BIT(state_bit - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT; =20 /* Poll for mainlink ready status */ - ret =3D readx_poll_timeout(readl, ctrl->catalog->link_base + REG_DP_MAINL= INK_READY, + ret =3D readx_poll_timeout(readl, ctrl->link_base + REG_DP_MAINLINK_READY, data, data & bit, POLLING_SLEEP_US, POLLING_TIMEOUT_US); if (ret < 0) { @@ -1403,7 +1421,7 @@ static int msm_dp_ctrl_link_train_1(struct msm_dp_ctr= l_private *ctrl, delay_us =3D drm_dp_read_clock_recovery_delay(ctrl->aux, ctrl->panel->dpcd, dp_phy, false); =20 - msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, 0); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); =20 *training_step =3D DP_TRAINING_1; =20 @@ -1521,7 +1539,7 @@ static int msm_dp_ctrl_link_train_2(struct msm_dp_ctr= l_private *ctrl, delay_us =3D drm_dp_read_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd, dp_phy, false); =20 - msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, 0); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); =20 *training_step =3D DP_TRAINING_2; =20 @@ -1638,7 +1656,7 @@ static int msm_dp_ctrl_link_train(struct msm_dp_ctrl_= private *ctrl, } =20 end: - msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, 0); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); =20 return ret; } @@ -1783,55 +1801,50 @@ static int msm_dp_ctrl_enable_mainlink_clocks(struc= t msm_dp_ctrl_private *ctrl) =20 static void msm_dp_ctrl_enable_sdp(struct msm_dp_ctrl_private *ctrl) { - struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; - /* trigger sdp */ - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, UPDATE_SDP); - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, 0x0); + msm_dp_write_link(ctrl, MMSS_DP_SDP_CFG3, UPDATE_SDP); + msm_dp_write_link(ctrl, MMSS_DP_SDP_CFG3, 0x0); } =20 static void msm_dp_ctrl_psr_enter(struct msm_dp_ctrl_private *ctrl) { - struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; u32 cmd; =20 - cmd =3D msm_dp_read_link(msm_dp_catalog, REG_PSR_CMD); + cmd =3D msm_dp_read_link(ctrl, REG_PSR_CMD); =20 cmd &=3D ~(PSR_ENTER | PSR_EXIT); cmd |=3D PSR_ENTER; =20 msm_dp_ctrl_enable_sdp(ctrl); - msm_dp_write_link(msm_dp_catalog, REG_PSR_CMD, cmd); + msm_dp_write_link(ctrl, REG_PSR_CMD, cmd); } =20 static void msm_dp_ctrl_psr_exit(struct msm_dp_ctrl_private *ctrl) { - struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; u32 cmd; =20 - cmd =3D msm_dp_read_link(msm_dp_catalog, REG_PSR_CMD); + cmd =3D msm_dp_read_link(ctrl, REG_PSR_CMD); =20 cmd &=3D ~(PSR_ENTER | PSR_EXIT); cmd |=3D PSR_EXIT; =20 msm_dp_ctrl_enable_sdp(ctrl); - msm_dp_write_link(msm_dp_catalog, REG_PSR_CMD, cmd); + msm_dp_write_link(ctrl, REG_PSR_CMD, cmd); } =20 void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm_dp_ctrl) { struct msm_dp_ctrl_private *ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); - struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; u32 cfg; =20 if (!ctrl->panel->psr_cap.version) return; =20 /* enable PSR1 function */ - cfg =3D msm_dp_read_link(msm_dp_catalog, REG_PSR_CONFIG); + cfg =3D msm_dp_read_link(ctrl, REG_PSR_CONFIG); cfg |=3D PSR1_SUPPORTED; - msm_dp_write_link(msm_dp_catalog, REG_PSR_CONFIG, cfg); + msm_dp_write_link(ctrl, REG_PSR_CONFIG, cfg); =20 msm_dp_ctrl_config_psr_interrupt(ctrl); msm_dp_ctrl_enable_sdp(ctrl); @@ -1870,25 +1883,25 @@ void msm_dp_ctrl_set_psr(struct msm_dp_ctrl *msm_dp= _ctrl, bool enter) } =20 msm_dp_ctrl_push_idle(msm_dp_ctrl); - msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, 0); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); =20 msm_dp_ctrl_psr_mainlink_disable(ctrl); } else { msm_dp_ctrl_psr_mainlink_enable(ctrl); =20 msm_dp_ctrl_psr_exit(ctrl); - msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_V= IDEO); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); msm_dp_ctrl_wait4video_ready(ctrl); - msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, 0); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); } } =20 static void msm_dp_ctrl_phy_reset(struct msm_dp_ctrl_private *ctrl) { - msm_dp_write_ahb(ctrl->catalog, REG_DP_PHY_CTRL, + msm_dp_write_ahb(ctrl, REG_DP_PHY_CTRL, DP_PHY_CTRL_SW_RESET | DP_PHY_CTRL_SW_RESET_PLL); usleep_range(1000, 1100); /* h/w recommended delay */ - msm_dp_write_ahb(ctrl->catalog, REG_DP_PHY_CTRL, 0x0); + msm_dp_write_ahb(ctrl, REG_DP_PHY_CTRL, 0x0); } =20 void msm_dp_ctrl_phy_init(struct msm_dp_ctrl *msm_dp_ctrl) @@ -1990,7 +2003,7 @@ static int msm_dp_ctrl_link_maintenance(struct msm_dp= _ctrl_private *ctrl) =20 msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); =20 - msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VI= DEO); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); =20 ret =3D msm_dp_ctrl_wait4video_ready(ctrl); end: @@ -2002,75 +2015,74 @@ static int msm_dp_ctrl_link_maintenance(struct msm_= dp_ctrl_private *ctrl) static void msm_dp_ctrl_send_phy_pattern(struct msm_dp_ctrl_private *ctrl, u32 pattern) { - struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; u32 value =3D 0x0; =20 /* Make sure to clear the current pattern before starting a new one */ - msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, 0x0); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0x0); =20 drm_dbg_dp(ctrl->drm_dev, "pattern: %#x\n", pattern); switch (pattern) { case DP_PHY_TEST_PATTERN_D10_2: - msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_LINK_TRAINING_PATTERN1); break; =20 case DP_PHY_TEST_PATTERN_ERROR_COUNT: value &=3D ~(1 << 16); - msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value); value |=3D SCRAMBLER_RESET_COUNT_VALUE; - msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value); - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_LEVELS, + msm_dp_write_link(ctrl, REG_DP_MAINLINK_LEVELS, DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); - msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); break; =20 case DP_PHY_TEST_PATTERN_PRBS7: - msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_LINK_PRBS7); break; =20 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: - msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN); /* 00111110000011111000001111100000 */ - msm_dp_write_link(msm_dp_catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0, + msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0, 0x3E0F83E0); /* 00001111100000111110000011111000 */ - msm_dp_write_link(msm_dp_catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1, + msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1, 0x0F83E0F8); /* 1111100000111110 */ - msm_dp_write_link(msm_dp_catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2, + msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2, 0x0000F83E); break; =20 case DP_PHY_TEST_PATTERN_CP2520: - value =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); + value =3D msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); value &=3D ~DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER; - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, value); + msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, value); =20 value =3D DP_HBR2_ERM_PATTERN; - msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value); value |=3D SCRAMBLER_RESET_COUNT_VALUE; - msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value); - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_LEVELS, + msm_dp_write_link(ctrl, REG_DP_MAINLINK_LEVELS, DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); - msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); - value =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); + value =3D msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); value |=3D DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, value); + msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, value); break; =20 case DP_PHY_TEST_PATTERN_SEL_MASK: - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, + msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, DP_MAINLINK_CTRL_ENABLE); - msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_LINK_TRAINING_PATTERN4); break; =20 @@ -2099,7 +2111,7 @@ static bool msm_dp_ctrl_send_phy_test_pattern(struct = msm_dp_ctrl_private *ctrl) msm_dp_ctrl_update_phy_vx_px(ctrl, DP_PHY_DPRX); msm_dp_link_send_test_response(ctrl->link); =20 - pattern_sent =3D msm_dp_read_link(ctrl->catalog, REG_DP_MAINLINK_READY); + pattern_sent =3D msm_dp_read_link(ctrl, REG_DP_MAINLINK_READY); =20 switch (pattern_sent) { case MR_LINK_TRAINING1: @@ -2430,8 +2442,8 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl= _private *ctrl, nvid *=3D 3; =20 drm_dbg_dp(ctrl->drm_dev, "mvid=3D0x%x, nvid=3D0x%x\n", mvid, nvid); - msm_dp_write_link(ctrl->catalog, REG_DP_SOFTWARE_MVID, mvid); - msm_dp_write_link(ctrl->catalog, REG_DP_SOFTWARE_NVID, nvid); + msm_dp_write_link(ctrl, REG_DP_SOFTWARE_MVID, mvid); + msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID, nvid); } =20 int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link= _train) @@ -2508,7 +2520,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl, bool force_link_train =20 msm_dp_ctrl_setup_tr_unit(ctrl); =20 - msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VI= DEO); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); =20 ret =3D msm_dp_ctrl_wait4video_ready(ctrl); if (ret) @@ -2705,14 +2717,14 @@ static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl = *msm_dp_ctrl) =20 struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link= *link, struct msm_dp_panel *panel, struct drm_dp_aux *aux, - struct msm_dp_catalog *catalog, - struct phy *phy) + struct phy *phy, + void __iomem *ahb_base, + void __iomem *link_base) { struct msm_dp_ctrl_private *ctrl; int ret; =20 - if (!dev || !panel || !aux || - !link || !catalog) { + if (!dev || !panel || !aux || !link) { DRM_ERROR("invalid input\n"); return ERR_PTR(-EINVAL); } @@ -2743,9 +2755,10 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *d= ev, struct msm_dp_link *link ctrl->panel =3D panel; ctrl->aux =3D aux; ctrl->link =3D link; - ctrl->catalog =3D catalog; ctrl->dev =3D dev; ctrl->phy =3D phy; + ctrl->ahb_base =3D ahb_base; + ctrl->link_base =3D link_base; =20 ret =3D msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl); if (ret) { diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index 10a4b7cf0335a584b4db67baca882620d7bab74c..124b9b21bb7f2d8616afcebb2cf= af3a2e7b482d1 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -9,7 +9,6 @@ #include "dp_aux.h" #include "dp_panel.h" #include "dp_link.h" -#include "dp_catalog.h" =20 struct msm_dp_ctrl { bool wide_bus_en; @@ -25,10 +24,13 @@ void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_handle_sink_request(struct msm_dp_ctrl *msm_dp_ctrl); -struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link= *link, - struct msm_dp_panel *panel, struct drm_dp_aux *aux, - struct msm_dp_catalog *catalog, - struct phy *phy); +struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, + struct msm_dp_link *link, + struct msm_dp_panel *panel, + struct drm_dp_aux *aux, + struct phy *phy, + void __iomem *ahb_base, + void __iomem *link_base); =20 void msm_dp_ctrl_reset(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_phy_init(struct msm_dp_ctrl *msm_dp_ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_debug.c b/drivers/gpu/drm/msm/dp/dp_= debug.c index 22fd946ee201397b72b43c8499714139deb7ba82..b65b358e98381488ecd0ecb8648= dbe76dd6ff310 100644 --- a/drivers/gpu/drm/msm/dp/dp_debug.c +++ b/drivers/gpu/drm/msm/dp/dp_debug.c @@ -9,7 +9,6 @@ #include #include =20 -#include "dp_catalog.h" #include "dp_aux.h" #include "dp_ctrl.h" #include "dp_debug.h" diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index e0ce410c6b26e10c36fff530b6b07e537c7ed759..96fb291b28d0290c6a43291c8de= a5533075341b3 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -19,7 +19,6 @@ #include "msm_drv.h" #include "msm_kms.h" #include "dp_ctrl.h" -#include "dp_catalog.h" #include "dp_aux.h" #include "dp_reg.h" #include "dp_link.h" @@ -87,7 +86,6 @@ struct msm_dp_display_private { =20 struct drm_device *drm_dev; =20 - struct msm_dp_catalog *catalog; struct drm_dp_aux *aux; struct msm_dp_link *link; struct msm_dp_panel *panel; @@ -112,6 +110,18 @@ struct msm_dp_display_private { bool wide_bus_supported; =20 struct msm_dp_audio *audio; + + void __iomem *ahb_base; + size_t ahb_len; + + void __iomem *aux_base; + size_t aux_len; + + void __iomem *link_base; + size_t link_len; + + void __iomem *p0_base; + size_t p0_len; }; =20 struct msm_dp_desc { @@ -751,21 +761,10 @@ static int msm_dp_init_sub_modules(struct msm_dp_disp= lay_private *dp) dp->msm_dp_display.is_edp ? PHY_SUBMODE_EDP : PHY_SUBMODE_DP); if (rc) { DRM_ERROR("failed to set phy submode, rc =3D %d\n", rc); - dp->catalog =3D NULL; - goto error; - } - - dp->catalog =3D msm_dp_catalog_get(dev); - if (IS_ERR(dp->catalog)) { - rc =3D PTR_ERR(dp->catalog); - DRM_ERROR("failed to initialize catalog, rc =3D %d\n", rc); - dp->catalog =3D NULL; goto error; } =20 - dp->aux =3D msm_dp_aux_get(dev, dp->catalog, - phy, - dp->msm_dp_display.is_edp); + dp->aux =3D msm_dp_aux_get(dev, phy, dp->msm_dp_display.is_edp, dp->aux_b= ase); if (IS_ERR(dp->aux)) { rc =3D PTR_ERR(dp->aux); DRM_ERROR("failed to initialize aux, rc =3D %d\n", rc); @@ -781,7 +780,7 @@ static int msm_dp_init_sub_modules(struct msm_dp_displa= y_private *dp) goto error_link; } =20 - dp->panel =3D msm_dp_panel_get(dev, dp->aux, dp->link, dp->catalog); + dp->panel =3D msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, dp-= >p0_base); if (IS_ERR(dp->panel)) { rc =3D PTR_ERR(dp->panel); DRM_ERROR("failed to initialize panel, rc =3D %d\n", rc); @@ -790,8 +789,7 @@ static int msm_dp_init_sub_modules(struct msm_dp_displa= y_private *dp) } =20 dp->ctrl =3D msm_dp_ctrl_get(dev, dp->link, dp->panel, dp->aux, - dp->catalog, - phy); + phy, dp->ahb_base, dp->link_base); if (IS_ERR(dp->ctrl)) { rc =3D PTR_ERR(dp->ctrl); DRM_ERROR("failed to initialize ctrl, rc =3D %d\n", rc); @@ -799,7 +797,7 @@ static int msm_dp_init_sub_modules(struct msm_dp_displa= y_private *dp) goto error_ctrl; } =20 - dp->audio =3D msm_dp_audio_get(dp->msm_dp_display.pdev, dp->catalog); + dp->audio =3D msm_dp_audio_get(dp->msm_dp_display.pdev, dp->link_base); if (IS_ERR(dp->audio)) { rc =3D PTR_ERR(dp->audio); pr_err("failed to initialize audio, rc =3D %d\n", rc); @@ -1022,7 +1020,14 @@ void msm_dp_snapshot(struct msm_disp_state *disp_sta= te, struct msm_dp *dp) return; } =20 - msm_dp_catalog_snapshot(msm_dp_display->catalog, disp_state); + msm_disp_snapshot_add_block(disp_state, msm_dp_display->ahb_len, + msm_dp_display->ahb_base, "dp_ahb"); + msm_disp_snapshot_add_block(disp_state, msm_dp_display->aux_len, + msm_dp_display->aux_base, "dp_aux"); + msm_disp_snapshot_add_block(disp_state, msm_dp_display->link_len, + msm_dp_display->link_base, "dp_link"); + msm_disp_snapshot_add_block(disp_state, msm_dp_display->p0_len, + msm_dp_display->p0_base, "dp_p0"); =20 mutex_unlock(&msm_dp_display->event_mutex); } @@ -1269,6 +1274,80 @@ static int msm_dp_display_get_connector_type(struct = platform_device *pdev, return connector_type; } =20 +static void __iomem *msm_dp_ioremap(struct platform_device *pdev, int idx,= size_t *len) +{ + struct resource *res; + void __iomem *base; + + base =3D devm_platform_get_and_ioremap_resource(pdev, idx, &res); + if (!IS_ERR(base)) + *len =3D resource_size(res); + + return base; +} + +#define DP_DEFAULT_AHB_OFFSET 0x0000 +#define DP_DEFAULT_AHB_SIZE 0x0200 +#define DP_DEFAULT_AUX_OFFSET 0x0200 +#define DP_DEFAULT_AUX_SIZE 0x0200 +#define DP_DEFAULT_LINK_OFFSET 0x0400 +#define DP_DEFAULT_LINK_SIZE 0x0C00 +#define DP_DEFAULT_P0_OFFSET 0x1000 +#define DP_DEFAULT_P0_SIZE 0x0400 + +static int msm_dp_display_get_io(struct msm_dp_display_private *display) +{ + struct platform_device *pdev =3D display->msm_dp_display.pdev; + + display->ahb_base =3D msm_dp_ioremap(pdev, 0, &display->ahb_len); + if (IS_ERR(display->ahb_base)) + return PTR_ERR(display->ahb_base); + + display->aux_base =3D msm_dp_ioremap(pdev, 1, &display->aux_len); + if (IS_ERR(display->aux_base)) { + if (display->aux_base !=3D ERR_PTR(-EINVAL)) { + DRM_ERROR("unable to remap aux region: %pe\n", display->aux_base); + return PTR_ERR(display->aux_base); + } + + /* + * The initial binding had a single reg, but in order to + * support variation in the sub-region sizes this was split. + * msm_dp_ioremap() will fail with -EINVAL here if only a single + * reg is specified, so fill in the sub-region offsets and + * lengths based on this single region. + */ + if (display->ahb_len < DP_DEFAULT_P0_OFFSET + DP_DEFAULT_P0_SIZE) { + DRM_ERROR("legacy memory region not large enough\n"); + return -EINVAL; + } + + display->ahb_len =3D DP_DEFAULT_AHB_SIZE; + display->aux_base =3D display->ahb_base + DP_DEFAULT_AUX_OFFSET; + display->aux_len =3D DP_DEFAULT_AUX_SIZE; + display->link_base =3D display->ahb_base + DP_DEFAULT_LINK_OFFSET; + display->link_len =3D DP_DEFAULT_LINK_SIZE; + display->p0_base =3D display->ahb_base + DP_DEFAULT_P0_OFFSET; + display->p0_len =3D DP_DEFAULT_P0_SIZE; + + return 0; + } + + display->link_base =3D msm_dp_ioremap(pdev, 2, &display->link_len); + if (IS_ERR(display->link_base)) { + DRM_ERROR("unable to remap link region: %pe\n", display->link_base); + return PTR_ERR(display->link_base); + } + + display->p0_base =3D msm_dp_ioremap(pdev, 3, &display->p0_len); + if (IS_ERR(display->p0_base)) { + DRM_ERROR("unable to remap p0 region: %pe\n", display->p0_base); + return PTR_ERR(display->p0_base); + } + + return 0; +} + static int msm_dp_display_probe(struct platform_device *pdev) { int rc =3D 0; @@ -1295,6 +1374,10 @@ static int msm_dp_display_probe(struct platform_devi= ce *pdev) dp->msm_dp_display.is_edp =3D (dp->msm_dp_display.connector_type =3D=3D DRM_MODE_CONNECTOR_eDP); =20 + rc =3D msm_dp_display_get_io(dp); + if (rc) + return rc; + rc =3D msm_dp_init_sub_modules(dp); if (rc) { DRM_ERROR("init sub module failed\n"); @@ -1640,8 +1723,6 @@ void msm_dp_bridge_mode_set(struct drm_bridge *drm_br= idge, /* populate wide_bus_support to different layers */ msm_dp_display->ctrl->wide_bus_en =3D msm_dp_display->msm_dp_mode.out_fmt_is_yuv_420 ? false : msm_dp_display-= >wide_bus_supported; - msm_dp_display->catalog->wide_bus_en =3D - msm_dp_display->msm_dp_mode.out_fmt_is_yuv_420 ? false : msm_dp_display-= >wide_bus_supported; } =20 void msm_dp_bridge_hpd_enable(struct drm_bridge *bridge) diff --git a/drivers/gpu/drm/msm/dp/dp_link.c b/drivers/gpu/drm/msm/dp/dp_l= ink.c index 92a9077959b3ec10c2a529db1a0e9fb3562aa5d3..66e1bbd80db3a28f5f16d083486= 752007ceaf3f7 100644 --- a/drivers/gpu/drm/msm/dp/dp_link.c +++ b/drivers/gpu/drm/msm/dp/dp_link.c @@ -5,6 +5,7 @@ =20 #define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__ =20 +#include #include =20 #include "dp_reg.h" diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index 7953b09b2fbd5c512ffe7c217b7fce986e4d9262..489e39f6c0ac0d2ce18d0ff83b5= fed23770a6b1e 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -23,10 +23,46 @@ struct msm_dp_panel_private { struct msm_dp_panel msm_dp_panel; struct drm_dp_aux *aux; struct msm_dp_link *link; - struct msm_dp_catalog *catalog; + void __iomem *link_base; + void __iomem *p0_base; bool panel_on; }; =20 +static inline u32 msm_dp_read_link(struct msm_dp_panel_private *panel, u32= offset) +{ + return readl_relaxed(panel->link_base + offset); +} + +static inline void msm_dp_write_link(struct msm_dp_panel_private *panel, + u32 offset, u32 data) +{ + /* + * To make sure link reg writes happens before any other operation, + * this function uses writel() instread of writel_relaxed() + */ + writel(data, panel->link_base + offset); +} + +static inline void msm_dp_write_p0(struct msm_dp_panel_private *panel, + u32 offset, u32 data) +{ + /* + * To make sure interface reg writes happens before any other operation, + * this function uses writel() instread of writel_relaxed() + */ + writel(data, panel->p0_base + offset); +} + +static inline u32 msm_dp_read_p0(struct msm_dp_panel_private *panel, + u32 offset) +{ + /* + * To make sure interface reg writes happens before any other operation, + * this function uses writel() instread of writel_relaxed() + */ + return readl_relaxed(panel->p0_base + offset); +} + static void msm_dp_panel_read_psr_cap(struct msm_dp_panel_private *panel) { ssize_t rlen; @@ -260,7 +296,6 @@ static void msm_dp_panel_tpg_enable(struct msm_dp_panel= *msm_dp_panel, { struct msm_dp_panel_private *panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); - struct msm_dp_catalog *catalog =3D panel->catalog; u32 hsync_period, vsync_period; u32 display_v_start, display_v_end; u32 hsync_start_x, hsync_end_x; @@ -292,33 +327,33 @@ static void msm_dp_panel_tpg_enable(struct msm_dp_pan= el *msm_dp_panel, display_hctl =3D (hsync_end_x << 16) | hsync_start_x; =20 =20 - msm_dp_write_p0(catalog, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); - msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period * + msm_dp_write_p0(panel, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); + msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period); - msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width * + msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width * hsync_period); - msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); - msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_HCTL, 0); - msm_dp_write_p0(catalog, MMSS_INTF_DISPLAY_V_START_F0, display_v_start); - msm_dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end); - msm_dp_write_p0(catalog, MMSS_INTF_DISPLAY_V_START_F1, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_POLARITY_CTL, 0); - - msm_dp_write_p0(catalog, MMSS_DP_TPG_MAIN_CONTROL, + msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); + msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); + msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); + msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_HCTL, 0); + msm_dp_write_p0(panel, MMSS_INTF_DISPLAY_V_START_F0, display_v_start); + msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end); + msm_dp_write_p0(panel, MMSS_INTF_DISPLAY_V_START_F1, 0); + msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); + msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); + msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); + msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); + msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); + msm_dp_write_p0(panel, MMSS_DP_INTF_POLARITY_CTL, 0); + + msm_dp_write_p0(panel, MMSS_DP_TPG_MAIN_CONTROL, DP_TPG_CHECKERED_RECT_PATTERN); - msm_dp_write_p0(catalog, MMSS_DP_TPG_VIDEO_CONFIG, + msm_dp_write_p0(panel, MMSS_DP_TPG_VIDEO_CONFIG, DP_TPG_VIDEO_CONFIG_BPP_8BIT | DP_TPG_VIDEO_CONFIG_RGB); - msm_dp_write_p0(catalog, MMSS_DP_BIST_ENABLE, + msm_dp_write_p0(panel, MMSS_DP_BIST_ENABLE, DP_BIST_ENABLE_DPBIST_EN); - msm_dp_write_p0(catalog, MMSS_DP_TIMING_ENGINE_EN, + msm_dp_write_p0(panel, MMSS_DP_TIMING_ENGINE_EN, DP_TIMING_ENGINE_EN_EN); drm_dbg_dp(panel->drm_dev, "%s: enabled tpg\n", __func__); } @@ -327,11 +362,10 @@ static void msm_dp_panel_tpg_disable(struct msm_dp_pa= nel *msm_dp_panel) { struct msm_dp_panel_private *panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); - struct msm_dp_catalog *catalog =3D panel->catalog; =20 - msm_dp_write_p0(catalog, MMSS_DP_TPG_MAIN_CONTROL, 0x0); - msm_dp_write_p0(catalog, MMSS_DP_BIST_ENABLE, 0x0); - msm_dp_write_p0(catalog, MMSS_DP_TIMING_ENGINE_EN, 0x0); + msm_dp_write_p0(panel, MMSS_DP_TPG_MAIN_CONTROL, 0x0); + msm_dp_write_p0(panel, MMSS_DP_BIST_ENABLE, 0x0); + msm_dp_write_p0(panel, MMSS_DP_TIMING_ENGINE_EN, 0x0); } =20 void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enabl= e) @@ -364,27 +398,25 @@ void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *= msm_dp_panel) { struct msm_dp_panel_private *panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); - struct msm_dp_catalog *catalog =3D panel->catalog; =20 - msm_dp_write_p0(catalog, MMSS_DP_DSC_DTO, 0x0); + msm_dp_write_p0(panel, MMSS_DP_DSC_DTO, 0x0); } =20 static void msm_dp_panel_send_vsc_sdp(struct msm_dp_panel_private *panel, = struct dp_sdp *vsc_sdp) { - struct msm_dp_catalog *msm_dp_catalog =3D panel->catalog; u32 header[2]; u32 val; int i; =20 msm_dp_utils_pack_sdp_header(&vsc_sdp->sdp_header, header); =20 - msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_0, header[0]); - msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_1, header[1]); + msm_dp_write_link(panel, MMSS_DP_GENERIC0_0, header[0]); + msm_dp_write_link(panel, MMSS_DP_GENERIC0_1, header[1]); =20 for (i =3D 0; i < sizeof(vsc_sdp->db); i +=3D 4) { val =3D ((vsc_sdp->db[i]) | (vsc_sdp->db[i + 1] << 8) | (vsc_sdp->db[i += 2] << 16) | (vsc_sdp->db[i + 3] << 24)); - msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_2 + i, val); + msm_dp_write_link(panel, MMSS_DP_GENERIC0_2 + i, val); } } =20 @@ -394,8 +426,8 @@ static void msm_dp_panel_update_sdp(struct msm_dp_panel= _private *panel) =20 if (hw_revision >=3D DP_HW_VERSION_1_0 && hw_revision < DP_HW_VERSION_1_2) { - msm_dp_write_link(panel->catalog, MMSS_DP_SDP_CFG3, UPDATE_SDP); - msm_dp_write_link(panel->catalog, MMSS_DP_SDP_CFG3, 0x0); + msm_dp_write_link(panel, MMSS_DP_SDP_CFG3, UPDATE_SDP); + msm_dp_write_link(panel, MMSS_DP_SDP_CFG3, 0x0); } } =20 @@ -403,18 +435,17 @@ void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel = *msm_dp_panel, struct dp_sd { struct msm_dp_panel_private *panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); - struct msm_dp_catalog *msm_dp_catalog =3D panel->catalog; u32 cfg, cfg2, misc; =20 - cfg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG); - cfg2 =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2); - misc =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MISC1_MISC0); + cfg =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG); + cfg2 =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG2); + misc =3D msm_dp_read_link(panel, REG_DP_MISC1_MISC0); =20 cfg |=3D GEN0_SDP_EN; - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, cfg); + msm_dp_write_link(panel, MMSS_DP_SDP_CFG, cfg); =20 cfg2 |=3D GENERIC0_SDPSIZE_VALID; - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, cfg2); + msm_dp_write_link(panel, MMSS_DP_SDP_CFG2, cfg2); =20 msm_dp_panel_send_vsc_sdp(panel, vsc_sdp); =20 @@ -424,7 +455,7 @@ void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *m= sm_dp_panel, struct dp_sd drm_dbg_dp(panel->drm_dev, "vsc sdp enable=3D1\n"); =20 pr_debug("misc settings =3D 0x%x\n", misc); - msm_dp_write_link(msm_dp_catalog, REG_DP_MISC1_MISC0, misc); + msm_dp_write_link(panel, REG_DP_MISC1_MISC0, misc); =20 msm_dp_panel_update_sdp(panel); } @@ -433,18 +464,17 @@ void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel= *msm_dp_panel) { struct msm_dp_panel_private *panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); - struct msm_dp_catalog *msm_dp_catalog =3D panel->catalog; u32 cfg, cfg2, misc; =20 - cfg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG); - cfg2 =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2); - misc =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MISC1_MISC0); + cfg =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG); + cfg2 =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG2); + misc =3D msm_dp_read_link(panel, REG_DP_MISC1_MISC0); =20 cfg &=3D ~GEN0_SDP_EN; - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, cfg); + msm_dp_write_link(panel, MMSS_DP_SDP_CFG, cfg); =20 cfg2 &=3D ~GENERIC0_SDPSIZE_VALID; - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, cfg2); + msm_dp_write_link(panel, MMSS_DP_SDP_CFG2, cfg2); =20 /* switch back to MSA */ misc &=3D ~DP_MISC1_VSC_SDP; @@ -452,7 +482,7 @@ void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *= msm_dp_panel) drm_dbg_dp(panel->drm_dev, "vsc sdp enable=3D0\n"); =20 pr_debug("misc settings =3D 0x%x\n", misc); - msm_dp_write_link(msm_dp_catalog, REG_DP_MISC1_MISC0, misc); + msm_dp_write_link(panel, REG_DP_MISC1_MISC0, misc); =20 msm_dp_panel_update_sdp(panel); } @@ -500,10 +530,9 @@ static int msm_dp_panel_setup_vsc_sdp_yuv_420(struct m= sm_dp_panel *msm_dp_panel) return 0; } =20 -int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel) +int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_b= us_en) { u32 data, total_ver, total_hor; - struct msm_dp_catalog *catalog; struct msm_dp_panel_private *panel; struct drm_display_mode *drm_mode; u32 width_blanking; @@ -513,7 +542,6 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp= _panel) u32 reg; =20 panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_= panel); - catalog =3D panel->catalog; drm_mode =3D &panel->msm_dp_panel.msm_dp_mode.drm_mode; =20 drm_dbg_dp(panel->drm_dev, "width=3D%d hporch=3D %d %d %d\n", @@ -556,20 +584,20 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_= dp_panel) =20 msm_dp_active =3D data; =20 - msm_dp_write_link(catalog, REG_DP_TOTAL_HOR_VER, total); - msm_dp_write_link(catalog, REG_DP_START_HOR_VER_FROM_SYNC, sync_start); - msm_dp_write_link(catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, width_blank= ing); - msm_dp_write_link(catalog, REG_DP_ACTIVE_HOR_VER, msm_dp_active); + msm_dp_write_link(panel, REG_DP_TOTAL_HOR_VER, total); + msm_dp_write_link(panel, REG_DP_START_HOR_VER_FROM_SYNC, sync_start); + msm_dp_write_link(panel, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, width_blankin= g); + msm_dp_write_link(panel, REG_DP_ACTIVE_HOR_VER, msm_dp_active); =20 - reg =3D msm_dp_read_p0(catalog, MMSS_DP_INTF_CONFIG); - if (catalog->wide_bus_en) + reg =3D msm_dp_read_p0(panel, MMSS_DP_INTF_CONFIG); + if (wide_bus_en) reg |=3D DP_INTF_CONFIG_DATABUS_WIDEN; else reg &=3D ~DP_INTF_CONFIG_DATABUS_WIDEN; =20 - drm_dbg_dp(panel->drm_dev, "wide_bus_en=3D%d reg=3D%#x\n", catalog->wide_= bus_en, reg); + drm_dbg_dp(panel->drm_dev, "wide_bus_en=3D%d reg=3D%#x\n", wide_bus_en, r= eg); =20 - msm_dp_write_p0(catalog, MMSS_DP_INTF_CONFIG, reg); + msm_dp_write_p0(panel, MMSS_DP_INTF_CONFIG, reg); =20 if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) msm_dp_panel_setup_vsc_sdp_yuv_420(msm_dp_panel); @@ -673,13 +701,15 @@ static int msm_dp_panel_parse_dt(struct msm_dp_panel = *msm_dp_panel) } =20 struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_au= x *aux, - struct msm_dp_link *link, struct msm_dp_catalog *catalog) + struct msm_dp_link *link, + void __iomem *link_base, + void __iomem *p0_base) { struct msm_dp_panel_private *panel; struct msm_dp_panel *msm_dp_panel; int ret; =20 - if (!dev || !catalog || !aux || !link) { + if (!dev || !aux || !link) { DRM_ERROR("invalid input\n"); return ERR_PTR(-EINVAL); } @@ -690,8 +720,9 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *de= v, struct drm_dp_aux *aux =20 panel->dev =3D dev; panel->aux =3D aux; - panel->catalog =3D catalog; panel->link =3D link; + panel->link_base =3D link_base; + panel->p0_base =3D p0_base; =20 msm_dp_panel =3D &panel->msm_dp_panel; msm_dp_panel->max_bw_code =3D DP_LINK_BW_8_1; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_= panel.h index c348417bb07f33efdf1402a73c27ff99e394e5a3..d2cf401506dcbaf553192d5e18c= 87207337664ab 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -6,6 +6,7 @@ #ifndef _DP_PANEL_H_ #define _DP_PANEL_H_ =20 +#include #include =20 #include "dp_aux.h" @@ -48,7 +49,7 @@ struct msm_dp_panel { =20 int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel); int msm_dp_panel_deinit(struct msm_dp_panel *msm_dp_panel); -int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel); +int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_b= us_en); int msm_dp_panel_read_sink_caps(struct msm_dp_panel *msm_dp_panel, struct drm_connector *connector); u32 msm_dp_panel_get_mode_bpp(struct msm_dp_panel *msm_dp_panel, u32 mode_= max_bpp, @@ -91,6 +92,8 @@ static inline bool is_lane_count_valid(u32 lane_count) } =20 struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_au= x *aux, - struct msm_dp_link *link, struct msm_dp_catalog *catalog); + struct msm_dp_link *link, + void __iomem *link_base, + void __iomem *p0_base); void msm_dp_panel_put(struct msm_dp_panel *msm_dp_panel); #endif /* _DP_PANEL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_re= g.h index d17e077ded73251624b5fb1bfbd8f213b4a86d65..7c44d4e2cf13960b5ab3277b158= 1ebbd539d4f65 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -11,6 +11,8 @@ =20 /* DP_TX Registers */ #define REG_DP_HW_VERSION (0x00000000) +#define DP_HW_VERSION_1_0 0x10000000 +#define DP_HW_VERSION_1_2 0x10020000 =20 #define REG_DP_SW_RESET (0x00000010) #define DP_SW_RESET (0x00000001) --=20 2.39.5