From nobody Wed Dec 17 07:10:22 2025 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E5222147F0; Sat, 17 May 2025 20:14:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747512871; cv=none; b=adBk8dBzNTJu1uD8bdx7baDI1xFjAAt2No/489RYb4T5eVy6HFkLcaA+XEkYDeYkbDVVPK/h3N8x0qEq+6I5CL5/Wdsmy7X1OXMDxD1ag7E/7YjDWjpwiwBT9c9X54gQfu6FR5sCvlp7nG7ys8JJoWq6+rKXwDxMoJ3rQZK/Q4M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747512871; c=relaxed/simple; bh=UeyHDMn4bp1Ui/bLDmpa/rWmqfFSNF//Lkq0ecvZZMw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jD+rQTejFfy4GQ7IIQ+IYwyM1MrjgZLT6cHKORzbmnTH6mnnJZaHWZD1oMMumvPdw3hj2uJH/ZZathU/Pghy2IVnX7gjeMxO0tzZ9D+Qy1pVu5cJq9N+Oe1QDKPRykTU1m4KmDACMSSyNWLhoW124cbBmQupyW0Ua+vBlvRF8RY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=MECB8zkv; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="MECB8zkv" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-441d1ed82dbso31135475e9.0; Sat, 17 May 2025 13:14:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1747512867; x=1748117667; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wjrKJJQ/alu21U0CaUScGyKXWxRO2mZ0HkmMBCRud/g=; b=MECB8zkvx4xhFcBPm8/50xL6F3Bw463DNllkufK3J8V06QYsFjk9dqk5sxzFXTeAm1 tQfSfb57SJ8U18N5qdJjwz/7OeLRBTArw179Vioze3givfKZpPHH1kzB91sskfV2QWs6 gigeXcb/QK9MOimT1c229SyZNTdgpUmbV4VxrGfmAvQsZUldHjaKZWqLry17ZtHr7Foj 7wRIpCkSKs1w9SO4dGUpGIFil3Jc05uXwiM5HKu5NexwYlyZcq/t+R3a1YdKaBomfMub sgXatVfnoWTXlzs3p6LZwN2YmfY0rCsddP1hmQPD30nKXRhfeJpMIXYfEbd20x0dMNOk b/kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747512867; x=1748117667; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wjrKJJQ/alu21U0CaUScGyKXWxRO2mZ0HkmMBCRud/g=; b=gb75mVGFYdurWXgpTMIGFzXmq3nDjog9NQXWsCUeDxUk0e1BbqXAFUiwox/O8H4dnT rNXCvlp59uX4hrA4D/QRAjSJGCi0vTlMIiYylVgvfr7huI0oWIk0z5U+VG2LMSW60KE+ sJcSqVyKJkcVmf+PviTqLkxbB6g6nPQpgJ+nX8mQ7hf1CPY5hYYajvmOQWHKaPP+9FaP Tah+XbCyhTit0i42ju/QaatQcMquxEFFr/NeJI2aYN0G5f11kypdMDawGyXM4tAzlec/ ZkgLYohF4/TRlsU5APyWymN89y2Aual6giMxh6cbWPb0bpx8iAO/2vCGT+4frthbqi9o 9opg== X-Forwarded-Encrypted: i=1; AJvYcCU/3zDBnkPMEP2ZycJkwNAodBaxoTAq4a3ec5pnwKVMFqPM7KuEEOxoKaePWexW4eQuw1oNaLuKuPNtg15M@vger.kernel.org, AJvYcCVVvi6coZvZo4XSmjj2lHoRFO0NIYWiMbMSjw8OphTXzn1hgFsLqC/uMyvQuc3FPpf02ztHSp0QD+b65bnkArQ=@vger.kernel.org, AJvYcCWRlCS/olGGEiNFok4rN61jKtVbXON7RmWWjFLuuboG5fv1jNIM6jGMYXdNLcPZvSFvfXOUXHy0mie0@vger.kernel.org, AJvYcCWxwv6UJwJHcO1haZPBcxH+GH1TnUqKBZRcffkzz2xFt1j4yDbSuysAMVUA3VraREUEuwHkT9n9@vger.kernel.org X-Gm-Message-State: AOJu0YyHNOzuDVpUGl0/9N+OPpD/cH6oZdWY2UFSk8LgsdzDL6FQfJml JmMcafVfvwfZfF31Fru4Z3/wLdIu3L3nyMakTC+hCJChym6h+N/KjXqy X-Gm-Gg: ASbGncsH3hQuMBF8DR8XiFqbgbqztlIFmebKh43QXoirzWNOEJ23HiRb3aFr1L9oAvz 4HnzvrIwd10EZP0wPEhh2EDg698XXKTd/CnTepXA8BE4YKA2RchJkHiMvHB5Ownzk4ESwPO3vrh 6/nGTDP4vfGyZ0cMcksqvCBDeo1WCr9VXlVB92cGCmz+CxIbNf/oRFtqUBteKOWjmudDCeh5WX8 JUjwNge8VbmtVYvKZBOeXabRCyoKO5kNhBNqNJCBalMJ4dwLB3+sB/ibDIyDkv246nKRrGsAyfx I/FYGG5vuDv5i2lfP1GSMrFdiaJfIIAuIg2x6VMWS+ucFYawlLBvzbo2C2Sc8c8QyA/pzZ78KGf bScAxbnXv9GAmlUVprwEp X-Google-Smtp-Source: AGHT+IEf84+aSQcfL21XHVBcjwGl0PxF1NE0XvvkKVkpZyv5o+O/CXk7Ibk/uD1u5HjeibRu+2tRbQ== X-Received: by 2002:a05:600c:4fd4:b0:441:b00d:e9d1 with SMTP id 5b1f17b1804b1-442fd606ce9mr86895945e9.2.1747512867367; Sat, 17 May 2025 13:14:27 -0700 (PDT) Received: from localhost.localdomain (93-34-88-225.ip49.fastwebnet.it. [93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-442fd4fdcccsm85345445e9.6.2025.05.17.13.14.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 May 2025 13:14:26 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , =?UTF-8?q?Marek=20Beh=C3=BAn?= , Andrei Botila , FUJITA Tomonori , Trevor Gross , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Danilo Krummrich , Sabrina Dubroca , Michael Klein , Daniel Golle , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org Cc: "Russell King (Oracle)" Subject: [net-next PATCH v12 1/6] net: phy: pass PHY driver to .match_phy_device OP Date: Sat, 17 May 2025 22:13:45 +0200 Message-ID: <20250517201353.5137-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250517201353.5137-1-ansuelsmth@gmail.com> References: <20250517201353.5137-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Pass PHY driver pointer to .match_phy_device OP in addition to phydev. Having access to the PHY driver struct might be useful to check the PHY ID of the driver is being matched for in case the PHY ID scanned in the phydev is not consistent. A scenario for this is a PHY that change PHY ID after a firmware is loaded, in such case, the PHY ID stored in PHY device struct is not valid anymore and PHY will manually scan the ID in the match_phy_device function. Having the PHY driver info is also useful for those PHY driver that implement multiple simple .match_phy_device OP to match specific MMD PHY ID. With this extra info if the parsing logic is the same, the matching function can be generalized by using the phy_id in the PHY driver instead of hardcoding. Rust wrapper callback is updated to align to the new match_phy_device arguments. Suggested-by: Russell King (Oracle) Reviewed-by: Russell King (Oracle) Signed-off-by: Christian Marangi Reviewed-by: Benno Lossin # for Rust Reviewed-by: FUJITA Tomonori --- drivers/net/phy/bcm87xx.c | 6 ++++-- drivers/net/phy/icplus.c | 6 ++++-- drivers/net/phy/marvell10g.c | 12 ++++++++---- drivers/net/phy/micrel.c | 6 ++++-- drivers/net/phy/nxp-c45-tja11xx.c | 12 ++++++++---- drivers/net/phy/nxp-tja11xx.c | 6 ++++-- drivers/net/phy/phy_device.c | 2 +- drivers/net/phy/realtek/realtek_main.c | 27 +++++++++++++++++--------- drivers/net/phy/teranetics.c | 3 ++- include/linux/phy.h | 3 ++- rust/kernel/net/phy.rs | 1 + 11 files changed, 56 insertions(+), 28 deletions(-) diff --git a/drivers/net/phy/bcm87xx.c b/drivers/net/phy/bcm87xx.c index e81404bf8994..1e1e2259fc2b 100644 --- a/drivers/net/phy/bcm87xx.c +++ b/drivers/net/phy/bcm87xx.c @@ -185,12 +185,14 @@ static irqreturn_t bcm87xx_handle_interrupt(struct ph= y_device *phydev) return IRQ_HANDLED; } =20 -static int bcm8706_match_phy_device(struct phy_device *phydev) +static int bcm8706_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return phydev->c45_ids.device_ids[4] =3D=3D PHY_ID_BCM8706; } =20 -static int bcm8727_match_phy_device(struct phy_device *phydev) +static int bcm8727_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return phydev->c45_ids.device_ids[4] =3D=3D PHY_ID_BCM8727; } diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c index bbcc7d2b54cd..c0c4f19cfb6a 100644 --- a/drivers/net/phy/icplus.c +++ b/drivers/net/phy/icplus.c @@ -520,12 +520,14 @@ static int ip101a_g_match_phy_device(struct phy_devic= e *phydev, bool ip101a) return ip101a =3D=3D !ret; } =20 -static int ip101a_match_phy_device(struct phy_device *phydev) +static int ip101a_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return ip101a_g_match_phy_device(phydev, true); } =20 -static int ip101g_match_phy_device(struct phy_device *phydev) +static int ip101g_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return ip101a_g_match_phy_device(phydev, false); } diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c index 5354c8895163..13e81dff42c1 100644 --- a/drivers/net/phy/marvell10g.c +++ b/drivers/net/phy/marvell10g.c @@ -1264,7 +1264,8 @@ static int mv3310_get_number_of_ports(struct phy_devi= ce *phydev) return ret + 1; } =20 -static int mv3310_match_phy_device(struct phy_device *phydev) +static int mv3310_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & MARVELL_PHY_ID_MASK) !=3D MARVELL_PHY_ID_88X3310) @@ -1273,7 +1274,8 @@ static int mv3310_match_phy_device(struct phy_device = *phydev) return mv3310_get_number_of_ports(phydev) =3D=3D 1; } =20 -static int mv3340_match_phy_device(struct phy_device *phydev) +static int mv3340_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & MARVELL_PHY_ID_MASK) !=3D MARVELL_PHY_ID_88X3310) @@ -1297,12 +1299,14 @@ static int mv211x_match_phy_device(struct phy_devic= e *phydev, bool has_5g) return !!(val & MDIO_PCS_SPEED_5G) =3D=3D has_5g; } =20 -static int mv2110_match_phy_device(struct phy_device *phydev) +static int mv2110_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return mv211x_match_phy_device(phydev, true); } =20 -static int mv2111_match_phy_device(struct phy_device *phydev) +static int mv2111_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return mv211x_match_phy_device(phydev, false); } diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index 71fb4410c31b..4d8460c93078 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -768,7 +768,8 @@ static int ksz8051_ksz8795_match_phy_device(struct phy_= device *phydev, return !ret; } =20 -static int ksz8051_match_phy_device(struct phy_device *phydev) +static int ksz8051_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return ksz8051_ksz8795_match_phy_device(phydev, true); } @@ -888,7 +889,8 @@ static int ksz8061_config_init(struct phy_device *phyde= v) return kszphy_config_init(phydev); } =20 -static int ksz8795_match_phy_device(struct phy_device *phydev) +static int ksz8795_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return ksz8051_ksz8795_match_phy_device(phydev, false); } diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tj= a11xx.c index f11dd32494c3..22921b192a8b 100644 --- a/drivers/net/phy/nxp-c45-tja11xx.c +++ b/drivers/net/phy/nxp-c45-tja11xx.c @@ -1966,25 +1966,29 @@ static int nxp_c45_macsec_ability(struct phy_device= *phydev) return macsec_ability; } =20 -static int tja1103_match_phy_device(struct phy_device *phydev) +static int tja1103_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return phy_id_compare(phydev->phy_id, PHY_ID_TJA_1103, PHY_ID_MASK) && !nxp_c45_macsec_ability(phydev); } =20 -static int tja1104_match_phy_device(struct phy_device *phydev) +static int tja1104_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return phy_id_compare(phydev->phy_id, PHY_ID_TJA_1103, PHY_ID_MASK) && nxp_c45_macsec_ability(phydev); } =20 -static int tja1120_match_phy_device(struct phy_device *phydev) +static int tja1120_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return phy_id_compare(phydev->phy_id, PHY_ID_TJA_1120, PHY_ID_MASK) && !nxp_c45_macsec_ability(phydev); } =20 -static int tja1121_match_phy_device(struct phy_device *phydev) +static int tja1121_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return phy_id_compare(phydev->phy_id, PHY_ID_TJA_1120, PHY_ID_MASK) && nxp_c45_macsec_ability(phydev); diff --git a/drivers/net/phy/nxp-tja11xx.c b/drivers/net/phy/nxp-tja11xx.c index 07e94a2478ac..3c38a8ddae2f 100644 --- a/drivers/net/phy/nxp-tja11xx.c +++ b/drivers/net/phy/nxp-tja11xx.c @@ -651,12 +651,14 @@ static int tja1102_match_phy_device(struct phy_device= *phydev, bool port0) return !ret; } =20 -static int tja1102_p0_match_phy_device(struct phy_device *phydev) +static int tja1102_p0_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return tja1102_match_phy_device(phydev, true); } =20 -static int tja1102_p1_match_phy_device(struct phy_device *phydev) +static int tja1102_p1_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return tja1102_match_phy_device(phydev, false); } diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index 2eb735e68dd8..96a96c0334a7 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -554,7 +554,7 @@ static int phy_bus_match(struct device *dev, const stru= ct device_driver *drv) return 0; =20 if (phydrv->match_phy_device) - return phydrv->match_phy_device(phydev); + return phydrv->match_phy_device(phydev, phydrv); =20 if (phydev->is_c45) { for (i =3D 1; i < num_ids; i++) { diff --git a/drivers/net/phy/realtek/realtek_main.c b/drivers/net/phy/realt= ek/realtek_main.c index 301fbe141b9b..6b655d3c7e1c 100644 --- a/drivers/net/phy/realtek/realtek_main.c +++ b/drivers/net/phy/realtek/realtek_main.c @@ -1314,13 +1314,15 @@ static bool rtlgen_supports_mmd(struct phy_device *= phydev) return val > 0; } =20 -static int rtlgen_match_phy_device(struct phy_device *phydev) +static int rtlgen_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return phydev->phy_id =3D=3D RTL_GENERIC_PHYID && !rtlgen_supports_2_5gbps(phydev); } =20 -static int rtl8226_match_phy_device(struct phy_device *phydev) +static int rtl8226_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return phydev->phy_id =3D=3D RTL_GENERIC_PHYID && rtlgen_supports_2_5gbps(phydev) && @@ -1336,32 +1338,38 @@ static int rtlgen_is_c45_match(struct phy_device *p= hydev, unsigned int id, return !is_c45 && (id =3D=3D phydev->phy_id); } =20 -static int rtl8221b_match_phy_device(struct phy_device *phydev) +static int rtl8221b_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return phydev->phy_id =3D=3D RTL_8221B && rtlgen_supports_mmd(phydev); } =20 -static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev) +static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false); } =20 -static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev) +static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true); } =20 -static int rtl8221b_vn_cg_c22_match_phy_device(struct phy_device *phydev) +static int rtl8221b_vn_cg_c22_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, false); } =20 -static int rtl8221b_vn_cg_c45_match_phy_device(struct phy_device *phydev) +static int rtl8221b_vn_cg_c45_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true); } =20 -static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev) +static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { if (phydev->is_c45) return false; @@ -1379,7 +1387,8 @@ static int rtl_internal_nbaset_match_phy_device(struc= t phy_device *phydev) return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev); } =20 -static int rtl8251b_c45_match_phy_device(struct phy_device *phydev) +static int rtl8251b_c45_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return rtlgen_is_c45_match(phydev, RTL_8251B, true); } diff --git a/drivers/net/phy/teranetics.c b/drivers/net/phy/teranetics.c index 752d4bf7bb99..46c5ff7d7b56 100644 --- a/drivers/net/phy/teranetics.c +++ b/drivers/net/phy/teranetics.c @@ -67,7 +67,8 @@ static int teranetics_read_status(struct phy_device *phyd= ev) return 0; } =20 -static int teranetics_match_phy_device(struct phy_device *phydev) +static int teranetics_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { return phydev->c45_ids.device_ids[3] =3D=3D PHY_ID_TN2020; } diff --git a/include/linux/phy.h b/include/linux/phy.h index 7c29d346d4b3..34ed85686b83 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -990,7 +990,8 @@ struct phy_driver { * driver for the given phydev. If NULL, matching is based on * phy_id and phy_id_mask. */ - int (*match_phy_device)(struct phy_device *phydev); + int (*match_phy_device)(struct phy_device *phydev, + const struct phy_driver *phydrv); =20 /** * @set_wol: Some devices (e.g. qnap TS-119P II) require PHY diff --git a/rust/kernel/net/phy.rs b/rust/kernel/net/phy.rs index a59469c785e3..32ea43ece646 100644 --- a/rust/kernel/net/phy.rs +++ b/rust/kernel/net/phy.rs @@ -421,6 +421,7 @@ impl Adapter { /// `phydev` must be passed by the corresponding callback in `phy_driv= er`. unsafe extern "C" fn match_phy_device_callback( phydev: *mut bindings::phy_device, + _phydrv: *const bindings::phy_driver, ) -> crate::ffi::c_int { // SAFETY: This callback is called only in contexts // where we hold `phy_device->lock`, so the accessors on --=20 2.48.1 From nobody Wed Dec 17 07:10:22 2025 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2FD3215198; Sat, 17 May 2025 20:14:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747512872; cv=none; b=UmNPkA/4AKguu4eM8jG5jHjK7F0zshriCbAFyQguFSVDo5s1lU7PaPADJ8SKTpt9ObFQrj/rRAJ2t/g1QlEAMDWO7k4MtJOvr9HU5pphjwEwUa5blifjk1cJ4XFWkdaqRhzqYE+iI0sMQXz+wSY9l7zut4R+1FA0udg+a4p8TPw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747512872; c=relaxed/simple; bh=9G4ubJ6lV4V2dWOs0FNh/K1YDBBBYb3K8frA6VqI9G8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OgvHD9pUlkBdrA0Nv6ptYHkkrk9G+MUrJM1XLGxIb+RdBOW9By37ANyGVe/YQ2R+Ma8U8hdsx2Mg56G7X5+YVUThaZfILdyQwWYvIGi2dyD4e0IdKPKL1oW4ixRHUA1usDFy14c42bWK3/dytCN/NjVMGf4mYPC3K5UKvcI5lB0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=liqWWzmH; arc=none smtp.client-ip=209.85.221.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="liqWWzmH" Received: by mail-wr1-f42.google.com with SMTP id ffacd0b85a97d-3a363d15c64so847369f8f.3; Sat, 17 May 2025 13:14:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1747512869; x=1748117669; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pvRhcUvsur4qZV9ZsxMG2pchOpKzL3rOM+elE1weNSU=; b=liqWWzmHg1ee4VFoip3O053X+AesVBVWJtyVi0mk6G7JNBKEMLoHelPHfxx8izvadB 6jzt3uXwSYo49akToyame61Qzhd1WgLa3PihuMgolvnfGU+/UEEY6t2nHpQnrHKHb1qH NpaOgbSENZx1gangmxwI+979WvK+j16Rvz9xxBXifw8a/G2SCZL+EInn/mg4+IplOfoU fmATVlmM3u3TLt0QN4wrJ2CIzb3hLcR7AlU8gW6IX/g/Xh1gI9ESqT7GA07CqKYsPjfV HR7WGJPpPZpm+oeOL5qkB3dpYNiTUFnzWsmWYRjlzOeZa7YiEmUCmhmIQUAgjQ/AhIG/ lXsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747512869; x=1748117669; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pvRhcUvsur4qZV9ZsxMG2pchOpKzL3rOM+elE1weNSU=; b=SBcKVfkF/1YjQxZhLeDovM0SBRDyh4OGETo9UuRJbAi4ereoNQIrKPTH5odhqdnSmG tGl2uPA+4su3JAyuA+3demXSRGde8HVW4SsM9M1Knn93OApfHujZhPbHFJWry7QBJ28H 4/7TNISX364iNGGi29GrNnucMZaWsXqiPoV3SUbMmD4oeuSws/np+nSWhW7J1LNcH7jb 1KSFtnmlNfobNQQaBpoV5g8vfekzH1Ge+QMP7f+xOJTuGgKEsYp6THxvbbhIlwCAl9eX y47vbkBdgDh21MyXqx8eCujDOg0yMsLKRxgfkjn0ivmnzTaxWf3vxR47wB966yIOkX5z UEmw== X-Forwarded-Encrypted: i=1; AJvYcCUHZioR+Ge3z12KovxVy6coK2Svfll0sGkicwsMTJNg+4YICY973WWj+R33euM70AKQzfcp0/V1@vger.kernel.org, AJvYcCVc5pZi806UtHjvlMnfHe40Z7uKd1xmctgtnzt2D+WLq+SwvWK/6oszc+JenrRofSkhXHsfpJZxLs4EH1vcydQ=@vger.kernel.org, AJvYcCWsqILzJEzINNlDmhs0Aq3MhzVeWLH5rWYxnk0KGF/JyChx96jnGxq/Yii9DVjWkjP8eHHwiIqTC24SiIfn@vger.kernel.org, AJvYcCXXo92uxsTgjcdnFemtXsfxH7j+7mkqxztH70OsojV069D87V24ucp1vGxnpz6lRhXIzu0vca2OEE64@vger.kernel.org X-Gm-Message-State: AOJu0YwxiHAUK3xS22ULg7/E9lkrTTa2vV298iTsLLcofSWD8iuHlMd5 8F8lQlg6t8YpSkCqps/OkUPUl+4xfg4jEkePdTegkvI9nkHNO1GcoGaN X-Gm-Gg: ASbGncscUwvewok3o9QBoUm6bgvMF6TZAJXQ2b6AsUKBP64s9uZtAi8VW45HbUI4NS7 tGFS9rl7kdO8Acl+ScUXJWDFNzuxtDMAC56FcuBb8WULIkjWYSu4l2mXX8WnVZ9DQBSgOLACsMx 035ar2sAVjH19aekKFr93GlMTpsij5AbQcMqm696wh0bd5fz+cTVDODHM8d6AErnXiCsMrbNDMT TV/FQVfrijXADVMSxn8SYyAdNufDqC0Qc4LoQ/JOsmOlpcKZSSS44meoUcp//pD9ImcLaQHgUZf YC4XvUfCHZrvx9+n+ILTt71evwvV4d9ycOBaNPqq1M9PL1UfWivRGXhZKp8B+4da9r09fWGr+M2 Bdw6jQGBVgacZ8frDi2gx X-Google-Smtp-Source: AGHT+IH0ZGWnW1K3Jp3p4o3BJE8BsjzlmsMNkZXGB5yNqvSvLbdgA7SMzMBdF7N3MFqmjTATY5rLmg== X-Received: by 2002:a05:6000:2210:b0:3a1:fc91:2819 with SMTP id ffacd0b85a97d-3a35c825f62mr6793668f8f.32.1747512869146; Sat, 17 May 2025 13:14:29 -0700 (PDT) Received: from localhost.localdomain (93-34-88-225.ip49.fastwebnet.it. [93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-442fd4fdcccsm85345445e9.6.2025.05.17.13.14.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 May 2025 13:14:28 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , =?UTF-8?q?Marek=20Beh=C3=BAn?= , Andrei Botila , FUJITA Tomonori , Trevor Gross , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Danilo Krummrich , Sabrina Dubroca , Michael Klein , Daniel Golle , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org Cc: "Russell King (Oracle)" Subject: [net-next PATCH v12 2/6] net: phy: bcm87xx: simplify .match_phy_device OP Date: Sat, 17 May 2025 22:13:46 +0200 Message-ID: <20250517201353.5137-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250517201353.5137-1-ansuelsmth@gmail.com> References: <20250517201353.5137-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Simplify .match_phy_device OP by using a generic function and using the new phy_id PHY driver info instead of hardcoding the matching PHY ID. Reviewed-by: Russell King (Oracle) Signed-off-by: Christian Marangi --- drivers/net/phy/bcm87xx.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/drivers/net/phy/bcm87xx.c b/drivers/net/phy/bcm87xx.c index 1e1e2259fc2b..299f9a8f30f4 100644 --- a/drivers/net/phy/bcm87xx.c +++ b/drivers/net/phy/bcm87xx.c @@ -185,16 +185,10 @@ static irqreturn_t bcm87xx_handle_interrupt(struct ph= y_device *phydev) return IRQ_HANDLED; } =20 -static int bcm8706_match_phy_device(struct phy_device *phydev, +static int bcm87xx_match_phy_device(struct phy_device *phydev, const struct phy_driver *phydrv) { - return phydev->c45_ids.device_ids[4] =3D=3D PHY_ID_BCM8706; -} - -static int bcm8727_match_phy_device(struct phy_device *phydev, - const struct phy_driver *phydrv) -{ - return phydev->c45_ids.device_ids[4] =3D=3D PHY_ID_BCM8727; + return phydev->c45_ids.device_ids[4] =3D=3D phydrv->phy_id; } =20 static struct phy_driver bcm87xx_driver[] =3D { @@ -208,7 +202,7 @@ static struct phy_driver bcm87xx_driver[] =3D { .read_status =3D bcm87xx_read_status, .config_intr =3D bcm87xx_config_intr, .handle_interrupt =3D bcm87xx_handle_interrupt, - .match_phy_device =3D bcm8706_match_phy_device, + .match_phy_device =3D bcm87xx_match_phy_device, }, { .phy_id =3D PHY_ID_BCM8727, .phy_id_mask =3D 0xffffffff, @@ -219,7 +213,7 @@ static struct phy_driver bcm87xx_driver[] =3D { .read_status =3D bcm87xx_read_status, .config_intr =3D bcm87xx_config_intr, .handle_interrupt =3D bcm87xx_handle_interrupt, - .match_phy_device =3D bcm8727_match_phy_device, + .match_phy_device =3D bcm87xx_match_phy_device, } }; =20 module_phy_driver(bcm87xx_driver); --=20 2.48.1 From nobody Wed Dec 17 07:10:22 2025 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5857214A91; Sat, 17 May 2025 20:14:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747512874; cv=none; b=Jnp0MxkM44EL6BEP9dsr84YvXAlFFRiXulqYBV+ClC/m6zpdy1AfalgeTF6O147sWHLeDuS2MaEC+072fg730v5xG4XUzHNekrLCRuG0BjWhz/f9Ja3teZKyUkanJkz7dmfWTSSk+5l8JyyUHJ4SWR+PrnEJazXY0a85bbc+tpY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747512874; c=relaxed/simple; bh=JMeorUGvSZqGdgT8eqo1GtEKe7cqqq8Xmt0oOBKX1/Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lPLgjDg+cBdBdmzWJnoimGxMIa5CyawqI+9X/7j1FM7S6H619R7ufKERrl/JG5NWGzsFgcCVi7KB+IuhVcWXcf87OPVoOR71fKqWfz2gBKbPQ4bDkfAZlZCR4rrPnKUuCMKAk/iLQVQxQi6YmwP2+Ljqs5lnuwnV0qGXTElo1eo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=PPJ+DtGe; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="PPJ+DtGe" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-442ea95f738so24100965e9.3; Sat, 17 May 2025 13:14:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1747512871; x=1748117671; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lTQhXTyWA+dzynRUt+APtRqGDF+FBiwvMZ8BjXEGJS4=; b=PPJ+DtGe77/Tmia2bLr/5n6OwgWqlWFvIu+Wl64sGMysYN58YYlFBknblBU99hx3UY F99cNz5bAXGH7FYU8f2rx+o7gPH82zgw5rmM+aN8JZR+wS/hCWZHFX6NE8DS7I9P+vju R1eyorVWdAOEw0AFtx8zXqfS0gJQAfV9eusFwY0qEJSzK/IWF9wIL/43thpots8VcdV3 h0gVt5MNPKwvCbXURTJ3AMa3rDj59QaOSAFvqiETQS5zpJ3eEmatFKcsfq6vZBoDuP+o Xi4hEhnSGf80x1Qgv9r7DTaObrFxsWWWaAFVX3SL2ojzqhXJ2mIvqO+9o34bwm9wVdtt sQSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747512871; x=1748117671; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lTQhXTyWA+dzynRUt+APtRqGDF+FBiwvMZ8BjXEGJS4=; b=F1RZjs6ZTQfz3kN6W17S3ghC+VMIEnbzkIbMWvvIJln7S5RH/+unMF7UubmZJ0xSrv 6DCnl1u6G8cJwRD64D+CUIk49wEYhFEIywf/SSMVLK9XaJ0LCkf43fgIjA+85katWaUE SrlOFgQ1F5+K7M1oTVb18Sku0CFurCdmh1PO7LCLsCid6ctGN1mAF5tb0+iGbmeEk0Qw Sfi8Y69y6K9Pgoujvi1b36eoz4rXyI5dbgRGpezjJMI2kGD9rvt7qU+QFgluG9ZBANir jJQpsK2rIxBNkZvJ8gDq6Pfcz2jTIHMLsfEYKiLqbYx0YTrYLHiO7I6RbNFLmIFG6xxt f1ww== X-Forwarded-Encrypted: i=1; AJvYcCUUiMhkvl9IVYmPJ+QPPl7uzZR5oZgfP6qmnFU8SJOt0qvRgDvCqQZJ1t1s3gTJzw1f0ZjtE5uA@vger.kernel.org, AJvYcCWGJwzSTrOEz2HmKWy+y2E1ts0eqKzS/uptHA5+NDKJeXPqN72sRId3rYK9Xozguur9AWn8opKdgzU6@vger.kernel.org, AJvYcCXA1Q+/ji6nJOnMjlJdR0769UyOb2bTmYqtEV2RukA+sGOd9WTFMA45Rgup1W6Ep4iZiSirUKWX4bwtx1wm6YU=@vger.kernel.org, AJvYcCXabSZDBymlTGF7om3lbDF6WuN6MFiLfi/2til+mUGO6u/+hdUgvLIW5RAk0CSE4UrsXZY6EqcpcjnVKVjX@vger.kernel.org X-Gm-Message-State: AOJu0YyeVYValHm+UDekszzNafE1vGJRdla9y2dW7IXBBQAz7lm1tykM cbrPMbM3t1NwVzQwJlfanD8RNKwsR5qHY71xyeWOhSKHYV6gEPRBRwOm X-Gm-Gg: ASbGncunxC4nhVvUuqxTTlDxvAznFxbVo9MlYHpZzTftMU/tc5y/Z4K25svhdtuaLGx mLdQenObjY7fFs0j8ezuBWZtlTsiOxMZkuYl8dqMD48KdrP3GVERRKXPZpe6a6EvZ0SwME8/bna AXz8/sI6A4tNq75nujsac9ekAJcoKCuexJxag33BHFyShUT90FFigh4HvA3D2ld9bk4phuO24MR IGU4x6023zirko1R7fFHq3YWl26FIi6Q80au8b/NE/bcUOhKb5+KidPu1rrQjLSnp6Fd5foirVk ESarZ/FYD/36fH36PgkFf1/aNGvVxn9Pdi0DWVQ/Xg8p0VA0d7x1zMQPflZnVuLrxKIOKrTSTru rGzTc/x9MLhq2Yx8OKirmO0z7oWhDLVk= X-Google-Smtp-Source: AGHT+IF17AQpViVU083IJgM6t4NsFN1G06ba3Grx4g16s1dBnHhgUvn539UfEByy/q2BHmHqoRQU9A== X-Received: by 2002:a05:600c:1c14:b0:441:c1ea:ac35 with SMTP id 5b1f17b1804b1-442fd64df64mr62100625e9.18.1747512870885; Sat, 17 May 2025 13:14:30 -0700 (PDT) Received: from localhost.localdomain (93-34-88-225.ip49.fastwebnet.it. [93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-442fd4fdcccsm85345445e9.6.2025.05.17.13.14.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 May 2025 13:14:30 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , =?UTF-8?q?Marek=20Beh=C3=BAn?= , Andrei Botila , FUJITA Tomonori , Trevor Gross , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Danilo Krummrich , Sabrina Dubroca , Michael Klein , Daniel Golle , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org Cc: "Russell King (Oracle)" Subject: [net-next PATCH v12 3/6] net: phy: nxp-c45-tja11xx: simplify .match_phy_device OP Date: Sat, 17 May 2025 22:13:47 +0200 Message-ID: <20250517201353.5137-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250517201353.5137-1-ansuelsmth@gmail.com> References: <20250517201353.5137-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Simplify .match_phy_device OP by using a generic function and using the new phy_id PHY driver info instead of hardcoding the matching PHY ID with new variant for macsec and no_macsec PHYs. Also make use of PHY_ID_MATCH_MODEL macro and drop PHY_ID_MASK define to introduce phy_id and phy_id_mask again in phy_driver struct. Reviewed-by: Russell King (Oracle) Signed-off-by: Christian Marangi --- drivers/net/phy/nxp-c45-tja11xx.c | 45 ++++++++++++++----------------- 1 file changed, 20 insertions(+), 25 deletions(-) diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tj= a11xx.c index 22921b192a8b..4c6d905f0a9f 100644 --- a/drivers/net/phy/nxp-c45-tja11xx.c +++ b/drivers/net/phy/nxp-c45-tja11xx.c @@ -19,7 +19,6 @@ =20 #include "nxp-c45-tja11xx.h" =20 -#define PHY_ID_MASK GENMASK(31, 4) /* Same id: TJA1103, TJA1104 */ #define PHY_ID_TJA_1103 0x001BB010 /* Same id: TJA1120, TJA1121 */ @@ -1966,32 +1965,24 @@ static int nxp_c45_macsec_ability(struct phy_device= *phydev) return macsec_ability; } =20 -static int tja1103_match_phy_device(struct phy_device *phydev, - const struct phy_driver *phydrv) +static int tja11xx_no_macsec_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { - return phy_id_compare(phydev->phy_id, PHY_ID_TJA_1103, PHY_ID_MASK) && - !nxp_c45_macsec_ability(phydev); -} + if (!phy_id_compare(phydev->phy_id, phydrv->phy_id, + phydrv->phy_id_mask)) + return 0; =20 -static int tja1104_match_phy_device(struct phy_device *phydev, - const struct phy_driver *phydrv) -{ - return phy_id_compare(phydev->phy_id, PHY_ID_TJA_1103, PHY_ID_MASK) && - nxp_c45_macsec_ability(phydev); + return !nxp_c45_macsec_ability(phydev); } =20 -static int tja1120_match_phy_device(struct phy_device *phydev, - const struct phy_driver *phydrv) +static int tja11xx_macsec_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { - return phy_id_compare(phydev->phy_id, PHY_ID_TJA_1120, PHY_ID_MASK) && - !nxp_c45_macsec_ability(phydev); -} + if (!phy_id_compare(phydev->phy_id, phydrv->phy_id, + phydrv->phy_id_mask)) + return 0; =20 -static int tja1121_match_phy_device(struct phy_device *phydev, - const struct phy_driver *phydrv) -{ - return phy_id_compare(phydev->phy_id, PHY_ID_TJA_1120, PHY_ID_MASK) && - nxp_c45_macsec_ability(phydev); + return nxp_c45_macsec_ability(phydev); } =20 static const struct nxp_c45_regmap tja1120_regmap =3D { @@ -2064,6 +2055,7 @@ static const struct nxp_c45_phy_data tja1120_phy_data= =3D { =20 static struct phy_driver nxp_c45_driver[] =3D { { + PHY_ID_MATCH_MODEL(PHY_ID_TJA_1103), .name =3D "NXP C45 TJA1103", .get_features =3D nxp_c45_get_features, .driver_data =3D &tja1103_phy_data, @@ -2085,9 +2077,10 @@ static struct phy_driver nxp_c45_driver[] =3D { .get_sqi =3D nxp_c45_get_sqi, .get_sqi_max =3D nxp_c45_get_sqi_max, .remove =3D nxp_c45_remove, - .match_phy_device =3D tja1103_match_phy_device, + .match_phy_device =3D tja11xx_no_macsec_match_phy_device, }, { + PHY_ID_MATCH_MODEL(PHY_ID_TJA_1103), .name =3D "NXP C45 TJA1104", .get_features =3D nxp_c45_get_features, .driver_data =3D &tja1103_phy_data, @@ -2109,9 +2102,10 @@ static struct phy_driver nxp_c45_driver[] =3D { .get_sqi =3D nxp_c45_get_sqi, .get_sqi_max =3D nxp_c45_get_sqi_max, .remove =3D nxp_c45_remove, - .match_phy_device =3D tja1104_match_phy_device, + .match_phy_device =3D tja11xx_macsec_match_phy_device, }, { + PHY_ID_MATCH_MODEL(PHY_ID_TJA_1120), .name =3D "NXP C45 TJA1120", .get_features =3D nxp_c45_get_features, .driver_data =3D &tja1120_phy_data, @@ -2134,9 +2128,10 @@ static struct phy_driver nxp_c45_driver[] =3D { .get_sqi =3D nxp_c45_get_sqi, .get_sqi_max =3D nxp_c45_get_sqi_max, .remove =3D nxp_c45_remove, - .match_phy_device =3D tja1120_match_phy_device, + .match_phy_device =3D tja11xx_no_macsec_match_phy_device, }, { + PHY_ID_MATCH_MODEL(PHY_ID_TJA_1120), .name =3D "NXP C45 TJA1121", .get_features =3D nxp_c45_get_features, .driver_data =3D &tja1120_phy_data, @@ -2159,7 +2154,7 @@ static struct phy_driver nxp_c45_driver[] =3D { .get_sqi =3D nxp_c45_get_sqi, .get_sqi_max =3D nxp_c45_get_sqi_max, .remove =3D nxp_c45_remove, - .match_phy_device =3D tja1121_match_phy_device, + .match_phy_device =3D tja11xx_macsec_match_phy_device, }, }; =20 --=20 2.48.1 From nobody Wed Dec 17 07:10:22 2025 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DED4C21883E; Sat, 17 May 2025 20:14:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747512877; cv=none; b=GEYdFvPSJqLH/bxw7X+dj6XyAGEmOEyTsX2PQmgulz/87RMt9GwE5cituIiXj2XaDQKQHxd1kSUdoVTZyp1BFUhl7l5ViOjRG4z0Rtm+6pVm8ftqpRavy/SZCyBIgJ2QuNnwQ6+v+TRaCxsFupnlv7M7txUhpwj87QfEFTpr13Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747512877; c=relaxed/simple; bh=AXCBl/5hZD5LUHlzciawMj8Ax7ubKl91r7de/X5+Tbc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=stUImFV/DwPg88KqMzQAjzQTn2F5teNNvvE1foQuRdqRXfYJa2XJtBJA/5hIn/GsEXSjsgI4R2sDcEMFXHSSmknq53D1Cqj5sgZoLFKaipCpo8LjP0mdhbVgRNrLXmBzeGr4qyW2GdL8DleSdDiCQmZhVjOOffyNDMIzlrn3vl0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=K4i4v5ba; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="K4i4v5ba" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-43d0618746bso24747865e9.2; Sat, 17 May 2025 13:14:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1747512874; x=1748117674; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=P0UbM3f3aiE6Xk9v2x1ninQEe7kuXc+YrE+ZJvHjaik=; b=K4i4v5ban/EHpXlXQHyqeUr/dNofr34stnzu34s++ybRPdooue9slBtys3KQo5D4Gx NstzWJ7pAw7KxiWX+JFCkCiKPScwhVQUUkJ4xNWuSZ+9kvM6SOZhgSR3EIgBG2etKbsb LenT9+VCPkXQvTJ8ZcWSHbiBqwkERfzOgq/xph6usHUy/0UBkf8te0+VrXy/JAMUyMKI HLsFp71Yt4cfRkIiscvzxNauDKJCoj7bZm5z3JZTBbb4HGitirhI5NmpRX0ORE4fLdPU L9QtYm3jRhJKpQ3lvLCyy6waQ8ctNtbRbdfnd8GPdT0WPDPamHzlkpFJdvzw8FmSGTl0 hkHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747512874; x=1748117674; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=P0UbM3f3aiE6Xk9v2x1ninQEe7kuXc+YrE+ZJvHjaik=; b=jxxQ6LCrjwaBIT55SOzYH2KKBcLo/5WFpMg980gWQiOcla2kHhBT+aqKVmVRQs/7uk fMwy6NZ0sXC1sOImMyCCbQ+IZYVGPLddj6n1jAI1zrAmv8yWSfK3HvH2/kKGoASy8aEl RwUZBM4muh02/n7M5uRCNDJy//qKCwq67JTuvO3dlgVd0omPBQiFiWo72LO81mkJdk9T sowNkk5XQmGUKSUok1LbN/UmI2t+a/jK/BVqGQzuatwPsHNtBQlrVH5kIJ/xXVw8jyXQ cJkJtVFQiuxdmbelumFUGlcUZ1J4FAKPDwC8CgXF5zi7fm7qfX9KZkSiuNNcGfu3ytw0 IhJA== X-Forwarded-Encrypted: i=1; AJvYcCU5H2L+gZnDpSPLtAlfq3wAcMjHfHnaX0Hr3ydeQKqZGrer5Bpt9pk155HGQBI+96UyLGq/1cQQwqJ9@vger.kernel.org, AJvYcCVNsX8NgEZb+T6GjePJW/CuIwXPYDB6DHiz+pkbfJPN5nwVnn1nIU2uq9407HBdiskpyxUNA1ED@vger.kernel.org, AJvYcCWrYjxv6lJu+X8orlClsuFqQN1eFEfjEUnuN0xVjmilLuPuVnh65A8w92kUCbtAzVW6fV2CrqRq1Fc3NoK6mBA=@vger.kernel.org, AJvYcCXU98fCt8pcF7wgAtglQBsV2B+gGE+GJgIGgl7b/EaFjEXCH/Bkq/9xwL6M++PQdaUHvKYmQOYHcYVQLD+y@vger.kernel.org X-Gm-Message-State: AOJu0Yzf9vH9YDpILZ6UWGYpWy8dHnH1EF8IqnFjkKJruvg5j5yTFfQa IAEtZz74V9xkvVG53qW5mXAc93Xphc7Os8A3qDN4FlEi3CDgIVe6m5be X-Gm-Gg: ASbGncs+nGW3RrlEkyD4pc6HDb6x+090dt/Z4orUc8YBOJJethoi1BdHGQyLPYex3n+ iGSmJGQr074XXBEL/jE0CN3BUq7InxD3QZKrap/PVaT7lJSsvSbHosoZvYmPYR89GJHNyIgBDDs YfZNqK33xcjWCCPtylwqaBYjdgDcQZcBlbY9Lb+az9sQn8qCHfVafhFXq+8OljYUW6ORWGo5zqk C9U4ESEnaY05tA+r3obunJz0ZwAo3ozSzulUerPp6F1nB5d8gl5WRf2S3PqtWDn8d28edm0qvcd nYwHIm+4iqIlc5rtT7IT8x4EAnctHVZY27doS8EURSCO2n/JjKp4HIgRkHrnMkR2SUWXpdPzzyt Lqr2M2zkiubH9dZbiY2cm X-Google-Smtp-Source: AGHT+IF/u43nVQvGCM1qDWWYaeuX2cnIjZovEACph2cRwcJkpi89NPYD58MOwCg3h//iJvhO/C4amA== X-Received: by 2002:a05:600c:c8c:b0:442:f4a3:b5ec with SMTP id 5b1f17b1804b1-442fefd5f8dmr76418235e9.4.1747512873836; Sat, 17 May 2025 13:14:33 -0700 (PDT) Received: from localhost.localdomain (93-34-88-225.ip49.fastwebnet.it. [93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-442fd4fdcccsm85345445e9.6.2025.05.17.13.14.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 May 2025 13:14:33 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , =?UTF-8?q?Marek=20Beh=C3=BAn?= , Andrei Botila , FUJITA Tomonori , Trevor Gross , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Danilo Krummrich , Sabrina Dubroca , Michael Klein , Daniel Golle , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org Cc: "Russell King (Oracle)" Subject: [net-next PATCH v12 4/6] net: phy: introduce genphy_match_phy_device() Date: Sat, 17 May 2025 22:13:48 +0200 Message-ID: <20250517201353.5137-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250517201353.5137-1-ansuelsmth@gmail.com> References: <20250517201353.5137-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce new API, genphy_match_phy_device(), to provide a way to check to match a PHY driver for a PHY device based on the info stored in the PHY device struct. The function generalize the logic used in phy_bus_match() to check the PHY ID whether if C45 or C22 ID should be used for matching. This is useful for custom .match_phy_device function that wants to use the generic logic under some condition. (example a PHY is already setup and provide the correct PHY ID) Reviewed-by: Russell King (Oracle) Signed-off-by: Christian Marangi --- drivers/net/phy/phy_device.c | 52 +++++++++++++++++++++++++----------- include/linux/phy.h | 3 +++ 2 files changed, 40 insertions(+), 15 deletions(-) diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index 96a96c0334a7..9282de0d591e 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -543,20 +543,26 @@ static int phy_scan_fixups(struct phy_device *phydev) return 0; } =20 -static int phy_bus_match(struct device *dev, const struct device_driver *d= rv) +/** + * genphy_match_phy_device - match a PHY device with a PHY driver + * @phydev: target phy_device struct + * @phydrv: target phy_driver struct + * + * Description: Checks whether the given PHY device matches the specified + * PHY driver. For Clause 45 PHYs, iterates over the available device + * identifiers and compares them against the driver's expected PHY ID, + * applying the provided mask. For Clause 22 PHYs, a direct ID comparison + * is performed. + * + * Return: 1 if the PHY device matches the driver, 0 otherwise. + */ +int genphy_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) { - struct phy_device *phydev =3D to_phy_device(dev); - const struct phy_driver *phydrv =3D to_phy_driver(drv); - const int num_ids =3D ARRAY_SIZE(phydev->c45_ids.device_ids); - int i; - - if (!(phydrv->mdiodrv.flags & MDIO_DEVICE_IS_PHY)) - return 0; - - if (phydrv->match_phy_device) - return phydrv->match_phy_device(phydev, phydrv); - if (phydev->is_c45) { + const int num_ids =3D ARRAY_SIZE(phydev->c45_ids.device_ids); + int i; + for (i =3D 1; i < num_ids; i++) { if (phydev->c45_ids.device_ids[i] =3D=3D 0xffffffff) continue; @@ -565,11 +571,27 @@ static int phy_bus_match(struct device *dev, const st= ruct device_driver *drv) phydrv->phy_id, phydrv->phy_id_mask)) return 1; } + return 0; - } else { - return phy_id_compare(phydev->phy_id, phydrv->phy_id, - phydrv->phy_id_mask); } + + return phy_id_compare(phydev->phy_id, phydrv->phy_id, + phydrv->phy_id_mask); +} +EXPORT_SYMBOL_GPL(genphy_match_phy_device); + +static int phy_bus_match(struct device *dev, const struct device_driver *d= rv) +{ + struct phy_device *phydev =3D to_phy_device(dev); + const struct phy_driver *phydrv =3D to_phy_driver(drv); + + if (!(phydrv->mdiodrv.flags & MDIO_DEVICE_IS_PHY)) + return 0; + + if (phydrv->match_phy_device) + return phydrv->match_phy_device(phydev, phydrv); + + return genphy_match_phy_device(phydev, phydrv); } =20 static ssize_t diff --git a/include/linux/phy.h b/include/linux/phy.h index 34ed85686b83..48e80f089b17 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -1868,6 +1868,9 @@ char *phy_attached_info_irq(struct phy_device *phydev) __malloc; void phy_attached_info(struct phy_device *phydev); =20 +int genphy_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv); + /* Clause 22 PHY */ int genphy_read_abilities(struct phy_device *phydev); int genphy_setup_forced(struct phy_device *phydev); --=20 2.48.1 From nobody Wed Dec 17 07:10:22 2025 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3CCF214A6C; Sat, 17 May 2025 20:14:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747512880; cv=none; b=TPLGlDLg5HECH8FfDPK+bv6LdQTJJtOYCEdXRks+E4Us5eJ5HCYvwJPUDOrMVGSy9EooUG9TDonGm4ao7lNSlN7reHsjy//r8fj/hws6Ni8r9pimsyvp9c+6llSuUFNRGzKhisArSFNtEY8sJIujLsF83/UvABkajgttGTg8Zx8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747512880; c=relaxed/simple; bh=OBzxc+mG/tEmNZ/fzmLSoMU07kyddgcW7zxSSUf2vkc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jOgx/xzpPYFDBrZF9S65SZtqGW1vshkJQTeYmKPW0jv/jtMMMVHcvjzSmkS4liaD6kliA9r3ch7mZo8A1b7qikFKDiMdRF8qdserbSCPYuw6ZtOBlgQQjfwEuLInp5ZwdhtwzECau9sJv2otq/iyrDDQSY59TCLBD3FdUGtdFPk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=BHRgs49E; arc=none smtp.client-ip=209.85.128.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="BHRgs49E" Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-43cfdc2c8c9so17439405e9.2; Sat, 17 May 2025 13:14:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1747512876; x=1748117676; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6wqLNJlKKOMMcoR20VDwPRwuOIgWtkXz6yr4sqIanhY=; b=BHRgs49EbFS7veiHNdTusrMScY0W5jVZPUyuYZwOAWnvm1ECGZ21ytU9RXsovwi9G0 b1NgTe2+caMqcIVuGsQHSq4nMSEPRCbleQZpNLgTdnjIRSBMrlD170d7Wo3UYEK82ypu 7QxwCpIMSkFqrlp2FRVn2f/QX3gnMf8cf+A561Y3Fsy/DKmOuoJS3ln6U5SLbbeUqXOF TYtl8A4BbCOtew2hTXtNiKQwaYcWbyX5U8R/8zLeHuQaKdkM0D+7jvZ+HcHcUkdB0ry2 YHlObo3gZ+us8/EPYEqxWC5Xv5takG0SdocvhYgHse1ZrTAehehXtMbTDoMy5L0Npduc wCgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747512876; x=1748117676; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6wqLNJlKKOMMcoR20VDwPRwuOIgWtkXz6yr4sqIanhY=; b=R3f/Lrqg8ldAncxb4u0Bvt3rCzYNa6ZMoTWSYudYg43roXlIErbCW+EntaOo5u3dyd 9DohoSXvcY0rqHnFgtHLVLgEQGNfEIPXs4nScmbc1LcnSfms2JPpMxadYT9L/lbsjxmc 4tnAr0lCGbPK4f//6MU6WlmQI8JkpGsUxtHL4vYZTPxBGTQlsapRc26IZ+7dvsY7c2VS 7Bd2xO+jUOJoI1dgMzGqYyZHiScW13BBa+XHwogfIMozLTHOyB3ubWZKrNf191OT2tsU uF6bivLM9qyuL5bJOOptJGjYf3PABzTsfE0Uk10Jni+KJ3CJbCs+B9Jax+GWYI0dUI4a JvcA== X-Forwarded-Encrypted: i=1; AJvYcCUZsnPNJdhb/BTsFB5HFNEJqZ9gtdZM+/5qTnR5hqGqm2KptH+Gbn1gi4yJJogM6AVJWa/L4lzh@vger.kernel.org, AJvYcCWaI/Lz1prX7nvns5hiAAy3BSF/HvHxT3JGuuIefESaLXhTuaxjfCdduCVyswTOlz+L0ciylcL9tknc+ByF@vger.kernel.org, AJvYcCWhNAwGW7sp4xIWWxwSFwvP5MAZVK0mKGozY9iwxo8oJ3EARE6/F0hODrRvjDwrMaW5aPkB0YTMlSZ3OF69QBY=@vger.kernel.org, AJvYcCX84PwiPWek7pCuQFsBPzP7vVSGza7hcOsC09tOXIuDL9oexWbnFhHFyKcIAAl+d5u/vLSWGR/PXxzh@vger.kernel.org X-Gm-Message-State: AOJu0YyyDFP6qbhdWApcgqyNJULwWZsiGLQajSCCvhmYaH9AiSWCr3vW 6xo2LpTHHFaRNnJLG95lfJFrmtSL6T8rMbizp/RVk1KTXs0bPX4rEpKb X-Gm-Gg: ASbGncurXCd52Asc/bUx6zGjuCUFDTUkEl3bCvX5HVIhCP9T/GahO2u2CJ2C91C8ch/ QVhUS8B7O6SjsRyqGR8xB9EXSLcJWbEq+RX2DizxS4uREGGSL74cmANnFplyllyN0vd6dHeSfTj YAnuwxs7RZuygWOhjSfF/RlCsCXPDChmYTqm/EcLWzDE3wsfWbJZfiBWk4bJtHuAIOqs1HmP8kI Eu0ZeYJkVgbgjukF098AHon5PmGuz0kw7Q+Uc1y9akUe2F2qmhsgxzzquznXU6F6qKA1YPMlVH3 Ay7BjqPFW9snet6NM3rjVIYSn0COZVmaFhuZvrCTiTjNLahWzuyHjx1ha9CEJ0sQfTLZQ2a+SEU WN3jqv/yLRqsVKl9pvfEn X-Google-Smtp-Source: AGHT+IHS44MWQGGQH5DOC9OR8i7VZuNFtruHymSVUDkwoHbU8JE88geQFCfdf/K+q9U7g+SgmNCtow== X-Received: by 2002:a05:600c:4f42:b0:442:dc75:5625 with SMTP id 5b1f17b1804b1-442fd60cb7bmr72059955e9.5.1747512875778; Sat, 17 May 2025 13:14:35 -0700 (PDT) Received: from localhost.localdomain (93-34-88-225.ip49.fastwebnet.it. [93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-442fd4fdcccsm85345445e9.6.2025.05.17.13.14.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 May 2025 13:14:35 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , =?UTF-8?q?Marek=20Beh=C3=BAn?= , Andrei Botila , FUJITA Tomonori , Trevor Gross , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Danilo Krummrich , Sabrina Dubroca , Michael Klein , Daniel Golle , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org Cc: Andrew Lunn Subject: [net-next PATCH v12 5/6] net: phy: Add support for Aeonsemi AS21xxx PHYs Date: Sat, 17 May 2025 22:13:49 +0200 Message-ID: <20250517201353.5137-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250517201353.5137-1-ansuelsmth@gmail.com> References: <20250517201353.5137-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add support for Aeonsemi AS21xxx 10G C45 PHYs. These PHYs integrate an IPC to setup some configuration and require special handling to sync with the parity bit. The parity bit is a way the IPC use to follow correct order of command sent. Supported PHYs AS21011JB1, AS21011PB1, AS21010JB1, AS21010PB1, AS21511JB1, AS21511PB1, AS21510JB1, AS21510PB1, AS21210JB1, AS21210PB1 that all register with the PHY ID 0x7500 0x7510 before the firmware is loaded. They all support up to 5 LEDs with various HW mode supported. While implementing it was found some strange coincidence with using the same logic for implementing C22 in MMD regs in Broadcom PHYs. For reference here the AS21xxx PHY name logic: AS21x1xxB1 ^ ^^ | |J: Supports SyncE/PTP | |P: No SyncE/PTP support | 1: Supports 2nd Serdes | 2: Not 2nd Serdes support 0: 10G, 5G, 2.5G 5: 5G, 2.5G 2: 2.5G Reviewed-by: Andrew Lunn Signed-off-by: Christian Marangi --- MAINTAINERS | 6 + drivers/net/phy/Kconfig | 12 + drivers/net/phy/Makefile | 1 + drivers/net/phy/as21xxx.c | 1087 +++++++++++++++++++++++++++++++++++++ 4 files changed, 1106 insertions(+) create mode 100644 drivers/net/phy/as21xxx.c diff --git a/MAINTAINERS b/MAINTAINERS index 800d23264c94..6cc52e99c1f8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -646,6 +646,12 @@ F: drivers/iio/accel/adxl380.h F: drivers/iio/accel/adxl380_i2c.c F: drivers/iio/accel/adxl380_spi.c =20 +AEONSEMI PHY DRIVER +M: Christian Marangi +L: netdev@vger.kernel.org +S: Maintained +F: drivers/net/phy/as21xxx.c + AF8133J THREE-AXIS MAGNETOMETER DRIVER M: Ond=C5=99ej Jirman S: Maintained diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 677d56e06539..895f92ccfe1f 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -76,6 +76,18 @@ config SFP =20 comment "MII PHY device drivers" =20 +config AS21XXX_PHY + tristate "Aeonsemi AS21xxx PHYs" + help + Currently supports the Aeonsemi AS21xxx PHY. + + These are C45 PHYs 10G that require all a generic firmware. + + Supported PHYs AS21011JB1, AS21011PB1, AS21010JB1, AS21010PB1, + AS21511JB1, AS21511PB1, AS21510JB1, AS21510PB1, AS21210JB1, + AS21210PB1 that all register with the PHY ID 0x7500 0x7500 + before the firmware is loaded. + config AIR_EN8811H_PHY tristate "Airoha EN8811H 2.5 Gigabit PHY" help diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 59ac3a9a3177..42f215905a29 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_AIR_EN8811H_PHY) +=3D air_en8811h.o obj-$(CONFIG_AMD_PHY) +=3D amd.o obj-$(CONFIG_AMCC_QT2025_PHY) +=3D qt2025.o obj-$(CONFIG_AQUANTIA_PHY) +=3D aquantia/ +obj-$(CONFIG_AS21XXX_PHY) +=3D as21xxx.o ifdef CONFIG_AX88796B_RUST_PHY obj-$(CONFIG_AX88796B_PHY) +=3D ax88796b_rust.o else diff --git a/drivers/net/phy/as21xxx.c b/drivers/net/phy/as21xxx.c new file mode 100644 index 000000000000..92697f43087d --- /dev/null +++ b/drivers/net/phy/as21xxx.c @@ -0,0 +1,1087 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Aeonsemi AS21XXxX PHY Driver + * + * Author: Christian Marangi + */ + +#include +#include +#include +#include +#include + +#define VEND1_GLB_REG_CPU_RESET_ADDR_LO_BASEADDR 0x3 +#define VEND1_GLB_REG_CPU_RESET_ADDR_HI_BASEADDR 0x4 + +#define VEND1_GLB_REG_CPU_CTRL 0xe +#define VEND1_GLB_CPU_CTRL_MASK GENMASK(4, 0) +#define VEND1_GLB_CPU_CTRL_LED_POLARITY_MASK GENMASK(12, 8) +#define VEND1_GLB_CPU_CTRL_LED_POLARITY(_n) FIELD_PREP(VEND1_GLB_CPU_CTR= L_LED_POLARITY_MASK, \ + BIT(_n)) + +#define VEND1_FW_START_ADDR 0x100 + +#define VEND1_GLB_REG_MDIO_INDIRECT_ADDRCMD 0x101 +#define VEND1_GLB_REG_MDIO_INDIRECT_LOAD 0x102 + +#define VEND1_GLB_REG_MDIO_INDIRECT_STATUS 0x103 + +#define VEND1_PTP_CLK 0x142 +#define VEND1_PTP_CLK_EN BIT(6) + +/* 5 LED at step of 0x20 + * FE: Fast-Ethernet (10/100) + * GE: Gigabit-Ethernet (1000) + * NG: New-Generation (2500/5000/10000) + */ +#define VEND1_LED_REG(_n) (0x1800 + ((_n) * 0x10)) +#define VEND1_LED_REG_A_EVENT GENMASK(15, 11) +#define VEND1_LED_CONF 0x1881 +#define VEND1_LED_CONFG_BLINK GENMASK(7, 0) + +#define VEND1_SPEED_STATUS 0x4002 +#define VEND1_SPEED_MASK GENMASK(7, 0) +#define VEND1_SPEED_10000 FIELD_PREP_CONST(VEND1_SPEED_MASK, 0x3) +#define VEND1_SPEED_5000 FIELD_PREP_CONST(VEND1_SPEED_MASK, 0x5) +#define VEND1_SPEED_2500 FIELD_PREP_CONST(VEND1_SPEED_MASK, 0x9) +#define VEND1_SPEED_1000 FIELD_PREP_CONST(VEND1_SPEED_MASK, 0x10) +#define VEND1_SPEED_100 FIELD_PREP_CONST(VEND1_SPEED_MASK, 0x20) +#define VEND1_SPEED_10 FIELD_PREP_CONST(VEND1_SPEED_MASK, 0x0) + +#define VEND1_IPC_CMD 0x5801 +#define AEON_IPC_CMD_PARITY BIT(15) +#define AEON_IPC_CMD_SIZE GENMASK(10, 6) +#define AEON_IPC_CMD_OPCODE GENMASK(5, 0) + +#define IPC_CMD_NOOP 0x0 /* Do nothing */ +#define IPC_CMD_INFO 0x1 /* Get Firmware Version */ +#define IPC_CMD_SYS_CPU 0x2 /* SYS_CPU */ +#define IPC_CMD_BULK_DATA 0xa /* Pass bulk data in ipc registers. */ +#define IPC_CMD_BULK_WRITE 0xc /* Write bulk data to memory */ +#define IPC_CMD_CFG_PARAM 0x1a /* Write config parameters to memory */ +#define IPC_CMD_NG_TESTMODE 0x1b /* Set NG test mode and tone */ +#define IPC_CMD_TEMP_MON 0x15 /* Temperature monitoring function */ +#define IPC_CMD_SET_LED 0x23 /* Set led */ + +#define VEND1_IPC_STS 0x5802 +#define AEON_IPC_STS_PARITY BIT(15) +#define AEON_IPC_STS_SIZE GENMASK(14, 10) +#define AEON_IPC_STS_OPCODE GENMASK(9, 4) +#define AEON_IPC_STS_STATUS GENMASK(3, 0) +#define AEON_IPC_STS_STATUS_RCVD FIELD_PREP_CONST(AEON_IPC_STS_STATUS, 0= x1) +#define AEON_IPC_STS_STATUS_PROCESS FIELD_PREP_CONST(AEON_IPC_STS_STATUS= , 0x2) +#define AEON_IPC_STS_STATUS_SUCCESS FIELD_PREP_CONST(AEON_IPC_STS_STATUS= , 0x4) +#define AEON_IPC_STS_STATUS_ERROR FIELD_PREP_CONST(AEON_IPC_STS_STATUS, = 0x8) +#define AEON_IPC_STS_STATUS_BUSY FIELD_PREP_CONST(AEON_IPC_STS_STATUS, 0= xe) +#define AEON_IPC_STS_STATUS_READY FIELD_PREP_CONST(AEON_IPC_STS_STATUS, = 0xf) + +#define VEND1_IPC_DATA0 0x5808 +#define VEND1_IPC_DATA1 0x5809 +#define VEND1_IPC_DATA2 0x580a +#define VEND1_IPC_DATA3 0x580b +#define VEND1_IPC_DATA4 0x580c +#define VEND1_IPC_DATA5 0x580d +#define VEND1_IPC_DATA6 0x580e +#define VEND1_IPC_DATA7 0x580f +#define VEND1_IPC_DATA(_n) (VEND1_IPC_DATA0 + (_n)) + +/* Sub command of CMD_INFO */ +#define IPC_INFO_VERSION 0x1 + +/* Sub command of CMD_SYS_CPU */ +#define IPC_SYS_CPU_REBOOT 0x3 +#define IPC_SYS_CPU_IMAGE_OFST 0x4 +#define IPC_SYS_CPU_IMAGE_CHECK 0x5 +#define IPC_SYS_CPU_PHY_ENABLE 0x6 + +/* Sub command of CMD_CFG_PARAM */ +#define IPC_CFG_PARAM_DIRECT 0x4 + +/* CFG DIRECT sub command */ +#define IPC_CFG_PARAM_DIRECT_NG_PHYCTRL 0x1 +#define IPC_CFG_PARAM_DIRECT_CU_AN 0x2 +#define IPC_CFG_PARAM_DIRECT_SDS_PCS 0x3 +#define IPC_CFG_PARAM_DIRECT_AUTO_EEE 0x4 +#define IPC_CFG_PARAM_DIRECT_SDS_PMA 0x5 +#define IPC_CFG_PARAM_DIRECT_DPC_RA 0x6 +#define IPC_CFG_PARAM_DIRECT_DPC_PKT_CHK 0x7 +#define IPC_CFG_PARAM_DIRECT_DPC_SDS_WAIT_ETH 0x8 +#define IPC_CFG_PARAM_DIRECT_WDT 0x9 +#define IPC_CFG_PARAM_DIRECT_SDS_RESTART_AN 0x10 +#define IPC_CFG_PARAM_DIRECT_TEMP_MON 0x11 +#define IPC_CFG_PARAM_DIRECT_WOL 0x12 + +/* Sub command of CMD_TEMP_MON */ +#define IPC_CMD_TEMP_MON_GET 0x4 + +#define AS21XXX_MDIO_AN_C22 0xffe0 + +#define PHY_ID_AS21XXX 0x75009410 +/* AS21xxx ID Legend + * AS21x1xxB1 + * ^ ^^ + * | |J: Supports SyncE/PTP + * | |P: No SyncE/PTP support + * | 1: Supports 2nd Serdes + * | 2: Not 2nd Serdes support + * 0: 10G, 5G, 2.5G + * 5: 5G, 2.5G + * 2: 2.5G + */ +#define PHY_ID_AS21011JB1 0x75009402 +#define PHY_ID_AS21011PB1 0x75009412 +#define PHY_ID_AS21010JB1 0x75009422 +#define PHY_ID_AS21010PB1 0x75009432 +#define PHY_ID_AS21511JB1 0x75009442 +#define PHY_ID_AS21511PB1 0x75009452 +#define PHY_ID_AS21510JB1 0x75009462 +#define PHY_ID_AS21510PB1 0x75009472 +#define PHY_ID_AS21210JB1 0x75009482 +#define PHY_ID_AS21210PB1 0x75009492 +#define PHY_VENDOR_AEONSEMI 0x75009400 + +#define AEON_MAX_LEDS 5 +#define AEON_IPC_DELAY 10000 +#define AEON_IPC_TIMEOUT (AEON_IPC_DELAY * 100) +#define AEON_IPC_DATA_NUM_REGISTERS 8 +#define AEON_IPC_DATA_MAX (AEON_IPC_DATA_NUM_REGISTERS * sizeof(u16)) + +#define AEON_BOOT_ADDR 0x1000 +#define AEON_CPU_BOOT_ADDR 0x2000 +#define AEON_CPU_CTRL_FW_LOAD (BIT(4) | BIT(2) | BIT(1) | BIT(0)) +#define AEON_CPU_CTRL_FW_START BIT(0) + +enum as21xxx_led_event { + VEND1_LED_REG_A_EVENT_ON_10 =3D 0x0, + VEND1_LED_REG_A_EVENT_ON_100, + VEND1_LED_REG_A_EVENT_ON_1000, + VEND1_LED_REG_A_EVENT_ON_2500, + VEND1_LED_REG_A_EVENT_ON_5000, + VEND1_LED_REG_A_EVENT_ON_10000, + VEND1_LED_REG_A_EVENT_ON_FE_GE, + VEND1_LED_REG_A_EVENT_ON_NG, + VEND1_LED_REG_A_EVENT_ON_FULL_DUPLEX, + VEND1_LED_REG_A_EVENT_ON_COLLISION, + VEND1_LED_REG_A_EVENT_BLINK_TX, + VEND1_LED_REG_A_EVENT_BLINK_RX, + VEND1_LED_REG_A_EVENT_BLINK_ACT, + VEND1_LED_REG_A_EVENT_ON_LINK, + VEND1_LED_REG_A_EVENT_ON_LINK_BLINK_ACT, + VEND1_LED_REG_A_EVENT_ON_LINK_BLINK_RX, + VEND1_LED_REG_A_EVENT_ON_FE_GE_BLINK_ACT, + VEND1_LED_REG_A_EVENT_ON_NG_BLINK_ACT, + VEND1_LED_REG_A_EVENT_ON_NG_BLINK_FE_GE, + VEND1_LED_REG_A_EVENT_ON_FD_BLINK_COLLISION, + VEND1_LED_REG_A_EVENT_ON, + VEND1_LED_REG_A_EVENT_OFF, +}; + +struct as21xxx_led_pattern_info { + unsigned int pattern; + u16 val; +}; + +struct as21xxx_priv { + bool parity_status; + /* Protect concurrent IPC access */ + struct mutex ipc_lock; +}; + +static struct as21xxx_led_pattern_info as21xxx_led_supported_pattern[] =3D= { + { + .pattern =3D BIT(TRIGGER_NETDEV_LINK_10), + .val =3D VEND1_LED_REG_A_EVENT_ON_10 + }, + { + .pattern =3D BIT(TRIGGER_NETDEV_LINK_100), + .val =3D VEND1_LED_REG_A_EVENT_ON_100 + }, + { + .pattern =3D BIT(TRIGGER_NETDEV_LINK_1000), + .val =3D VEND1_LED_REG_A_EVENT_ON_1000 + }, + { + .pattern =3D BIT(TRIGGER_NETDEV_LINK_2500), + .val =3D VEND1_LED_REG_A_EVENT_ON_2500 + }, + { + .pattern =3D BIT(TRIGGER_NETDEV_LINK_5000), + .val =3D VEND1_LED_REG_A_EVENT_ON_5000 + }, + { + .pattern =3D BIT(TRIGGER_NETDEV_LINK_10000), + .val =3D VEND1_LED_REG_A_EVENT_ON_10000 + }, + { + .pattern =3D BIT(TRIGGER_NETDEV_LINK), + .val =3D VEND1_LED_REG_A_EVENT_ON_LINK + }, + { + .pattern =3D BIT(TRIGGER_NETDEV_LINK_10) | + BIT(TRIGGER_NETDEV_LINK_100) | + BIT(TRIGGER_NETDEV_LINK_1000), + .val =3D VEND1_LED_REG_A_EVENT_ON_FE_GE + }, + { + .pattern =3D BIT(TRIGGER_NETDEV_LINK_2500) | + BIT(TRIGGER_NETDEV_LINK_5000) | + BIT(TRIGGER_NETDEV_LINK_10000), + .val =3D VEND1_LED_REG_A_EVENT_ON_NG + }, + { + .pattern =3D BIT(TRIGGER_NETDEV_FULL_DUPLEX), + .val =3D VEND1_LED_REG_A_EVENT_ON_FULL_DUPLEX + }, + { + .pattern =3D BIT(TRIGGER_NETDEV_TX), + .val =3D VEND1_LED_REG_A_EVENT_BLINK_TX + }, + { + .pattern =3D BIT(TRIGGER_NETDEV_RX), + .val =3D VEND1_LED_REG_A_EVENT_BLINK_RX + }, + { + .pattern =3D BIT(TRIGGER_NETDEV_TX) | + BIT(TRIGGER_NETDEV_RX), + .val =3D VEND1_LED_REG_A_EVENT_BLINK_ACT + }, + { + .pattern =3D BIT(TRIGGER_NETDEV_LINK_10) | + BIT(TRIGGER_NETDEV_LINK_100) | + BIT(TRIGGER_NETDEV_LINK_1000) | + BIT(TRIGGER_NETDEV_LINK_2500) | + BIT(TRIGGER_NETDEV_LINK_5000) | + BIT(TRIGGER_NETDEV_LINK_10000), + .val =3D VEND1_LED_REG_A_EVENT_ON_LINK + }, + { + .pattern =3D BIT(TRIGGER_NETDEV_LINK_10) | + BIT(TRIGGER_NETDEV_LINK_100) | + BIT(TRIGGER_NETDEV_LINK_1000) | + BIT(TRIGGER_NETDEV_LINK_2500) | + BIT(TRIGGER_NETDEV_LINK_5000) | + BIT(TRIGGER_NETDEV_LINK_10000) | + BIT(TRIGGER_NETDEV_TX) | + BIT(TRIGGER_NETDEV_RX), + .val =3D VEND1_LED_REG_A_EVENT_ON_LINK_BLINK_ACT + }, + { + .pattern =3D BIT(TRIGGER_NETDEV_LINK_10) | + BIT(TRIGGER_NETDEV_LINK_100) | + BIT(TRIGGER_NETDEV_LINK_1000) | + BIT(TRIGGER_NETDEV_LINK_2500) | + BIT(TRIGGER_NETDEV_LINK_5000) | + BIT(TRIGGER_NETDEV_LINK_10000) | + BIT(TRIGGER_NETDEV_RX), + .val =3D VEND1_LED_REG_A_EVENT_ON_LINK_BLINK_RX + }, + { + .pattern =3D BIT(TRIGGER_NETDEV_LINK_10) | + BIT(TRIGGER_NETDEV_LINK_100) | + BIT(TRIGGER_NETDEV_LINK_1000) | + BIT(TRIGGER_NETDEV_TX) | + BIT(TRIGGER_NETDEV_RX), + .val =3D VEND1_LED_REG_A_EVENT_ON_FE_GE_BLINK_ACT + }, + { + .pattern =3D BIT(TRIGGER_NETDEV_LINK_2500) | + BIT(TRIGGER_NETDEV_LINK_5000) | + BIT(TRIGGER_NETDEV_LINK_10000) | + BIT(TRIGGER_NETDEV_TX) | + BIT(TRIGGER_NETDEV_RX), + .val =3D VEND1_LED_REG_A_EVENT_ON_NG_BLINK_ACT + } +}; + +static int aeon_firmware_boot(struct phy_device *phydev, const u8 *data, + size_t size) +{ + int i, ret; + u16 val; + + ret =3D phy_modify_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLB_REG_CPU_CTRL, + VEND1_GLB_CPU_CTRL_MASK, AEON_CPU_CTRL_FW_LOAD); + if (ret) + return ret; + + ret =3D phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_FW_START_ADDR, + AEON_BOOT_ADDR); + if (ret) + return ret; + + ret =3D phy_modify_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLB_REG_MDIO_INDIRECT_ADDRCMD, + 0x3ffc, 0xc000); + if (ret) + return ret; + + val =3D phy_read_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLB_REG_MDIO_INDIRECT_STATUS); + if (val > 1) { + phydev_err(phydev, "wrong origin mdio_indirect_status: %x\n", val); + return -EINVAL; + } + + /* Firmware is always aligned to u16 */ + for (i =3D 0; i < size; i +=3D 2) { + val =3D data[i + 1] << 8 | data[i]; + + ret =3D phy_write_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLB_REG_MDIO_INDIRECT_LOAD, val); + if (ret) + return ret; + } + + ret =3D phy_write_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLB_REG_CPU_RESET_ADDR_LO_BASEADDR, + lower_16_bits(AEON_CPU_BOOT_ADDR)); + if (ret) + return ret; + + ret =3D phy_write_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLB_REG_CPU_RESET_ADDR_HI_BASEADDR, + upper_16_bits(AEON_CPU_BOOT_ADDR)); + if (ret) + return ret; + + return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLB_REG_CPU_CTRL, + VEND1_GLB_CPU_CTRL_MASK, AEON_CPU_CTRL_FW_START); +} + +static int aeon_firmware_load(struct phy_device *phydev) +{ + struct device *dev =3D &phydev->mdio.dev; + const struct firmware *fw; + const char *fw_name; + int ret; + + ret =3D of_property_read_string(dev->of_node, "firmware-name", + &fw_name); + if (ret) + return ret; + + ret =3D request_firmware(&fw, fw_name, dev); + if (ret) { + phydev_err(phydev, "failed to find FW file %s (%d)\n", + fw_name, ret); + return ret; + } + + ret =3D aeon_firmware_boot(phydev, fw->data, fw->size); + + release_firmware(fw); + + return ret; +} + +static bool aeon_ipc_ready(u16 val, bool parity_status) +{ + u16 status; + + if (FIELD_GET(AEON_IPC_STS_PARITY, val) !=3D parity_status) + return false; + + status =3D val & AEON_IPC_STS_STATUS; + + return status !=3D AEON_IPC_STS_STATUS_RCVD && + status !=3D AEON_IPC_STS_STATUS_PROCESS && + status !=3D AEON_IPC_STS_STATUS_BUSY; +} + +static int aeon_ipc_wait_cmd(struct phy_device *phydev, bool parity_status) +{ + u16 val; + + /* Exit condition logic: + * - Wait for parity bit equal + * - Wait for status success, error OR ready + */ + return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, VEND1_IPC_STS, v= al, + aeon_ipc_ready(val, parity_status), + AEON_IPC_DELAY, AEON_IPC_TIMEOUT, false); +} + +static int aeon_ipc_send_cmd(struct phy_device *phydev, + struct as21xxx_priv *priv, + u16 cmd, u16 *ret_sts) +{ + bool curr_parity; + int ret; + + /* The IPC sync by using a single parity bit. + * Each CMD have alternately this bit set or clear + * to understand correct flow and packet order. + */ + curr_parity =3D priv->parity_status; + if (priv->parity_status) + cmd |=3D AEON_IPC_CMD_PARITY; + + /* Always update parity for next packet */ + priv->parity_status =3D !priv->parity_status; + + ret =3D phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_IPC_CMD, cmd); + if (ret) + return ret; + + /* Wait for packet to be processed */ + usleep_range(AEON_IPC_DELAY, AEON_IPC_DELAY + 5000); + + /* With no ret_sts, ignore waiting for packet completion + * (ipc parity bit sync) + */ + if (!ret_sts) + return 0; + + ret =3D aeon_ipc_wait_cmd(phydev, curr_parity); + if (ret) + return ret; + + ret =3D phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_IPC_STS); + if (ret < 0) + return ret; + + *ret_sts =3D ret; + if ((*ret_sts & AEON_IPC_STS_STATUS) !=3D AEON_IPC_STS_STATUS_SUCCESS) + return -EINVAL; + + return 0; +} + +/* If data is NULL, return 0 or negative error. + * If data not NULL, return number of Bytes received from IPC or + * a negative error. + */ +static int aeon_ipc_send_msg(struct phy_device *phydev, + u16 opcode, u16 *data, unsigned int data_len, + u16 *ret_data) +{ + struct as21xxx_priv *priv =3D phydev->priv; + unsigned int ret_size; + u16 cmd, ret_sts; + int ret; + int i; + + /* IPC have a max of 8 register to transfer data, + * make sure we never exceed this. + */ + if (data_len > AEON_IPC_DATA_MAX) + return -EINVAL; + + for (i =3D 0; i < data_len / sizeof(u16); i++) + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_IPC_DATA(i), + data[i]); + + cmd =3D FIELD_PREP(AEON_IPC_CMD_SIZE, data_len) | + FIELD_PREP(AEON_IPC_CMD_OPCODE, opcode); + + mutex_lock(&priv->ipc_lock); + + ret =3D aeon_ipc_send_cmd(phydev, priv, cmd, &ret_sts); + if (ret) { + phydev_err(phydev, "failed to send ipc msg for %x: %d\n", + opcode, ret); + goto out; + } + + if (!data) + goto out; + + if ((ret_sts & AEON_IPC_STS_STATUS) =3D=3D AEON_IPC_STS_STATUS_ERROR) { + ret =3D -EINVAL; + goto out; + } + + /* Prevent IPC from stack smashing the kernel. + * We can't trust IPC to return a good value and we always + * preallocate space for 16 Bytes. + */ + ret_size =3D FIELD_GET(AEON_IPC_STS_SIZE, ret_sts); + if (ret_size > AEON_IPC_DATA_MAX) { + ret =3D -EINVAL; + goto out; + } + + /* Read data from IPC data register for ret_size value from IPC */ + for (i =3D 0; i < DIV_ROUND_UP(ret_size, sizeof(u16)); i++) { + ret =3D phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_IPC_DATA(i)); + if (ret < 0) + goto out; + + ret_data[i] =3D ret; + } + + ret =3D ret_size; + +out: + mutex_unlock(&priv->ipc_lock); + + return ret; +} + +static int aeon_ipc_noop(struct phy_device *phydev, + struct as21xxx_priv *priv, u16 *ret_sts) +{ + u16 cmd; + + cmd =3D FIELD_PREP(AEON_IPC_CMD_SIZE, 0) | + FIELD_PREP(AEON_IPC_CMD_OPCODE, IPC_CMD_NOOP); + + return aeon_ipc_send_cmd(phydev, priv, cmd, ret_sts); +} + +/* Logic to sync parity bit with IPC. + * We send 2 NOP cmd with same partity and we wait for IPC + * to handle the packet only for the second one. This way + * we make sure we are sync for every next cmd. + */ +static int aeon_ipc_sync_parity(struct phy_device *phydev, + struct as21xxx_priv *priv) +{ + u16 ret_sts; + int ret; + + mutex_lock(&priv->ipc_lock); + + /* Send NOP with no parity */ + aeon_ipc_noop(phydev, priv, NULL); + + /* Reset packet parity */ + priv->parity_status =3D false; + + /* Send second NOP with no parity */ + ret =3D aeon_ipc_noop(phydev, priv, &ret_sts); + + mutex_unlock(&priv->ipc_lock); + + /* We expect to return -EINVAL */ + if (ret !=3D -EINVAL) + return ret; + + if ((ret_sts & AEON_IPC_STS_STATUS) !=3D AEON_IPC_STS_STATUS_READY) { + phydev_err(phydev, "Invalid IPC status on sync parity: %x\n", + ret_sts); + return -EINVAL; + } + + return 0; +} + +static int aeon_ipc_get_fw_version(struct phy_device *phydev) +{ + u16 ret_data[AEON_IPC_DATA_NUM_REGISTERS], data[1]; + char fw_version[AEON_IPC_DATA_MAX + 1]; + int ret; + + data[0] =3D IPC_INFO_VERSION; + + ret =3D aeon_ipc_send_msg(phydev, IPC_CMD_INFO, data, + sizeof(data), ret_data); + if (ret < 0) + return ret; + + /* Make sure FW version is NULL terminated */ + memcpy(fw_version, ret_data, ret); + fw_version[ret] =3D '\0'; + + phydev_info(phydev, "Firmware Version: %s\n", fw_version); + + return 0; +} + +static int aeon_dpc_ra_enable(struct phy_device *phydev) +{ + u16 data[2]; + + data[0] =3D IPC_CFG_PARAM_DIRECT; + data[1] =3D IPC_CFG_PARAM_DIRECT_DPC_RA; + + return aeon_ipc_send_msg(phydev, IPC_CMD_CFG_PARAM, data, + sizeof(data), NULL); +} + +static int as21xxx_probe(struct phy_device *phydev) +{ + struct as21xxx_priv *priv; + int ret; + + priv =3D devm_kzalloc(&phydev->mdio.dev, + sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + phydev->priv =3D priv; + + ret =3D devm_mutex_init(&phydev->mdio.dev, + &priv->ipc_lock); + if (ret) + return ret; + + ret =3D aeon_ipc_sync_parity(phydev, priv); + if (ret) + return ret; + + ret =3D aeon_ipc_get_fw_version(phydev); + if (ret) + return ret; + + /* Enable PTP clk if not already Enabled */ + ret =3D phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PTP_CLK, + VEND1_PTP_CLK_EN); + if (ret) + return ret; + + return aeon_dpc_ra_enable(phydev); +} + +static int as21xxx_read_link(struct phy_device *phydev, int *bmcr) +{ + int status; + + /* Normal C22 BMCR report inconsistent data, use + * the mapped C22 in C45 to have more consistent link info. + */ + *bmcr =3D phy_read_mmd(phydev, MDIO_MMD_AN, + AS21XXX_MDIO_AN_C22 + MII_BMCR); + if (*bmcr < 0) + return *bmcr; + + /* Autoneg is being started, therefore disregard current + * link status and report link as down. + */ + if (*bmcr & BMCR_ANRESTART) { + phydev->link =3D 0; + return 0; + } + + status =3D phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); + if (status < 0) + return status; + + phydev->link =3D !!(status & MDIO_STAT1_LSTATUS); + + return 0; +} + +static int as21xxx_read_c22_lpa(struct phy_device *phydev) +{ + int lpagb; + + /* MII_STAT1000 are only filled in the mapped C22 + * in C45, use that to fill lpagb values and check. + */ + lpagb =3D phy_read_mmd(phydev, MDIO_MMD_AN, + AS21XXX_MDIO_AN_C22 + MII_STAT1000); + if (lpagb < 0) + return lpagb; + + if (lpagb & LPA_1000MSFAIL) { + int adv =3D phy_read_mmd(phydev, MDIO_MMD_AN, + AS21XXX_MDIO_AN_C22 + MII_CTRL1000); + + if (adv < 0) + return adv; + + if (adv & CTL1000_ENABLE_MASTER) + phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting m= anual settings?\n"); + else + phydev_err(phydev, "Master/Slave resolution failed\n"); + return -ENOLINK; + } + + mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, + lpagb); + + return 0; +} + +static int as21xxx_read_status(struct phy_device *phydev) +{ + int bmcr, old_link =3D phydev->link; + int ret; + + ret =3D as21xxx_read_link(phydev, &bmcr); + if (ret) + return ret; + + /* why bother the PHY if nothing can have changed */ + if (phydev->autoneg =3D=3D AUTONEG_ENABLE && old_link && phydev->link) + return 0; + + phydev->speed =3D SPEED_UNKNOWN; + phydev->duplex =3D DUPLEX_UNKNOWN; + phydev->pause =3D 0; + phydev->asym_pause =3D 0; + + if (phydev->autoneg =3D=3D AUTONEG_ENABLE) { + ret =3D genphy_c45_read_lpa(phydev); + if (ret) + return ret; + + ret =3D as21xxx_read_c22_lpa(phydev); + if (ret) + return ret; + + phy_resolve_aneg_linkmode(phydev); + } else { + int speed; + + linkmode_zero(phydev->lp_advertising); + + speed =3D phy_read_mmd(phydev, MDIO_MMD_VEND1, + VEND1_SPEED_STATUS); + if (speed < 0) + return speed; + + switch (speed & VEND1_SPEED_STATUS) { + case VEND1_SPEED_10000: + phydev->speed =3D SPEED_10000; + phydev->duplex =3D DUPLEX_FULL; + break; + case VEND1_SPEED_5000: + phydev->speed =3D SPEED_5000; + phydev->duplex =3D DUPLEX_FULL; + break; + case VEND1_SPEED_2500: + phydev->speed =3D SPEED_2500; + phydev->duplex =3D DUPLEX_FULL; + break; + case VEND1_SPEED_1000: + phydev->speed =3D SPEED_1000; + if (bmcr & BMCR_FULLDPLX) + phydev->duplex =3D DUPLEX_FULL; + else + phydev->duplex =3D DUPLEX_HALF; + break; + case VEND1_SPEED_100: + phydev->speed =3D SPEED_100; + phydev->duplex =3D DUPLEX_FULL; + break; + case VEND1_SPEED_10: + phydev->speed =3D SPEED_10; + phydev->duplex =3D DUPLEX_FULL; + break; + default: + return -EINVAL; + } + } + + return 0; +} + +static int as21xxx_led_brightness_set(struct phy_device *phydev, + u8 index, enum led_brightness value) +{ + u16 val =3D VEND1_LED_REG_A_EVENT_OFF; + + if (index > AEON_MAX_LEDS) + return -EINVAL; + + if (value) + val =3D VEND1_LED_REG_A_EVENT_ON; + + return phy_modify_mmd(phydev, MDIO_MMD_VEND1, + VEND1_LED_REG(index), + VEND1_LED_REG_A_EVENT, + FIELD_PREP(VEND1_LED_REG_A_EVENT, val)); +} + +static int as21xxx_led_hw_is_supported(struct phy_device *phydev, u8 index, + unsigned long rules) +{ + int i; + + if (index > AEON_MAX_LEDS) + return -EINVAL; + + for (i =3D 0; i < ARRAY_SIZE(as21xxx_led_supported_pattern); i++) + if (rules =3D=3D as21xxx_led_supported_pattern[i].pattern) + return 0; + + return -EOPNOTSUPP; +} + +static int as21xxx_led_hw_control_get(struct phy_device *phydev, u8 index, + unsigned long *rules) +{ + int i, val; + + if (index > AEON_MAX_LEDS) + return -EINVAL; + + val =3D phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_LED_REG(index)); + if (val < 0) + return val; + + val =3D FIELD_GET(VEND1_LED_REG_A_EVENT, val); + for (i =3D 0; i < ARRAY_SIZE(as21xxx_led_supported_pattern); i++) + if (val =3D=3D as21xxx_led_supported_pattern[i].val) { + *rules =3D as21xxx_led_supported_pattern[i].pattern; + return 0; + } + + /* Should be impossible */ + return -EINVAL; +} + +static int as21xxx_led_hw_control_set(struct phy_device *phydev, u8 index, + unsigned long rules) +{ + u16 val =3D 0; + int i; + + if (index > AEON_MAX_LEDS) + return -EINVAL; + + for (i =3D 0; i < ARRAY_SIZE(as21xxx_led_supported_pattern); i++) + if (rules =3D=3D as21xxx_led_supported_pattern[i].pattern) { + val =3D as21xxx_led_supported_pattern[i].val; + break; + } + + return phy_modify_mmd(phydev, MDIO_MMD_VEND1, + VEND1_LED_REG(index), + VEND1_LED_REG_A_EVENT, + FIELD_PREP(VEND1_LED_REG_A_EVENT, val)); +} + +static int as21xxx_led_polarity_set(struct phy_device *phydev, int index, + unsigned long modes) +{ + bool led_active_low =3D false; + u16 mask, val =3D 0; + u32 mode; + + if (index > AEON_MAX_LEDS) + return -EINVAL; + + for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) { + switch (mode) { + case PHY_LED_ACTIVE_LOW: + led_active_low =3D true; + break; + case PHY_LED_ACTIVE_HIGH: /* default mode */ + led_active_low =3D false; + break; + default: + return -EINVAL; + } + } + + mask =3D VEND1_GLB_CPU_CTRL_LED_POLARITY(index); + if (led_active_low) + val =3D VEND1_GLB_CPU_CTRL_LED_POLARITY(index); + + return phy_modify_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLB_REG_CPU_CTRL, + mask, val); +} + +static int as21xxx_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) +{ + struct as21xxx_priv *priv; + u16 ret_sts; + u32 phy_id; + int ret; + + /* Skip PHY that are not AS21xxx or already have firmware loaded */ + if (phydev->c45_ids.device_ids[MDIO_MMD_PCS] !=3D PHY_ID_AS21XXX) + return genphy_match_phy_device(phydev, phydrv); + + /* Read PHY ID to handle firmware just loaded */ + ret =3D phy_read_mmd(phydev, MDIO_MMD_PCS, MII_PHYSID1); + if (ret < 0) + return ret; + phy_id =3D ret << 16; + + ret =3D phy_read_mmd(phydev, MDIO_MMD_PCS, MII_PHYSID2); + if (ret < 0) + return ret; + phy_id |=3D ret; + + /* With PHY ID not the generic AS21xxx one assume + * the firmware just loaded + */ + if (phy_id !=3D PHY_ID_AS21XXX) + return phy_id =3D=3D phydrv->phy_id; + + /* Allocate temp priv and load the firmware */ + priv =3D kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + mutex_init(&priv->ipc_lock); + + ret =3D aeon_firmware_load(phydev); + if (ret) + goto out; + + /* Sync parity... */ + ret =3D aeon_ipc_sync_parity(phydev, priv); + if (ret) + goto out; + + /* ...and send a third NOOP cmd to wait for firmware finish loading */ + ret =3D aeon_ipc_noop(phydev, priv, &ret_sts); + if (ret) + goto out; + +out: + mutex_destroy(&priv->ipc_lock); + kfree(priv); + + /* Return can either be 0 or a negative error code. + * Returning 0 here means THIS is NOT a suitable PHY. + * + * For the specific case of the generic Aeonsemi PHY ID that + * needs the firmware the be loaded first to have a correct PHY ID, + * this is OK as a matching PHY ID will be found right after. + * This relies on the driver probe order where the first PHY driver + * probed is the generic one. + */ + return ret; +} + +static struct phy_driver as21xxx_drivers[] =3D { + { + /* PHY expose in C45 as 0x7500 0x9410 + * before firmware is loaded. + * This driver entry must be attempted first to load + * the firmware and thus update the ID registers. + */ + PHY_ID_MATCH_EXACT(PHY_ID_AS21XXX), + .name =3D "Aeonsemi AS21xxx", + .match_phy_device =3D as21xxx_match_phy_device, + }, + { + PHY_ID_MATCH_EXACT(PHY_ID_AS21011JB1), + .name =3D "Aeonsemi AS21011JB1", + .probe =3D as21xxx_probe, + .match_phy_device =3D as21xxx_match_phy_device, + .read_status =3D as21xxx_read_status, + .led_brightness_set =3D as21xxx_led_brightness_set, + .led_hw_is_supported =3D as21xxx_led_hw_is_supported, + .led_hw_control_set =3D as21xxx_led_hw_control_set, + .led_hw_control_get =3D as21xxx_led_hw_control_get, + .led_polarity_set =3D as21xxx_led_polarity_set, + }, + { + PHY_ID_MATCH_EXACT(PHY_ID_AS21011PB1), + .name =3D "Aeonsemi AS21011PB1", + .probe =3D as21xxx_probe, + .match_phy_device =3D as21xxx_match_phy_device, + .read_status =3D as21xxx_read_status, + .led_brightness_set =3D as21xxx_led_brightness_set, + .led_hw_is_supported =3D as21xxx_led_hw_is_supported, + .led_hw_control_set =3D as21xxx_led_hw_control_set, + .led_hw_control_get =3D as21xxx_led_hw_control_get, + .led_polarity_set =3D as21xxx_led_polarity_set, + }, + { + PHY_ID_MATCH_EXACT(PHY_ID_AS21010PB1), + .name =3D "Aeonsemi AS21010PB1", + .probe =3D as21xxx_probe, + .match_phy_device =3D as21xxx_match_phy_device, + .read_status =3D as21xxx_read_status, + .led_brightness_set =3D as21xxx_led_brightness_set, + .led_hw_is_supported =3D as21xxx_led_hw_is_supported, + .led_hw_control_set =3D as21xxx_led_hw_control_set, + .led_hw_control_get =3D as21xxx_led_hw_control_get, + .led_polarity_set =3D as21xxx_led_polarity_set, + }, + { + PHY_ID_MATCH_EXACT(PHY_ID_AS21010JB1), + .name =3D "Aeonsemi AS21010JB1", + .probe =3D as21xxx_probe, + .match_phy_device =3D as21xxx_match_phy_device, + .read_status =3D as21xxx_read_status, + .led_brightness_set =3D as21xxx_led_brightness_set, + .led_hw_is_supported =3D as21xxx_led_hw_is_supported, + .led_hw_control_set =3D as21xxx_led_hw_control_set, + .led_hw_control_get =3D as21xxx_led_hw_control_get, + .led_polarity_set =3D as21xxx_led_polarity_set, + }, + { + PHY_ID_MATCH_EXACT(PHY_ID_AS21210PB1), + .name =3D "Aeonsemi AS21210PB1", + .probe =3D as21xxx_probe, + .match_phy_device =3D as21xxx_match_phy_device, + .read_status =3D as21xxx_read_status, + .led_brightness_set =3D as21xxx_led_brightness_set, + .led_hw_is_supported =3D as21xxx_led_hw_is_supported, + .led_hw_control_set =3D as21xxx_led_hw_control_set, + .led_hw_control_get =3D as21xxx_led_hw_control_get, + .led_polarity_set =3D as21xxx_led_polarity_set, + }, + { + PHY_ID_MATCH_EXACT(PHY_ID_AS21510JB1), + .name =3D "Aeonsemi AS21510JB1", + .probe =3D as21xxx_probe, + .match_phy_device =3D as21xxx_match_phy_device, + .read_status =3D as21xxx_read_status, + .led_brightness_set =3D as21xxx_led_brightness_set, + .led_hw_is_supported =3D as21xxx_led_hw_is_supported, + .led_hw_control_set =3D as21xxx_led_hw_control_set, + .led_hw_control_get =3D as21xxx_led_hw_control_get, + .led_polarity_set =3D as21xxx_led_polarity_set, + }, + { + PHY_ID_MATCH_EXACT(PHY_ID_AS21510PB1), + .name =3D "Aeonsemi AS21510PB1", + .probe =3D as21xxx_probe, + .match_phy_device =3D as21xxx_match_phy_device, + .read_status =3D as21xxx_read_status, + .led_brightness_set =3D as21xxx_led_brightness_set, + .led_hw_is_supported =3D as21xxx_led_hw_is_supported, + .led_hw_control_set =3D as21xxx_led_hw_control_set, + .led_hw_control_get =3D as21xxx_led_hw_control_get, + .led_polarity_set =3D as21xxx_led_polarity_set, + }, + { + PHY_ID_MATCH_EXACT(PHY_ID_AS21511JB1), + .name =3D "Aeonsemi AS21511JB1", + .probe =3D as21xxx_probe, + .match_phy_device =3D as21xxx_match_phy_device, + .read_status =3D as21xxx_read_status, + .led_brightness_set =3D as21xxx_led_brightness_set, + .led_hw_is_supported =3D as21xxx_led_hw_is_supported, + .led_hw_control_set =3D as21xxx_led_hw_control_set, + .led_hw_control_get =3D as21xxx_led_hw_control_get, + .led_polarity_set =3D as21xxx_led_polarity_set, + }, + { + PHY_ID_MATCH_EXACT(PHY_ID_AS21210JB1), + .name =3D "Aeonsemi AS21210JB1", + .probe =3D as21xxx_probe, + .match_phy_device =3D as21xxx_match_phy_device, + .read_status =3D as21xxx_read_status, + .led_brightness_set =3D as21xxx_led_brightness_set, + .led_hw_is_supported =3D as21xxx_led_hw_is_supported, + .led_hw_control_set =3D as21xxx_led_hw_control_set, + .led_hw_control_get =3D as21xxx_led_hw_control_get, + .led_polarity_set =3D as21xxx_led_polarity_set, + }, + { + PHY_ID_MATCH_EXACT(PHY_ID_AS21511PB1), + .name =3D "Aeonsemi AS21511PB1", + .probe =3D as21xxx_probe, + .match_phy_device =3D as21xxx_match_phy_device, + .read_status =3D as21xxx_read_status, + .led_brightness_set =3D as21xxx_led_brightness_set, + .led_hw_is_supported =3D as21xxx_led_hw_is_supported, + .led_hw_control_set =3D as21xxx_led_hw_control_set, + .led_hw_control_get =3D as21xxx_led_hw_control_get, + .led_polarity_set =3D as21xxx_led_polarity_set, + }, +}; +module_phy_driver(as21xxx_drivers); + +static struct mdio_device_id __maybe_unused as21xxx_tbl[] =3D { + { PHY_ID_MATCH_VENDOR(PHY_VENDOR_AEONSEMI) }, + { } +}; +MODULE_DEVICE_TABLE(mdio, as21xxx_tbl); + +MODULE_DESCRIPTION("Aeonsemi AS21xxx PHY driver"); +MODULE_AUTHOR("Christian Marangi "); +MODULE_LICENSE("GPL"); --=20 2.48.1 From nobody Wed Dec 17 07:10:22 2025 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AEE8E219EB6; Sat, 17 May 2025 20:14:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747512881; cv=none; b=fU4C13SdMmGi7qFcTgqirbz79K6PxPt9Y3G8JScswdZQFFc/sACtu7srakNfPFvwGH/O3U+xiZ9ws7oTRUO1seMHnqYtN/1qBQDl+ZM9gmo6+3ZgJUf4cFgaYc78RN2eMsf6ZuvrJAs9DNmaQRQnL+YK/WmprWwEVF0TSNHURVs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747512881; c=relaxed/simple; bh=2yGKARmPcHbfZzyzn2WTevDsYdGxrPhfxSpFQ/v7kks=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bCs6vf32q+gqU2FnzXl6EG3yujw5xLx9RSCUf1//pa/eFuHQC6u6MFHw2FhB1OUhfNCiCntCcF29XihhR+/IxqQgCYSyQBAuMtnSN9dAqblZJ5jlRAzApG2awiAb6q0Y6QWu85Z9kQg18CRWChSlnwDEiySwvJvps9u/yUoRjZo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=IO8zZh+Z; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="IO8zZh+Z" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-442ed8a275fso38628835e9.2; Sat, 17 May 2025 13:14:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1747512878; x=1748117678; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=1+WJq3/QRM5Ozd7Q8cMybi3PuINc6tP7bYwsOpEjVlw=; b=IO8zZh+ZBCx4T/i3oOkqHVlbhwKDp9TQR3TcPA//R3BtAiEj0l+gwz94or1idGXiYZ jAk0EySIg5dOvAtj0jIl6mzKsc91k+jcDHf/SQwTcP0Cd9oEMsc5kIlltMT7g5UBgDUD gBeUWizArWCmSHV9YNRUxchk372FcpiTVc/PI4LmcsfQMda/QRU4Ib2XmTTNmptNB5rP tDLoXs06yWSWOcyW6zeZJVmi+2uoJ7vFwtbCr2QKzPDGq0FzyE50w+Gt8g4I4zynEzZe x95+UpFADfegPk1pXa+zKnQIcEb6I2H45lUjT1avEBn/WgGIapaUVs3VyF29fli5MSFm BiUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747512878; x=1748117678; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1+WJq3/QRM5Ozd7Q8cMybi3PuINc6tP7bYwsOpEjVlw=; b=nr0kXgI9RuTUGHlONfaf9biHyNcW8mDRLXBlDTFYarnj35afxqAskkBdESyEiW9KaF GocDKScVXd+Pp/sY3wfmosnahgcDq7tkSHOST6eoPWFQdVhmaQw+yKV41iPXD2NzDl7r dIc6fHzOsk53TcLmDFfiYLopWq8B+j67fIbBAzIAOksDqllPaeOo4K2FFEjaOU3jHHNK s4iTyjBMGsz6pUbtW9Ck6ABbGFatWslnPfuJSjE1gYPMedC/4ikAWu2+rfwnj68x95sv JPVgdIcaGXmXpw6m1f5eMuheNHO+M0IgrqMQFWxU8UPyZyBszhNWopuQSLVweKtIM4cr kQgQ== X-Forwarded-Encrypted: i=1; AJvYcCU+CZRaswF6lVh2Impq+pt9gB2hLGONcce97fkAklRS8FqINpeqGlp/CLaeJ8Zg3DD4H5HaAkBSEuRl3VEnmaw=@vger.kernel.org, AJvYcCVSnDQvw/Sw8nseyhS9324Go9k9pcXavA3JAY08ClyrhAATFK0kGf8MADeTKxjLnWY+sOpfzgzf@vger.kernel.org, AJvYcCWlqa1FY5usYICl583nmLkBfJCxAABPzmb2+QeJMIn/LDKUy2HnqnvnOuanfhdboWzrjONCjpTw7unh@vger.kernel.org, AJvYcCXuvboBEhoi50kQkgWZG9BEecSgpurA3i9U2UkRWDdB8ij8qHXMfJ5pgci/k0QdVESW9GcotgMFyFj7k4O+@vger.kernel.org X-Gm-Message-State: AOJu0Yyiv8K+fp+UOBDTgGjo7VyEeD8TC8HWtC8oPYinS8UcgpgmJByR /jGJuVdRq6vY5T/Tp5E9Omqi9+g9lUg7WnFhbdmuvUXPxIR0+aOZTD17 X-Gm-Gg: ASbGnctxNtW45TNJI+6jkJbbiXu9q76XCThZuVkqdDa9+7cX9TL1bBY6/zKFxWN/mH+ 1xjYxdizhYcqYfJGBD9pFRZ9QR0j02V5IDcsJrJMRzZjO2D3DYS0E4/XRlhcAqY8ICJgS3xo0YZ LUoHH3SCP7B1AsWlsZAmfhk8dZOlfDPKFSB10qmqkZbD4tGsRLnA81HEk3A6OXbUNdBi/EMtyA/ 1e7o+IjgDecVEqPFa9+kRlip6/XNqO/9wiywvHpxfkjAiUyF8fOJ7bcc2QLqAY3CRgh5I2NOJYf jv7QnK98nTTA8w0lb3gMTV493+8A5M19BdjB2BC9NMgq02EgDVRNin7a+0bokXv8dnDrKKrJBNZ R9/fOYESunCMlTF0Br45F X-Google-Smtp-Source: AGHT+IEMYLcYs6Tqfs3/y2GsUBIqhzMkMi1qwMQIwzchu5sAPL3gwZ2+PECG9rDdW0ZYMuv/KfO3ng== X-Received: by 2002:a05:600c:3e88:b0:43c:fbbf:7bf1 with SMTP id 5b1f17b1804b1-442fd6724bbmr85451855e9.30.1747512877584; Sat, 17 May 2025 13:14:37 -0700 (PDT) Received: from localhost.localdomain (93-34-88-225.ip49.fastwebnet.it. [93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-442fd4fdcccsm85345445e9.6.2025.05.17.13.14.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 May 2025 13:14:37 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , =?UTF-8?q?Marek=20Beh=C3=BAn?= , Andrei Botila , FUJITA Tomonori , Trevor Gross , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Danilo Krummrich , Sabrina Dubroca , Michael Klein , Daniel Golle , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org Subject: [net-next PATCH v12 6/6] dt-bindings: net: Document support for Aeonsemi PHYs Date: Sat, 17 May 2025 22:13:50 +0200 Message-ID: <20250517201353.5137-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250517201353.5137-1-ansuelsmth@gmail.com> References: <20250517201353.5137-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Aeonsemi PHYs and the requirement of a firmware to correctly work. Also document the max number of LEDs supported and what PHY ID expose when no firmware is loaded. Supported PHYs AS21011JB1, AS21011PB1, AS21010JB1, AS21010PB1, AS21511JB1, AS21511PB1, AS21510JB1, AS21510PB1, AS21210JB1, AS21210PB1 that all register with the PHY ID 0x7500 0x9410 on C45 registers before the firmware is loaded. Reviewed-by: Rob Herring (Arm) Signed-off-by: Christian Marangi --- .../bindings/net/aeonsemi,as21xxx.yaml | 122 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 123 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/aeonsemi,as21xxx.= yaml diff --git a/Documentation/devicetree/bindings/net/aeonsemi,as21xxx.yaml b/= Documentation/devicetree/bindings/net/aeonsemi,as21xxx.yaml new file mode 100644 index 000000000000..69eb29dc4d7b --- /dev/null +++ b/Documentation/devicetree/bindings/net/aeonsemi,as21xxx.yaml @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/aeonsemi,as21xxx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aeonsemi AS21XXX Ethernet PHY + +maintainers: + - Christian Marangi + +description: | + Aeonsemi AS21xxx Ethernet PHYs requires a firmware to be loaded to actua= lly + work. The same firmware is compatible with various PHYs of the same fami= ly. + + A PHY with not firmware loaded will be exposed on the MDIO bus with ID + 0x7500 0x7500 or 0x7500 0x9410 on C45 registers. + + This can be done and is implemented by OEM in 2 different way: + - Attached SPI flash directly to the PHY with the firmware. The PHY + will self load the firmware in the presence of this configuration. + - Manually provided firmware loaded from a file in the filesystem. + + Each PHY can support up to 5 LEDs. + + AS2xxx PHY Name logic: + + AS21x1xxB1 + ^ ^^ + | |J: Supports SyncE/PTP + | |P: No SyncE/PTP support + | 1: Supports 2nd Serdes + | 2: Not 2nd Serdes support + 0: 10G, 5G, 2.5G + 5: 5G, 2.5G + 2: 2.5G + +allOf: + - $ref: ethernet-phy.yaml# + +select: + properties: + compatible: + contains: + enum: + - ethernet-phy-id7500.9410 + - ethernet-phy-id7500.9402 + - ethernet-phy-id7500.9412 + - ethernet-phy-id7500.9422 + - ethernet-phy-id7500.9432 + - ethernet-phy-id7500.9442 + - ethernet-phy-id7500.9452 + - ethernet-phy-id7500.9462 + - ethernet-phy-id7500.9472 + - ethernet-phy-id7500.9482 + - ethernet-phy-id7500.9492 + required: + - compatible + +properties: + reg: + maxItems: 1 + + firmware-name: + description: specify the name of PHY firmware to load + maxItems: 1 + +required: + - compatible + - reg + +if: + properties: + compatible: + contains: + const: ethernet-phy-id7500.9410 +then: + required: + - firmware-name +else: + properties: + firmware-name: false + +unevaluatedProperties: false + +examples: + - | + #include + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethernet-phy@1f { + compatible =3D "ethernet-phy-id7500.9410", + "ethernet-phy-ieee802.3-c45"; + + reg =3D <31>; + firmware-name =3D "as21x1x_fw.bin"; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@0 { + reg =3D <0>; + color =3D ; + function =3D LED_FUNCTION_LAN; + function-enumerator =3D <0>; + default-state =3D "keep"; + }; + + led@1 { + reg =3D <1>; + color =3D ; + function =3D LED_FUNCTION_LAN; + function-enumerator =3D <1>; + default-state =3D "keep"; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 6cc52e99c1f8..d11038a90113 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -650,6 +650,7 @@ AEONSEMI PHY DRIVER M: Christian Marangi L: netdev@vger.kernel.org S: Maintained +F: Documentation/devicetree/bindings/net/aeonsemi,as21xxx.yaml F: drivers/net/phy/as21xxx.c =20 AF8133J THREE-AXIS MAGNETOMETER DRIVER --=20 2.48.1