From nobody Fri Dec 19 20:38:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D9A320D4FA; Sat, 17 May 2025 17:33:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747503197; cv=none; b=rTzlV53EP51ZvfqxQBZAh1A03MXJFzITcbOfz1NT5178+Nlyijdbj7iLXi4p4YqRUR0MaFmiAtrewQiGXIOA+5Gny+hAbiLZhXHIYyIjr+FVQgkXiOFXCLMe+k/mdJRzZatDEk9ikYAe2oV4AEF3moNQNAmJGZ/g0yq3GWaLKDo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747503197; c=relaxed/simple; bh=e9CYqlf6f9RwZ7ZTGKfCmSLOPF7M+1dxoe2wrA4XZ0k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=r+Czg2NU9i06Nsf8K/xrSy6Ix0ACqcQbbGfnAYKRMDIx/2+HB2au2fGMgbnQwM9oQ8qwY0+BlkTd5uqx/y2cBRkdEOk1flwp/fHtXCs6CyzlZ8ejCkbKWfTaUUifGiQXFTTFGONqPGL+jrtE+hQazc2p0SdRHTwbyIORrBG4nlM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HdDcp4r+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HdDcp4r+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0A06EC4CEE3; Sat, 17 May 2025 17:33:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747503195; bh=e9CYqlf6f9RwZ7ZTGKfCmSLOPF7M+1dxoe2wrA4XZ0k=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=HdDcp4r+ToVCvpq4McaC+lEAkQD93BsgH4ncce+nJgt8SoUC/CFLHMrTXkcpyVr2z aajCykIR+ZhIYIlASDjAXdyIEsnZp/o0bOgnUYOBvImnt7FRo7g9LwEyu0eXLRc0mi yOSM/aZTawuW4GO9qNlEnH1hojUi/Iyq4ynsQUOk/W8iWLGt6EbfLCOs3NyK3DyzG3 97Z2KsQd0SO9GJneCTGHOdVMf8xP6sIwlSIL+R2dCShBXiWfwgA73YcS8Qi3BiKuUP +S00bqqzrOEcR2l7mOQngKrXNNbqVi+fThqZ5o8Xh0V+BGu77i+VFTVHkXOPdfhSgo cWHn5zQkiE4vw== From: Konrad Dybcio Date: Sat, 17 May 2025 19:32:40 +0200 Subject: [PATCH RFT v3 06/14] drm/msm/a6xx: Simplify uavflagprd_inv detection Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250517-topic-ubwc_central-v3-6-3c8465565f86@oss.qualcomm.com> References: <20250517-topic-ubwc_central-v3-0-3c8465565f86@oss.qualcomm.com> In-Reply-To: <20250517-topic-ubwc_central-v3-0-3c8465565f86@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Akhil P Oommen , Sean Paul , David Airlie , Simona Vetter Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747503160; l=3189; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=89MeujsXfBj+kp0rlzsNJ1Dv6IXHItTcLAkH3upWFCU=; b=iXps8WOLLeMKJhrL4Qop0Is1txUVzRQachfw+18I7LdueAMPqYyOlMF3g7durZBiq1K3rs9Hq UKfU8jWMmvYBO/VSsIFJau0LMzNGWerH3gW/4yOMAx2owu6TRUYHWQZ X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Instead of setting it on a gpu-per-gpu basis, converge it to the intended "is A650 family or A7xx". Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 7570ead904adfea13b22a63d57d55d7412abb4b8..00a928fee07290951b69263dd1d= 902ce85400fc0 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -593,7 +593,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) return PTR_ERR(gpu->common_ubwc_cfg); =20 gpu->ubwc_config.rgb565_predicator =3D 0; - gpu->ubwc_config.uavflagprd_inv =3D 0; gpu->ubwc_config.min_acc_len =3D 0; gpu->ubwc_config.ubwc_swizzle =3D 0x6; gpu->ubwc_config.macrotile_mode =3D 0; @@ -615,15 +614,12 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *g= pu) if (adreno_is_a619_holi(gpu)) gpu->ubwc_config.highest_bank_bit =3D 13; =20 - if (adreno_is_a621(gpu)) { + if (adreno_is_a621(gpu)) gpu->ubwc_config.highest_bank_bit =3D 13; - gpu->ubwc_config.uavflagprd_inv =3D 2; - } =20 if (adreno_is_a623(gpu)) { gpu->ubwc_config.highest_bank_bit =3D 16; gpu->ubwc_config.rgb565_predicator =3D 1; - gpu->ubwc_config.uavflagprd_inv =3D 2; gpu->ubwc_config.macrotile_mode =3D 1; } =20 @@ -638,21 +634,18 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *g= pu) /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ gpu->ubwc_config.highest_bank_bit =3D 16; gpu->ubwc_config.rgb565_predicator =3D 1; - gpu->ubwc_config.uavflagprd_inv =3D 2; gpu->ubwc_config.macrotile_mode =3D 1; } =20 if (adreno_is_a663(gpu)) { gpu->ubwc_config.highest_bank_bit =3D 13; gpu->ubwc_config.rgb565_predicator =3D 1; - gpu->ubwc_config.uavflagprd_inv =3D 2; gpu->ubwc_config.macrotile_mode =3D 1; gpu->ubwc_config.ubwc_swizzle =3D 0x4; } =20 if (adreno_is_7c3(gpu)) { gpu->ubwc_config.highest_bank_bit =3D 14; - gpu->ubwc_config.uavflagprd_inv =3D 2; gpu->ubwc_config.macrotile_mode =3D 1; } =20 @@ -676,11 +669,15 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13); u32 hbb =3D adreno_gpu->ubwc_config.highest_bank_bit - 13; bool amsbc =3D cfg->ubwc_enc_version >=3D UBWC_3_0; + u8 uavflagprd_inv =3D 0; u32 hbb_hi =3D hbb >> 2; u32 hbb_lo =3D hbb & 3; u32 ubwc_mode =3D adreno_gpu->ubwc_config.ubwc_swizzle & 1; u32 level2_swizzling_dis =3D !(adreno_gpu->ubwc_config.ubwc_swizzle & 2); =20 + if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) + uavflagprd_inv =3D 2; + gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, level2_swizzling_dis << 12 | adreno_gpu->ubwc_config.rgb565_predicator << 11 | @@ -695,7 +692,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) =20 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, level2_swizzling_dis << 12 | hbb_hi << 10 | - adreno_gpu->ubwc_config.uavflagprd_inv << 4 | + uavflagprd_inv << 4 | adreno_gpu->ubwc_config.min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); =20 --=20 2.49.0