From nobody Fri Dec 19 20:38:22 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 188911DEFE9; Sat, 17 May 2025 17:32:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747503177; cv=none; b=sP4t+O5nmCFWViNFRecq3KvirbRJdf+lRNm4HF/taD6f4MmBbIZX844ybpGh1PRfnKuJtKrmSATO2WJP07JpS0LoQ4B4Pcm8kwW1vQWbHsgIegeXBZ5APgVD1/wfO1ng6jZALFDqNWbvrHhcabIs9WhvA8RhUe1WheyzRt5RB/s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747503177; c=relaxed/simple; bh=8IiJ7TfHpgwzHF1zZolA7SKhmyykwTNJSFjEHGPviYQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bgFqeSNVlLiz/Svd2KDIHAn76n8DjB0IK0UQ9PX5fdEbPHWdR3PK4NnZ5Ie1KcbSb44iZvA3/pnNEhW58g2fHMiVSu9UKFPRz5J68sWv9/scCVx7u7og3GbrvB7o68soOZcoRkPB63qqtFLVN+VNegRYZrXgAEFS30ZTRFnvIIU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=i4Oe6hDj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="i4Oe6hDj" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2AFC0C4CEEA; Sat, 17 May 2025 17:32:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747503175; bh=8IiJ7TfHpgwzHF1zZolA7SKhmyykwTNJSFjEHGPviYQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=i4Oe6hDj1mrxtBWAVWhPh4j/AhDbXACXwDuqj85B0wu5BIrNqnkFl2UyQrIbu2FsR 75n0PZRJ+L6VLUc76ArNfCk7c8rXMSz5NIP6thd6gZe7DsfWKQ43CmcauXN0OTT4hk 5ZfUHwsSFMQjL9SFeT4TNS6DNitO+5oRH9DCypeBG7ee8dbAAnENHsjEgPXKsE9BGZ biKgfOAuv/RJA5idN/wTNFA5A47++fnUjK07XEpbWyMUhaXwAuHIgh/LIG96IwBBpj 5vhnucPSQTJ6DCPnAkFAD9jaj/lq2IEAe3p6IfpQ40CUXGznavoVq44uW9768wxQw3 xsNTcgDOqKS9w== From: Konrad Dybcio Date: Sat, 17 May 2025 19:32:36 +0200 Subject: [PATCH RFT v3 02/14] drm/msm: Offset MDSS HBB value by 13 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250517-topic-ubwc_central-v3-2-3c8465565f86@oss.qualcomm.com> References: <20250517-topic-ubwc_central-v3-0-3c8465565f86@oss.qualcomm.com> In-Reply-To: <20250517-topic-ubwc_central-v3-0-3c8465565f86@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Akhil P Oommen , Sean Paul , David Airlie , Simona Vetter Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747503160; l=7276; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=hLzGR3olZDh/aHeaHc3gE9Za/o8UapiYfK6HVRGZaEU=; b=o6ls/838znvdNaC82PWEbSmdZUZRBYyoT9IQmw7Jdi/SBAZCq6HCKrl1Eq5LgcaU9FnaOJz/j pCgjRsLiyn/DpB15WL6ed27gY5F5sBQR4kgfsOSeYS0iqrjnwOy3yMD X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio The Adreno part of the driver exposes this value to userspace, and the SMEM data source also presents a x+13 value. Keep things coherent and make the value uniform across them. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_mdss.c | 50 +++++++++++++++++++++-----------------= ---- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 709979fcfab6062c0f316f7655823e888638bfea..2c9531217eca7ac2308c6d1fa78= 287363ca652f9 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -167,7 +167,7 @@ static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss = *msm_mdss) { const struct msm_mdss_data *data =3D msm_mdss->mdss_data; u32 value =3D MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | - MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit); + MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); =20 if (data->ubwc_bank_spread) value |=3D MDSS_UBWC_STATIC_UBWC_BANK_SPREAD; @@ -182,7 +182,7 @@ static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss = *msm_mdss) { const struct msm_mdss_data *data =3D msm_mdss->mdss_data; u32 value =3D MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle & 0x1) | - MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit); + MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); =20 if (data->macrotile_mode) value |=3D MDSS_UBWC_STATIC_MACROTILE_MODE; @@ -200,7 +200,7 @@ static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss = *msm_mdss) { const struct msm_mdss_data *data =3D msm_mdss->mdss_data; u32 value =3D MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | - MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit); + MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); =20 if (data->ubwc_bank_spread) value |=3D MDSS_UBWC_STATIC_UBWC_BANK_SPREAD; @@ -259,9 +259,9 @@ static const struct msm_mdss_data *msm_mdss_generate_md= p5_mdss_data(struct msm_m =20 if (hw_rev =3D=3D MDSS_HW_MSM8996 || hw_rev =3D=3D MDSS_HW_MSM8998) - data->highest_bank_bit =3D 2; + data->highest_bank_bit =3D 15; else - data->highest_bank_bit =3D 1; + data->highest_bank_bit =3D 14; =20 return data; } @@ -572,13 +572,13 @@ static void mdss_remove(struct platform_device *pdev) static const struct msm_mdss_data msm8998_data =3D { .ubwc_enc_version =3D UBWC_1_0, .ubwc_dec_version =3D UBWC_1_0, - .highest_bank_bit =3D 2, + .highest_bank_bit =3D 15, .reg_bus_bw =3D 76800, }; =20 static const struct msm_mdss_data qcm2290_data =3D { /* no UBWC */ - .highest_bank_bit =3D 0x2, + .highest_bank_bit =3D 15, .reg_bus_bw =3D 76800, }; =20 @@ -587,7 +587,7 @@ static const struct msm_mdss_data sa8775p_data =3D { .ubwc_dec_version =3D UBWC_4_0, .ubwc_swizzle =3D 4, .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 0, + .highest_bank_bit =3D 13, .macrotile_mode =3D true, .reg_bus_bw =3D 74000, }; @@ -597,7 +597,7 @@ static const struct msm_mdss_data sar2130p_data =3D { .ubwc_dec_version =3D UBWC_4_3, .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 0, + .highest_bank_bit =3D 13, .macrotile_mode =3D 1, .reg_bus_bw =3D 74000, }; @@ -607,7 +607,7 @@ static const struct msm_mdss_data sc7180_data =3D { .ubwc_dec_version =3D UBWC_2_0, .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 0x1, + .highest_bank_bit =3D 14, .reg_bus_bw =3D 76800, }; =20 @@ -616,7 +616,7 @@ static const struct msm_mdss_data sc7280_data =3D { .ubwc_dec_version =3D UBWC_4_0, .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 1, + .highest_bank_bit =3D 14, .macrotile_mode =3D true, .reg_bus_bw =3D 74000, }; @@ -624,7 +624,7 @@ static const struct msm_mdss_data sc7280_data =3D { static const struct msm_mdss_data sc8180x_data =3D { .ubwc_enc_version =3D UBWC_3_0, .ubwc_dec_version =3D UBWC_3_0, - .highest_bank_bit =3D 3, + .highest_bank_bit =3D 16, .macrotile_mode =3D true, .reg_bus_bw =3D 76800, }; @@ -634,7 +634,7 @@ static const struct msm_mdss_data sc8280xp_data =3D { .ubwc_dec_version =3D UBWC_4_0, .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 3, + .highest_bank_bit =3D 16, .macrotile_mode =3D true, .reg_bus_bw =3D 76800, }; @@ -642,14 +642,14 @@ static const struct msm_mdss_data sc8280xp_data =3D { static const struct msm_mdss_data sdm670_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, - .highest_bank_bit =3D 1, + .highest_bank_bit =3D 14, .reg_bus_bw =3D 76800, }; =20 static const struct msm_mdss_data sdm845_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, - .highest_bank_bit =3D 2, + .highest_bank_bit =3D 15, .reg_bus_bw =3D 76800, }; =20 @@ -658,21 +658,21 @@ static const struct msm_mdss_data sm6350_data =3D { .ubwc_dec_version =3D UBWC_2_0, .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 1, + .highest_bank_bit =3D 14, .reg_bus_bw =3D 76800, }; =20 static const struct msm_mdss_data sm7150_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, - .highest_bank_bit =3D 1, + .highest_bank_bit =3D 14, .reg_bus_bw =3D 76800, }; =20 static const struct msm_mdss_data sm8150_data =3D { .ubwc_enc_version =3D UBWC_3_0, .ubwc_dec_version =3D UBWC_3_0, - .highest_bank_bit =3D 2, + .highest_bank_bit =3D 15, .reg_bus_bw =3D 76800, }; =20 @@ -681,7 +681,7 @@ static const struct msm_mdss_data sm6115_data =3D { .ubwc_dec_version =3D UBWC_2_0, .ubwc_swizzle =3D 7, .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 0x1, + .highest_bank_bit =3D 14, .reg_bus_bw =3D 76800, }; =20 @@ -689,13 +689,13 @@ static const struct msm_mdss_data sm6125_data =3D { .ubwc_enc_version =3D UBWC_1_0, .ubwc_dec_version =3D UBWC_3_0, .ubwc_swizzle =3D 1, - .highest_bank_bit =3D 1, + .highest_bank_bit =3D 14, }; =20 static const struct msm_mdss_data sm6150_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, - .highest_bank_bit =3D 1, + .highest_bank_bit =3D 14, .reg_bus_bw =3D 76800, }; =20 @@ -705,7 +705,7 @@ static const struct msm_mdss_data sm8250_data =3D { .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ - .highest_bank_bit =3D 3, + .highest_bank_bit =3D 16, .macrotile_mode =3D true, .reg_bus_bw =3D 76800, }; @@ -716,7 +716,7 @@ static const struct msm_mdss_data sm8350_data =3D { .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ - .highest_bank_bit =3D 3, + .highest_bank_bit =3D 16, .macrotile_mode =3D true, .reg_bus_bw =3D 74000, }; @@ -727,7 +727,7 @@ static const struct msm_mdss_data sm8550_data =3D { .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ - .highest_bank_bit =3D 3, + .highest_bank_bit =3D 16, .macrotile_mode =3D true, .reg_bus_bw =3D 57000, }; @@ -738,7 +738,7 @@ static const struct msm_mdss_data x1e80100_data =3D { .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ - .highest_bank_bit =3D 3, + .highest_bank_bit =3D 16, .macrotile_mode =3D true, /* TODO: Add reg_bus_bw with real value */ }; --=20 2.49.0