From nobody Fri Dec 19 20:38:13 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BAB002116E9; Sat, 17 May 2025 17:33:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747503222; cv=none; b=VKDVRNPT05hz+dHgJTcvhFztYdSM8pLD1F1HYv7NIYFfv1VbQxgpEnXIxhb9pkmr3Tt+8Wv01xMnYgBupQ8c9nP46YYIUO3a8NU9BP9+GEEWAWZL/s+wnuxii4A4lc+TGPT7Kjer0fFpzAiz7G2CfpTfZ8yiSNaLXKadSn/nrNc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747503222; c=relaxed/simple; bh=Bm2onoNExz/LGidV9DPkUgtkgNptNuhJ1pBsZofwMTE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hQV1tf8Txb9mNqXoSQjAXTE6qFSiBK6FpIDtp7cQc1GVdPSolSQ1BJXBZb10U5XjF6dC+Dlq42k5sASRBe1p6dnxyHj7Me2fM01nmPgOCyagteuRhvX5kUvXmVXgDUH4vqiMKPNjBqCBex0lf/sSmzziPVMLAnYca75oK5ixDFg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=G+V1JxDF; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="G+V1JxDF" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A43E0C4CEE3; Sat, 17 May 2025 17:33:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747503222; bh=Bm2onoNExz/LGidV9DPkUgtkgNptNuhJ1pBsZofwMTE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=G+V1JxDFRYyUzaeFiu8sk0ypK7+oEu7MOTWk6BlFHOozM3CoYUQ/SpJsFhpFpYSQh 1jG4A1o/T1jIfO5GIxZNaQs6IdcQYQLnoFd6xCJgZlmbgAeIXKfKdbzVg9KTKO7oeO URRrwvD7ybcA16+Q1F2nuU3q8LvKq46JY1Cspux06i0BGDwkVmA8SpxWUVaAQpVVko LYWP6gPJzTHGJd9GmV1kpe9LJ/RaGL8TSZ2TqHbBQPg5KlE4yocxMKqWUUF0xOt+RJ q8DIkHauqsbp0d12Eoi5jgHDh/4MsKqkScoAQNRY6Tha2OKCRybdGLoKoG/V/r2RVg nK7RkM/1ajpiA== From: Konrad Dybcio Date: Sat, 17 May 2025 19:32:46 +0200 Subject: [PATCH RFT v3 12/14] soc: qcom: ubwc: Add #defines for UBWC swizzle bits Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250517-topic-ubwc_central-v3-12-3c8465565f86@oss.qualcomm.com> References: <20250517-topic-ubwc_central-v3-0-3c8465565f86@oss.qualcomm.com> In-Reply-To: <20250517-topic-ubwc_central-v3-0-3c8465565f86@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Akhil P Oommen , Sean Paul , David Airlie , Simona Vetter Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747503160; l=6318; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=ziyxLgzuUwElyP+/uMRV2pWiwRnNMsIPyWLQmFpmnx4=; b=jIAzHdL0q1n0nyp1tPsUCsJ53+m14n6uje5nlTpKrh5mYw62wza2CFXgQbV5cTgliGqalH7s7 MGvSTrz2RZnB3gyJhslaIp7PfgdD7GtdE6ze5B+Ga5XzAScRRijpgPh X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Make the values a bit more meaningful. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/soc/qcom/ubwc_config.c | 37 +++++++++++++++++++++++++------------ include/linux/soc/qcom/ubwc.h | 8 ++++---- 2 files changed, 29 insertions(+), 16 deletions(-) diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index 7002744631341796d08fa197efa2202b3018cc3e..fe874ccd8df6acb4fac65f7d261= afb05861117c2 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -32,7 +32,7 @@ static const struct qcom_ubwc_cfg_data qcm2290_data =3D { static const struct qcom_ubwc_cfg_data sa8775p_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 4, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 13, .macrotile_mode =3D true, @@ -41,7 +41,8 @@ static const struct qcom_ubwc_cfg_data sa8775p_data =3D { static const struct qcom_ubwc_cfg_data sar2130p_data =3D { .ubwc_enc_version =3D UBWC_3_0, /* 4.0.2 in hw */ .ubwc_dec_version =3D UBWC_4_3, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 13, .macrotile_mode =3D true, @@ -50,7 +51,8 @@ static const struct qcom_ubwc_cfg_data sar2130p_data =3D { static const struct qcom_ubwc_cfg_data sc7180_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 14, }; @@ -58,7 +60,8 @@ static const struct qcom_ubwc_cfg_data sc7180_data =3D { static const struct qcom_ubwc_cfg_data sc7280_data =3D { .ubwc_enc_version =3D UBWC_3_0, .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 14, .macrotile_mode =3D true, @@ -74,7 +77,8 @@ static const struct qcom_ubwc_cfg_data sc8180x_data =3D { static const struct qcom_ubwc_cfg_data sc8280xp_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 16, .macrotile_mode =3D true, @@ -95,7 +99,9 @@ static const struct qcom_ubwc_cfg_data sdm845_data =3D { static const struct qcom_ubwc_cfg_data sm6115_data =3D { .ubwc_enc_version =3D UBWC_1_0, .ubwc_dec_version =3D UBWC_2_0, - .ubwc_swizzle =3D 7, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL1 | + UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 14, }; @@ -103,7 +109,9 @@ static const struct qcom_ubwc_cfg_data sm6115_data =3D { static const struct qcom_ubwc_cfg_data sm6125_data =3D { .ubwc_enc_version =3D UBWC_1_0, .ubwc_dec_version =3D UBWC_3_0, - .ubwc_swizzle =3D 7, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL1 | + UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; =20 @@ -116,7 +124,8 @@ static const struct qcom_ubwc_cfg_data sm6150_data =3D { static const struct qcom_ubwc_cfg_data sm6350_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 14, }; @@ -136,7 +145,8 @@ static const struct qcom_ubwc_cfg_data sm8150_data =3D { static const struct qcom_ubwc_cfg_data sm8250_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ .highest_bank_bit =3D 16, @@ -146,7 +156,8 @@ static const struct qcom_ubwc_cfg_data sm8250_data =3D { static const struct qcom_ubwc_cfg_data sm8350_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ .highest_bank_bit =3D 16, @@ -156,7 +167,8 @@ static const struct qcom_ubwc_cfg_data sm8350_data =3D { static const struct qcom_ubwc_cfg_data sm8550_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_3, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ .highest_bank_bit =3D 16, @@ -166,7 +178,8 @@ static const struct qcom_ubwc_cfg_data sm8550_data =3D { static const struct qcom_ubwc_cfg_data x1e80100_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_3, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ .highest_bank_bit =3D 16, diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h index 7227bcdbd8d88834beb7427ca0929964d2ae937d..ae09f48a96417f65824cdbfa98d= 2999dc01bc781 100644 --- a/include/linux/soc/qcom/ubwc.h +++ b/include/linux/soc/qcom/ubwc.h @@ -21,11 +21,11 @@ struct qcom_ubwc_cfg_data { * UBWC 1.0 always enables all three levels. * UBWC 2.0 removes level 1 bank swizzling, leaving levels 2 & 3. * UBWC 4.0 adds the optional ability to disable levels 2 & 3. - * - * This is a bitmask where BIT(0) enables level 1, BIT(1) - * controls level 2, and BIT(2) enables level 3. */ u32 ubwc_swizzle; +#define UBWC_SWIZZLE_ENABLE_LVL1 BIT(0) +#define UBWC_SWIZZLE_ENABLE_LVL2 BIT(1) +#define UBWC_SWIZZLE_ENABLE_LVL3 BIT(2) =20 /** * @highest_bank_bit: Highest Bank Bit @@ -58,7 +58,7 @@ static inline bool qcom_ubwc_get_ubwc_mode(const struct q= com_ubwc_cfg_data *cfg) { bool ret =3D cfg->ubwc_enc_version =3D=3D UBWC_1_0; =20 - if (ret && !(cfg->ubwc_swizzle & BIT(0))) + if (ret && !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL1)) pr_err("UBWC config discrepancy - level 1 swizzling disabled on UBWC 1.0= \n"); =20 return ret; --=20 2.49.0