From nobody Fri Dec 19 20:38:25 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6704720D4EB; Sat, 17 May 2025 17:28:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747502889; cv=none; b=VWHQ5kkJqdQenYqGtGlIul5/SgurRV3T9NH1F8bGQGrBiAI0KNijPbGV+lLvoPjhAP6Vso08sRT1i926bXvxFf8Xt2yWhTTIyhIvI2WnAqolRDJVIzUOtSgDaiufgGKo+v6Mvt4wTY2S58rOvGNO5s0rrhJk5+HlCWj5j+l6aWI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747502889; c=relaxed/simple; bh=062RmATaJHg1+JNK3SlnDQyFrSpSj7KSwC8nySXa7Pc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Xw4XUp/DMu0gNnwFbwMM3kcWM9oH6a6PHsI5pakoSTQyANYuJJ2rHPjmWZDs1g+3PbvOEtNpSaTlsRA7Sy709oJH9xFSAz5buE/T25shEze7UczL0PnDqXQgtaYVXoZYmeGiPglXuepvugPQH0dhpOloNQTAljtHEwW36tmYu8Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=a7ZUWE15; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="a7ZUWE15" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BA14DC4CEE3; Sat, 17 May 2025 17:28:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747502888; bh=062RmATaJHg1+JNK3SlnDQyFrSpSj7KSwC8nySXa7Pc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=a7ZUWE153k51Y3ZONtbzmYyMT6oS5nfTRYwN9dcZ0hjp1vY15tcvjNKrCfG87kY44 pead8zabmO0dGWuYVnppHec758XBJamtacWXzPBHgRE9ji3dAb7PNjYUQ4dHFa/Il/ xypkNk+8cM6Y2yqSLDspQsAUA/DjsJkMDS6loQgDLVpm2N1j3cJwBGwsjoO8hHPwUQ T/kJ/MbDma/vHfpukRcFlPM0Dmoqp7NfTCELp13LcPE8BJ6Kc62qdmN3/SLgYtxAYl FpwYVSQL+BS+lSf/GJ315Rv88jI8lElFXNJb0hPsi49df44V8NR+Nz4/VuBRm0hbE7 s/R40BaF2cUjA== From: Konrad Dybcio Date: Sat, 17 May 2025 19:27:51 +0200 Subject: [PATCH v2 2/5] arm64: dts: qcom: sc8280xp: Fix node order Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250517-topic-8280_slpi-v2-2-1f96f86ac3ae@oss.qualcomm.com> References: <20250517-topic-8280_slpi-v2-0-1f96f86ac3ae@oss.qualcomm.com> In-Reply-To: <20250517-topic-8280_slpi-v2-0-1f96f86ac3ae@oss.qualcomm.com> To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Konrad Dybcio Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747502874; l=17883; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=o4vvJe+dKVC6zH1d9tYG5Y4ze0AndgFi2VUDuEHKxRE=; b=seT+cxW7EX1gxNDzR3NVPBjioADlz90m2JO4B3M83YDlYNN5EeBQgXswa8p4GlhsrSxkOYCKH O3ycyNtPZdHBz6Kb2XPJ7MfakPSEI7VfnzNxklGKo/hPNjiUZpLeoC5 X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Certain /soc@0 subnodes are very out of order. Reshuffle them. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 574 ++++++++++++++++-------------= ---- 1 file changed, 287 insertions(+), 287 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 27d21e1a2d50c6fc12f324ab2b4dfa4b99791b81..94dcbccca62e992030bcdd6eb3b= c3fcd879c1e8a 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2454,293 +2454,6 @@ tcsr: syscon@1fc0000 { reg =3D <0x0 0x01fc0000 0x0 0x30000>; }; =20 - gpu: gpu@3d00000 { - compatible =3D "qcom,adreno-690.0", "qcom,adreno"; - - reg =3D <0 0x03d00000 0 0x40000>, - <0 0x03d9e000 0 0x1000>, - <0 0x03d61000 0 0x800>; - reg-names =3D "kgsl_3d0_reg_memory", - "cx_mem", - "cx_dbgc"; - interrupts =3D ; - iommus =3D <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>; - operating-points-v2 =3D <&gpu_opp_table>; - - qcom,gmu =3D <&gmu>; - interconnects =3D <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names =3D "gfx-mem"; - #cooling-cells =3D <2>; - - status =3D "disabled"; - - gpu_opp_table: opp-table { - compatible =3D "operating-points-v2"; - - opp-270000000 { - opp-hz =3D /bits/ 64 <270000000>; - opp-level =3D ; - opp-peak-kBps =3D <451000>; - }; - - opp-410000000 { - opp-hz =3D /bits/ 64 <410000000>; - opp-level =3D ; - opp-peak-kBps =3D <1555000>; - }; - - opp-500000000 { - opp-hz =3D /bits/ 64 <500000000>; - opp-level =3D ; - opp-peak-kBps =3D <1555000>; - }; - - opp-547000000 { - opp-hz =3D /bits/ 64 <547000000>; - opp-level =3D ; - opp-peak-kBps =3D <1555000>; - }; - - opp-606000000 { - opp-hz =3D /bits/ 64 <606000000>; - opp-level =3D ; - opp-peak-kBps =3D <2736000>; - }; - - opp-640000000 { - opp-hz =3D /bits/ 64 <640000000>; - opp-level =3D ; - opp-peak-kBps =3D <2736000>; - }; - - opp-655000000 { - opp-hz =3D /bits/ 64 <655000000>; - opp-level =3D ; - opp-peak-kBps =3D <2736000>; - }; - - opp-690000000 { - opp-hz =3D /bits/ 64 <690000000>; - opp-level =3D ; - opp-peak-kBps =3D <2736000>; - }; - }; - }; - - gmu: gmu@3d6a000 { - compatible =3D "qcom,adreno-gmu-690.0", "qcom,adreno-gmu"; - reg =3D <0 0x03d6a000 0 0x34000>, - <0 0x03de0000 0 0x10000>, - <0 0x0b290000 0 0x10000>; - reg-names =3D "gmu", "rscc", "gmu_pdc"; - interrupts =3D , - ; - interrupt-names =3D "hfi", "gmu"; - clocks =3D <&gpucc GPU_CC_CX_GMU_CLK>, - <&gpucc GPU_CC_CXO_CLK>, - <&gcc GCC_DDRSS_GPU_AXI_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>, - <&gpucc GPU_CC_AHB_CLK>, - <&gpucc GPU_CC_HUB_CX_INT_CLK>, - <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; - clock-names =3D "gmu", - "cxo", - "axi", - "memnoc", - "ahb", - "hub", - "smmu_vote"; - power-domains =3D <&gpucc GPU_CC_CX_GDSC>, - <&gpucc GPU_CC_GX_GDSC>; - power-domain-names =3D "cx", - "gx"; - iommus =3D <&gpu_smmu 5 0xc00>; - operating-points-v2 =3D <&gmu_opp_table>; - - gmu_opp_table: opp-table { - compatible =3D "operating-points-v2"; - - opp-200000000 { - opp-hz =3D /bits/ 64 <200000000>; - opp-level =3D ; - }; - - opp-500000000 { - opp-hz =3D /bits/ 64 <500000000>; - opp-level =3D ; - }; - }; - }; - - gpucc: clock-controller@3d90000 { - compatible =3D "qcom,sc8280xp-gpucc"; - reg =3D <0 0x03d90000 0 0x9000>; - clocks =3D <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_GPU_GPLL0_CLK_SRC>, - <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; - clock-names =3D "bi_tcxo", - "gcc_gpu_gpll0_clk_src", - "gcc_gpu_gpll0_div_clk_src"; - - power-domains =3D <&rpmhpd SC8280XP_GFX>; - #clock-cells =3D <1>; - #reset-cells =3D <1>; - #power-domain-cells =3D <1>; - }; - - gpu_smmu: iommu@3da0000 { - compatible =3D "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu", - "qcom,smmu-500", "arm,mmu-500"; - reg =3D <0 0x03da0000 0 0x20000>; - #iommu-cells =3D <2>; - #global-interrupts =3D <2>; - interrupts =3D , - , - , - , - , - , - , - , - , - , - , - , - , - ; - - clocks =3D <&gcc GCC_GPU_MEMNOC_GFX_CLK>, - <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, - <&gpucc GPU_CC_AHB_CLK>, - <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, - <&gpucc GPU_CC_CX_GMU_CLK>, - <&gpucc GPU_CC_HUB_CX_INT_CLK>, - <&gpucc GPU_CC_HUB_AON_CLK>; - clock-names =3D "gcc_gpu_memnoc_gfx_clk", - "gcc_gpu_snoc_dvm_gfx_clk", - "gpu_cc_ahb_clk", - "gpu_cc_hlos1_vote_gpu_smmu_clk", - "gpu_cc_cx_gmu_clk", - "gpu_cc_hub_cx_int_clk", - "gpu_cc_hub_aon_clk"; - - power-domains =3D <&gpucc GPU_CC_CX_GDSC>; - dma-coherent; - }; - - usb_0_hsphy: phy@88e5000 { - compatible =3D "qcom,sc8280xp-usb-hs-phy", - "qcom,usb-snps-hs-5nm-phy"; - reg =3D <0 0x088e5000 0 0x400>; - clocks =3D <&rpmhcc RPMH_CXO_CLK>; - clock-names =3D "ref"; - resets =3D <&gcc GCC_QUSB2PHY_PRIM_BCR>; - - #phy-cells =3D <0>; - - status =3D "disabled"; - }; - - usb_2_hsphy0: phy@88e7000 { - compatible =3D "qcom,sc8280xp-usb-hs-phy", - "qcom,usb-snps-hs-5nm-phy"; - reg =3D <0 0x088e7000 0 0x400>; - clocks =3D <&gcc GCC_USB2_HS0_CLKREF_CLK>; - clock-names =3D "ref"; - resets =3D <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; - - #phy-cells =3D <0>; - - status =3D "disabled"; - }; - - usb_2_hsphy1: phy@88e8000 { - compatible =3D "qcom,sc8280xp-usb-hs-phy", - "qcom,usb-snps-hs-5nm-phy"; - reg =3D <0 0x088e8000 0 0x400>; - clocks =3D <&gcc GCC_USB2_HS1_CLKREF_CLK>; - clock-names =3D "ref"; - resets =3D <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; - - #phy-cells =3D <0>; - - status =3D "disabled"; - }; - - usb_2_hsphy2: phy@88e9000 { - compatible =3D "qcom,sc8280xp-usb-hs-phy", - "qcom,usb-snps-hs-5nm-phy"; - reg =3D <0 0x088e9000 0 0x400>; - clocks =3D <&gcc GCC_USB2_HS2_CLKREF_CLK>; - clock-names =3D "ref"; - resets =3D <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; - - #phy-cells =3D <0>; - - status =3D "disabled"; - }; - - usb_2_hsphy3: phy@88ea000 { - compatible =3D "qcom,sc8280xp-usb-hs-phy", - "qcom,usb-snps-hs-5nm-phy"; - reg =3D <0 0x088ea000 0 0x400>; - clocks =3D <&gcc GCC_USB2_HS3_CLKREF_CLK>; - clock-names =3D "ref"; - resets =3D <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; - - #phy-cells =3D <0>; - - status =3D "disabled"; - }; - - usb_2_qmpphy0: phy@88ef000 { - compatible =3D "qcom,sc8280xp-qmp-usb3-uni-phy"; - reg =3D <0 0x088ef000 0 0x2000>; - - clocks =3D <&gcc GCC_USB3_MP_PHY_AUX_CLK>, - <&gcc GCC_USB3_MP0_CLKREF_CLK>, - <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, - <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; - clock-names =3D "aux", "ref", "com_aux", "pipe"; - - resets =3D <&gcc GCC_USB3_UNIPHY_MP0_BCR>, - <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; - reset-names =3D "phy", "phy_phy"; - - power-domains =3D <&gcc USB30_MP_GDSC>; - - #clock-cells =3D <0>; - clock-output-names =3D "usb2_phy0_pipe_clk"; - - #phy-cells =3D <0>; - - status =3D "disabled"; - }; - - usb_2_qmpphy1: phy@88f1000 { - compatible =3D "qcom,sc8280xp-qmp-usb3-uni-phy"; - reg =3D <0 0x088f1000 0 0x2000>; - - clocks =3D <&gcc GCC_USB3_MP_PHY_AUX_CLK>, - <&gcc GCC_USB3_MP1_CLKREF_CLK>, - <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, - <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; - clock-names =3D "aux", "ref", "com_aux", "pipe"; - - resets =3D <&gcc GCC_USB3_UNIPHY_MP1_BCR>, - <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; - reset-names =3D "phy", "phy_phy"; - - power-domains =3D <&gcc USB30_MP_GDSC>; - - #clock-cells =3D <0>; - clock-output-names =3D "usb2_phy1_pipe_clk"; - - #phy-cells =3D <0>; - - status =3D "disabled"; - }; - remoteproc_adsp: remoteproc@3000000 { compatible =3D "qcom,sc8280xp-adsp-pas"; reg =3D <0 0x03000000 0 0x10000>; @@ -3166,6 +2879,180 @@ lpasscc: clock-controller@33e0000 { #reset-cells =3D <1>; }; =20 + gpu: gpu@3d00000 { + compatible =3D "qcom,adreno-690.0", "qcom,adreno"; + + reg =3D <0 0x03d00000 0 0x40000>, + <0 0x03d9e000 0 0x1000>, + <0 0x03d61000 0 0x800>; + reg-names =3D "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + interrupts =3D ; + iommus =3D <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>; + operating-points-v2 =3D <&gpu_opp_table>; + + qcom,gmu =3D <&gmu>; + interconnects =3D <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "gfx-mem"; + #cooling-cells =3D <2>; + + status =3D "disabled"; + + gpu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-270000000 { + opp-hz =3D /bits/ 64 <270000000>; + opp-level =3D ; + opp-peak-kBps =3D <451000>; + }; + + opp-410000000 { + opp-hz =3D /bits/ 64 <410000000>; + opp-level =3D ; + opp-peak-kBps =3D <1555000>; + }; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + opp-level =3D ; + opp-peak-kBps =3D <1555000>; + }; + + opp-547000000 { + opp-hz =3D /bits/ 64 <547000000>; + opp-level =3D ; + opp-peak-kBps =3D <1555000>; + }; + + opp-606000000 { + opp-hz =3D /bits/ 64 <606000000>; + opp-level =3D ; + opp-peak-kBps =3D <2736000>; + }; + + opp-640000000 { + opp-hz =3D /bits/ 64 <640000000>; + opp-level =3D ; + opp-peak-kBps =3D <2736000>; + }; + + opp-655000000 { + opp-hz =3D /bits/ 64 <655000000>; + opp-level =3D ; + opp-peak-kBps =3D <2736000>; + }; + + opp-690000000 { + opp-hz =3D /bits/ 64 <690000000>; + opp-level =3D ; + opp-peak-kBps =3D <2736000>; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible =3D "qcom,adreno-gmu-690.0", "qcom,adreno-gmu"; + reg =3D <0 0x03d6a000 0 0x34000>, + <0 0x03de0000 0 0x10000>, + <0 0x0b290000 0 0x10000>; + reg-names =3D "gmu", "rscc", "gmu_pdc"; + interrupts =3D , + ; + interrupt-names =3D "hfi", "gmu"; + clocks =3D <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names =3D "gmu", + "cxo", + "axi", + "memnoc", + "ahb", + "hub", + "smmu_vote"; + power-domains =3D <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_GX_GDSC>; + power-domain-names =3D "cx", + "gx"; + iommus =3D <&gpu_smmu 5 0xc00>; + operating-points-v2 =3D <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + opp-level =3D ; + }; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + opp-level =3D ; + }; + }; + }; + + gpucc: clock-controller@3d90000 { + compatible =3D "qcom,sc8280xp-gpucc"; + reg =3D <0 0x03d90000 0 0x9000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names =3D "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + + power-domains =3D <&rpmhpd SC8280XP_GFX>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + gpu_smmu: iommu@3da0000 { + compatible =3D "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0 0x03da0000 0 0x20000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <2>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + clocks =3D <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>; + clock-names =3D "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk", + "gpu_cc_hlos1_vote_gpu_smmu_clk", + "gpu_cc_cx_gmu_clk", + "gpu_cc_hub_cx_int_clk", + "gpu_cc_hub_aon_clk"; + + power-domains =3D <&gpucc GPU_CC_CX_GDSC>; + dma-coherent; + }; + sdc2: mmc@8804000 { compatible =3D "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0 0x08804000 0 0x1000>; @@ -3209,6 +3096,71 @@ opp-202000000 { }; }; =20 + usb_0_hsphy: phy@88e5000 { + compatible =3D "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg =3D <0 0x088e5000 0 0x400>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "ref"; + resets =3D <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_2_hsphy0: phy@88e7000 { + compatible =3D "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg =3D <0 0x088e7000 0 0x400>; + clocks =3D <&gcc GCC_USB2_HS0_CLKREF_CLK>; + clock-names =3D "ref"; + resets =3D <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_2_hsphy1: phy@88e8000 { + compatible =3D "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg =3D <0 0x088e8000 0 0x400>; + clocks =3D <&gcc GCC_USB2_HS1_CLKREF_CLK>; + clock-names =3D "ref"; + resets =3D <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_2_hsphy2: phy@88e9000 { + compatible =3D "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg =3D <0 0x088e9000 0 0x400>; + clocks =3D <&gcc GCC_USB2_HS2_CLKREF_CLK>; + clock-names =3D "ref"; + resets =3D <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_2_hsphy3: phy@88ea000 { + compatible =3D "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg =3D <0 0x088ea000 0 0x400>; + clocks =3D <&gcc GCC_USB2_HS3_CLKREF_CLK>; + clock-names =3D "ref"; + resets =3D <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + usb_0_qmpphy: phy@88eb000 { compatible =3D "qcom,sc8280xp-qmp-usb43dp-phy"; reg =3D <0 0x088eb000 0 0x4000>; @@ -3256,6 +3208,54 @@ port@2 { }; }; =20 + usb_2_qmpphy0: phy@88ef000 { + compatible =3D "qcom,sc8280xp-qmp-usb3-uni-phy"; + reg =3D <0 0x088ef000 0 0x2000>; + + clocks =3D <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&gcc GCC_USB3_MP0_CLKREF_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; + clock-names =3D "aux", "ref", "com_aux", "pipe"; + + resets =3D <&gcc GCC_USB3_UNIPHY_MP0_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; + reset-names =3D "phy", "phy_phy"; + + power-domains =3D <&gcc USB30_MP_GDSC>; + + #clock-cells =3D <0>; + clock-output-names =3D "usb2_phy0_pipe_clk"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_2_qmpphy1: phy@88f1000 { + compatible =3D "qcom,sc8280xp-qmp-usb3-uni-phy"; + reg =3D <0 0x088f1000 0 0x2000>; + + clocks =3D <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&gcc GCC_USB3_MP1_CLKREF_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; + clock-names =3D "aux", "ref", "com_aux", "pipe"; + + resets =3D <&gcc GCC_USB3_UNIPHY_MP1_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; + reset-names =3D "phy", "phy_phy"; + + power-domains =3D <&gcc USB30_MP_GDSC>; + + #clock-cells =3D <0>; + clock-output-names =3D "usb2_phy1_pipe_clk"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + usb_1_hsphy: phy@8902000 { compatible =3D "qcom,sc8280xp-usb-hs-phy", "qcom,usb-snps-hs-5nm-phy"; --=20 2.49.0