From nobody Fri Dec 19 17:19:50 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE37F20E005; Sat, 17 May 2025 17:28:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747502884; cv=none; b=Sn+ZRRtIL4+a6sCTeGeLv0kEEByGiFlW5y5ehxWm64DDAgnF9GJdp7UP+EHahYN68onOlPGEHd8an64/e9SoUxkPN3FKz1K6HBh+o+sysL9S8UJ2o/GDjpLPii9mVhgzbdD+3/MaPvHCrBrD5ZtWY8UlBBwdVwV7VRcA6QvOTRI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747502884; c=relaxed/simple; bh=xzvM4v6bV7S7ZbZ4VakF5vvCatxUM3MT1eDZFcVMSjY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fl8wgU7A4ARYDHpLh/jDFE6WPD+1dwWWThkCZTEOuC8d8F3tZXB6llcpgR5GchejPFqdTHJNZN6e3QfmFDgoapupfdkPcf52PfCIfv58kDJLdBd+p3dSv1ObBkfYUon7Qul6Zf7cB+ORF8jPo9QkhjxUGIoPIqSJT8ldlSmgkWY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=F/OeTPDP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="F/OeTPDP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E6EC6C4CEEA; Sat, 17 May 2025 17:27:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747502884; bh=xzvM4v6bV7S7ZbZ4VakF5vvCatxUM3MT1eDZFcVMSjY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=F/OeTPDPELHfIZdsr4eIuoZOS+TlyuSoRRsAVdVEADxUHTNnqwQ6pOgJ6A++ILhWW gYnxK5HgKTUfcwhqAKgJU2JBEw7jLy3j81Po230LHbyt/4w/ZRbPNQ/THZDYNsa8fy CI4M8LXpP+eFqrMj1ljALgS4mEbXxLGHTEK/67cQicU+ljivYMcsGNJ+LHERo1n2VK a93+qibRv2zlH6znT6WxlRsSP/Z0CVtTsN+IVoKqINNcE0f/0qHJhvBsoLZtAcXMiU mS8WSEtfwzbxsM4cYYlFTW29iDiJ11fTVyD/+LP9cVZzNuub1aTHtS920nW2mbBSir zheEPtYBBsrFw== From: Konrad Dybcio Date: Sat, 17 May 2025 19:27:50 +0200 Subject: [PATCH v2 1/5] dt-bindings: remoteproc: qcom,sm8350-pas: Add SC8280XP Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250517-topic-8280_slpi-v2-1-1f96f86ac3ae@oss.qualcomm.com> References: <20250517-topic-8280_slpi-v2-0-1f96f86ac3ae@oss.qualcomm.com> In-Reply-To: <20250517-topic-8280_slpi-v2-0-1f96f86ac3ae@oss.qualcomm.com> To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Konrad Dybcio Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747502874; l=2866; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=luJWRq4V76R/ttAeoDO+p77i20LzK96hYKCcFunW7aM=; b=HNayJ0TgitkDtJk3ubt45tvpeysaEKCdT7EwYGGakNXVlefVW8l3cgsjkCw0o+Bwphw22CIwO aAT7xSlqevIDigEzltFpTT7BI6HBizTefKuh9gJPbDGQ+T/71k6mXLE X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio From the software POV, it matches the SM8350's implementation. Describe it as such, with a fallback. Signed-off-by: Konrad Dybcio --- .../bindings/remoteproc/qcom,sm8350-pas.yaml | 54 ++++++++++++------= ---- 1 file changed, 30 insertions(+), 24 deletions(-) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.y= aml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml index fd3423e6051bc8bb0e783479360a7b38e5fa1358..6d09823153fc8331f04d4657d9a= cba718533cce6 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml @@ -15,16 +15,20 @@ description: =20 properties: compatible: - enum: - - qcom,sar2130p-adsp-pas - - qcom,sm8350-adsp-pas - - qcom,sm8350-cdsp-pas - - qcom,sm8350-slpi-pas - - qcom,sm8350-mpss-pas - - qcom,sm8450-adsp-pas - - qcom,sm8450-cdsp-pas - - qcom,sm8450-mpss-pas - - qcom,sm8450-slpi-pas + oneOf: + - enum: + - qcom,sar2130p-adsp-pas + - qcom,sm8350-adsp-pas + - qcom,sm8350-cdsp-pas + - qcom,sm8350-slpi-pas + - qcom,sm8350-mpss-pas + - qcom,sm8450-adsp-pas + - qcom,sm8450-cdsp-pas + - qcom,sm8450-mpss-pas + - qcom,sm8450-slpi-pas + - items: + - const: qcom,sc8280xp-slpi-pas + - const: qcom,sm8350-slpi-pas =20 reg: maxItems: 1 @@ -61,14 +65,15 @@ allOf: - if: properties: compatible: - enum: - - qcom,sar2130p-adsp-pas - - qcom,sm8350-adsp-pas - - qcom,sm8350-cdsp-pas - - qcom,sm8350-slpi-pas - - qcom,sm8450-adsp-pas - - qcom,sm8450-cdsp-pas - - qcom,sm8450-slpi-pas + contains: + enum: + - qcom,sar2130p-adsp-pas + - qcom,sm8350-adsp-pas + - qcom,sm8350-cdsp-pas + - qcom,sm8350-slpi-pas + - qcom,sm8450-adsp-pas + - qcom,sm8450-cdsp-pas + - qcom,sm8450-slpi-pas then: properties: interrupts: @@ -102,12 +107,13 @@ allOf: - if: properties: compatible: - enum: - - qcom,sar2130p-adsp-pas - - qcom,sm8350-adsp-pas - - qcom,sm8350-slpi-pas - - qcom,sm8450-adsp-pas - - qcom,sm8450-slpi-pas + contains: + enum: + - qcom,sar2130p-adsp-pas + - qcom,sm8350-adsp-pas + - qcom,sm8350-slpi-pas + - qcom,sm8450-adsp-pas + - qcom,sm8450-slpi-pas then: properties: power-domains: --=20 2.49.0 From nobody Fri Dec 19 17:19:50 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6704720D4EB; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="a7ZUWE15" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BA14DC4CEE3; Sat, 17 May 2025 17:28:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747502888; bh=062RmATaJHg1+JNK3SlnDQyFrSpSj7KSwC8nySXa7Pc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=a7ZUWE153k51Y3ZONtbzmYyMT6oS5nfTRYwN9dcZ0hjp1vY15tcvjNKrCfG87kY44 pead8zabmO0dGWuYVnppHec758XBJamtacWXzPBHgRE9ji3dAb7PNjYUQ4dHFa/Il/ xypkNk+8cM6Y2yqSLDspQsAUA/DjsJkMDS6loQgDLVpm2N1j3cJwBGwsjoO8hHPwUQ T/kJ/MbDma/vHfpukRcFlPM0Dmoqp7NfTCELp13LcPE8BJ6Kc62qdmN3/SLgYtxAYl FpwYVSQL+BS+lSf/GJ315Rv88jI8lElFXNJb0hPsi49df44V8NR+Nz4/VuBRm0hbE7 s/R40BaF2cUjA== From: Konrad Dybcio Date: Sat, 17 May 2025 19:27:51 +0200 Subject: [PATCH v2 2/5] arm64: dts: qcom: sc8280xp: Fix node order Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250517-topic-8280_slpi-v2-2-1f96f86ac3ae@oss.qualcomm.com> References: <20250517-topic-8280_slpi-v2-0-1f96f86ac3ae@oss.qualcomm.com> In-Reply-To: <20250517-topic-8280_slpi-v2-0-1f96f86ac3ae@oss.qualcomm.com> To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Konrad Dybcio Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747502874; l=17883; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=o4vvJe+dKVC6zH1d9tYG5Y4ze0AndgFi2VUDuEHKxRE=; b=seT+cxW7EX1gxNDzR3NVPBjioADlz90m2JO4B3M83YDlYNN5EeBQgXswa8p4GlhsrSxkOYCKH O3ycyNtPZdHBz6Kb2XPJ7MfakPSEI7VfnzNxklGKo/hPNjiUZpLeoC5 X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Certain /soc@0 subnodes are very out of order. Reshuffle them. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 574 ++++++++++++++++-------------= ---- 1 file changed, 287 insertions(+), 287 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 27d21e1a2d50c6fc12f324ab2b4dfa4b99791b81..94dcbccca62e992030bcdd6eb3b= c3fcd879c1e8a 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2454,293 +2454,6 @@ tcsr: syscon@1fc0000 { reg =3D <0x0 0x01fc0000 0x0 0x30000>; }; =20 - gpu: gpu@3d00000 { - compatible =3D "qcom,adreno-690.0", "qcom,adreno"; - - reg =3D <0 0x03d00000 0 0x40000>, - <0 0x03d9e000 0 0x1000>, - <0 0x03d61000 0 0x800>; - reg-names =3D "kgsl_3d0_reg_memory", - "cx_mem", - "cx_dbgc"; - interrupts =3D ; - iommus =3D <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>; - operating-points-v2 =3D <&gpu_opp_table>; - - qcom,gmu =3D <&gmu>; - interconnects =3D <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names =3D "gfx-mem"; - #cooling-cells =3D <2>; - - status =3D "disabled"; - - gpu_opp_table: opp-table { - compatible =3D "operating-points-v2"; - - opp-270000000 { - opp-hz =3D /bits/ 64 <270000000>; - opp-level =3D ; - opp-peak-kBps =3D <451000>; - }; - - opp-410000000 { - opp-hz =3D /bits/ 64 <410000000>; - opp-level =3D ; - opp-peak-kBps =3D <1555000>; - }; - - opp-500000000 { - opp-hz =3D /bits/ 64 <500000000>; - opp-level =3D ; - opp-peak-kBps =3D <1555000>; - }; - - opp-547000000 { - opp-hz =3D /bits/ 64 <547000000>; - opp-level =3D ; - opp-peak-kBps =3D <1555000>; - }; - - opp-606000000 { - opp-hz =3D /bits/ 64 <606000000>; - opp-level =3D ; - opp-peak-kBps =3D <2736000>; - }; - - opp-640000000 { - opp-hz =3D /bits/ 64 <640000000>; - opp-level =3D ; - opp-peak-kBps =3D <2736000>; - }; - - opp-655000000 { - opp-hz =3D /bits/ 64 <655000000>; - opp-level =3D ; - opp-peak-kBps =3D <2736000>; - }; - - opp-690000000 { - opp-hz =3D /bits/ 64 <690000000>; - opp-level =3D ; - opp-peak-kBps =3D <2736000>; - }; - }; - }; - - gmu: gmu@3d6a000 { - compatible =3D "qcom,adreno-gmu-690.0", "qcom,adreno-gmu"; - reg =3D <0 0x03d6a000 0 0x34000>, - <0 0x03de0000 0 0x10000>, - <0 0x0b290000 0 0x10000>; - reg-names =3D "gmu", "rscc", "gmu_pdc"; - interrupts =3D , - ; - interrupt-names =3D "hfi", "gmu"; - clocks =3D <&gpucc GPU_CC_CX_GMU_CLK>, - <&gpucc GPU_CC_CXO_CLK>, - <&gcc GCC_DDRSS_GPU_AXI_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>, - <&gpucc GPU_CC_AHB_CLK>, - <&gpucc GPU_CC_HUB_CX_INT_CLK>, - <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; - clock-names =3D "gmu", - "cxo", - "axi", - "memnoc", - "ahb", - "hub", - "smmu_vote"; - power-domains =3D <&gpucc GPU_CC_CX_GDSC>, - <&gpucc GPU_CC_GX_GDSC>; - power-domain-names =3D "cx", - "gx"; - iommus =3D <&gpu_smmu 5 0xc00>; - operating-points-v2 =3D <&gmu_opp_table>; - - gmu_opp_table: opp-table { - compatible =3D "operating-points-v2"; - - opp-200000000 { - opp-hz =3D /bits/ 64 <200000000>; - opp-level =3D ; - }; - - opp-500000000 { - opp-hz =3D /bits/ 64 <500000000>; - opp-level =3D ; - }; - }; - }; - - gpucc: clock-controller@3d90000 { - compatible =3D "qcom,sc8280xp-gpucc"; - reg =3D <0 0x03d90000 0 0x9000>; - clocks =3D <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_GPU_GPLL0_CLK_SRC>, - <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; - clock-names =3D "bi_tcxo", - "gcc_gpu_gpll0_clk_src", - "gcc_gpu_gpll0_div_clk_src"; - - power-domains =3D <&rpmhpd SC8280XP_GFX>; - #clock-cells =3D <1>; - #reset-cells =3D <1>; - #power-domain-cells =3D <1>; - }; - - gpu_smmu: iommu@3da0000 { - compatible =3D "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu", - "qcom,smmu-500", "arm,mmu-500"; - reg =3D <0 0x03da0000 0 0x20000>; - #iommu-cells =3D <2>; - #global-interrupts =3D <2>; - interrupts =3D , - , - , - , - , - , - , - , - , - , - , - , - , - ; - - clocks =3D <&gcc GCC_GPU_MEMNOC_GFX_CLK>, - <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, - <&gpucc GPU_CC_AHB_CLK>, - <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, - <&gpucc GPU_CC_CX_GMU_CLK>, - <&gpucc GPU_CC_HUB_CX_INT_CLK>, - <&gpucc GPU_CC_HUB_AON_CLK>; - clock-names =3D "gcc_gpu_memnoc_gfx_clk", - "gcc_gpu_snoc_dvm_gfx_clk", - "gpu_cc_ahb_clk", - "gpu_cc_hlos1_vote_gpu_smmu_clk", - "gpu_cc_cx_gmu_clk", - "gpu_cc_hub_cx_int_clk", - "gpu_cc_hub_aon_clk"; - - power-domains =3D <&gpucc GPU_CC_CX_GDSC>; - dma-coherent; - }; - - usb_0_hsphy: phy@88e5000 { - compatible =3D "qcom,sc8280xp-usb-hs-phy", - "qcom,usb-snps-hs-5nm-phy"; - reg =3D <0 0x088e5000 0 0x400>; - clocks =3D <&rpmhcc RPMH_CXO_CLK>; - clock-names =3D "ref"; - resets =3D <&gcc GCC_QUSB2PHY_PRIM_BCR>; - - #phy-cells =3D <0>; - - status =3D "disabled"; - }; - - usb_2_hsphy0: phy@88e7000 { - compatible =3D "qcom,sc8280xp-usb-hs-phy", - "qcom,usb-snps-hs-5nm-phy"; - reg =3D <0 0x088e7000 0 0x400>; - clocks =3D <&gcc GCC_USB2_HS0_CLKREF_CLK>; - clock-names =3D "ref"; - resets =3D <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; - - #phy-cells =3D <0>; - - status =3D "disabled"; - }; - - usb_2_hsphy1: phy@88e8000 { - compatible =3D "qcom,sc8280xp-usb-hs-phy", - "qcom,usb-snps-hs-5nm-phy"; - reg =3D <0 0x088e8000 0 0x400>; - clocks =3D <&gcc GCC_USB2_HS1_CLKREF_CLK>; - clock-names =3D "ref"; - resets =3D <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; - - #phy-cells =3D <0>; - - status =3D "disabled"; - }; - - usb_2_hsphy2: phy@88e9000 { - compatible =3D "qcom,sc8280xp-usb-hs-phy", - "qcom,usb-snps-hs-5nm-phy"; - reg =3D <0 0x088e9000 0 0x400>; - clocks =3D <&gcc GCC_USB2_HS2_CLKREF_CLK>; - clock-names =3D "ref"; - resets =3D <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; - - #phy-cells =3D <0>; - - status =3D "disabled"; - }; - - usb_2_hsphy3: phy@88ea000 { - compatible =3D "qcom,sc8280xp-usb-hs-phy", - "qcom,usb-snps-hs-5nm-phy"; - reg =3D <0 0x088ea000 0 0x400>; - clocks =3D <&gcc GCC_USB2_HS3_CLKREF_CLK>; - clock-names =3D "ref"; - resets =3D <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; - - #phy-cells =3D <0>; - - status =3D "disabled"; - }; - - usb_2_qmpphy0: phy@88ef000 { - compatible =3D "qcom,sc8280xp-qmp-usb3-uni-phy"; - reg =3D <0 0x088ef000 0 0x2000>; - - clocks =3D <&gcc GCC_USB3_MP_PHY_AUX_CLK>, - <&gcc GCC_USB3_MP0_CLKREF_CLK>, - <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, - <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; - clock-names =3D "aux", "ref", "com_aux", "pipe"; - - resets =3D <&gcc GCC_USB3_UNIPHY_MP0_BCR>, - <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; - reset-names =3D "phy", "phy_phy"; - - power-domains =3D <&gcc USB30_MP_GDSC>; - - #clock-cells =3D <0>; - clock-output-names =3D "usb2_phy0_pipe_clk"; - - #phy-cells =3D <0>; - - status =3D "disabled"; - }; - - usb_2_qmpphy1: phy@88f1000 { - compatible =3D "qcom,sc8280xp-qmp-usb3-uni-phy"; - reg =3D <0 0x088f1000 0 0x2000>; - - clocks =3D <&gcc GCC_USB3_MP_PHY_AUX_CLK>, - <&gcc GCC_USB3_MP1_CLKREF_CLK>, - <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, - <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; - clock-names =3D "aux", "ref", "com_aux", "pipe"; - - resets =3D <&gcc GCC_USB3_UNIPHY_MP1_BCR>, - <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; - reset-names =3D "phy", "phy_phy"; - - power-domains =3D <&gcc USB30_MP_GDSC>; - - #clock-cells =3D <0>; - clock-output-names =3D "usb2_phy1_pipe_clk"; - - #phy-cells =3D <0>; - - status =3D "disabled"; - }; - remoteproc_adsp: remoteproc@3000000 { compatible =3D "qcom,sc8280xp-adsp-pas"; reg =3D <0 0x03000000 0 0x10000>; @@ -3166,6 +2879,180 @@ lpasscc: clock-controller@33e0000 { #reset-cells =3D <1>; }; =20 + gpu: gpu@3d00000 { + compatible =3D "qcom,adreno-690.0", "qcom,adreno"; + + reg =3D <0 0x03d00000 0 0x40000>, + <0 0x03d9e000 0 0x1000>, + <0 0x03d61000 0 0x800>; + reg-names =3D "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + interrupts =3D ; + iommus =3D <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>; + operating-points-v2 =3D <&gpu_opp_table>; + + qcom,gmu =3D <&gmu>; + interconnects =3D <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "gfx-mem"; + #cooling-cells =3D <2>; + + status =3D "disabled"; + + gpu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-270000000 { + opp-hz =3D /bits/ 64 <270000000>; + opp-level =3D ; + opp-peak-kBps =3D <451000>; + }; + + opp-410000000 { + opp-hz =3D /bits/ 64 <410000000>; + opp-level =3D ; + opp-peak-kBps =3D <1555000>; + }; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + opp-level =3D ; + opp-peak-kBps =3D <1555000>; + }; + + opp-547000000 { + opp-hz =3D /bits/ 64 <547000000>; + opp-level =3D ; + opp-peak-kBps =3D <1555000>; + }; + + opp-606000000 { + opp-hz =3D /bits/ 64 <606000000>; + opp-level =3D ; + opp-peak-kBps =3D <2736000>; + }; + + opp-640000000 { + opp-hz =3D /bits/ 64 <640000000>; + opp-level =3D ; + opp-peak-kBps =3D <2736000>; + }; + + opp-655000000 { + opp-hz =3D /bits/ 64 <655000000>; + opp-level =3D ; + opp-peak-kBps =3D <2736000>; + }; + + opp-690000000 { + opp-hz =3D /bits/ 64 <690000000>; + opp-level =3D ; + opp-peak-kBps =3D <2736000>; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible =3D "qcom,adreno-gmu-690.0", "qcom,adreno-gmu"; + reg =3D <0 0x03d6a000 0 0x34000>, + <0 0x03de0000 0 0x10000>, + <0 0x0b290000 0 0x10000>; + reg-names =3D "gmu", "rscc", "gmu_pdc"; + interrupts =3D , + ; + interrupt-names =3D "hfi", "gmu"; + clocks =3D <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names =3D "gmu", + "cxo", + "axi", + "memnoc", + "ahb", + "hub", + "smmu_vote"; + power-domains =3D <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_GX_GDSC>; + power-domain-names =3D "cx", + "gx"; + iommus =3D <&gpu_smmu 5 0xc00>; + operating-points-v2 =3D <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + opp-level =3D ; + }; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + opp-level =3D ; + }; + }; + }; + + gpucc: clock-controller@3d90000 { + compatible =3D "qcom,sc8280xp-gpucc"; + reg =3D <0 0x03d90000 0 0x9000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names =3D "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + + power-domains =3D <&rpmhpd SC8280XP_GFX>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + gpu_smmu: iommu@3da0000 { + compatible =3D "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0 0x03da0000 0 0x20000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <2>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + clocks =3D <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>; + clock-names =3D "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk", + "gpu_cc_hlos1_vote_gpu_smmu_clk", + "gpu_cc_cx_gmu_clk", + "gpu_cc_hub_cx_int_clk", + "gpu_cc_hub_aon_clk"; + + power-domains =3D <&gpucc GPU_CC_CX_GDSC>; + dma-coherent; + }; + sdc2: mmc@8804000 { compatible =3D "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0 0x08804000 0 0x1000>; @@ -3209,6 +3096,71 @@ opp-202000000 { }; }; =20 + usb_0_hsphy: phy@88e5000 { + compatible =3D "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg =3D <0 0x088e5000 0 0x400>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "ref"; + resets =3D <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_2_hsphy0: phy@88e7000 { + compatible =3D "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg =3D <0 0x088e7000 0 0x400>; + clocks =3D <&gcc GCC_USB2_HS0_CLKREF_CLK>; + clock-names =3D "ref"; + resets =3D <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_2_hsphy1: phy@88e8000 { + compatible =3D "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg =3D <0 0x088e8000 0 0x400>; + clocks =3D <&gcc GCC_USB2_HS1_CLKREF_CLK>; + clock-names =3D "ref"; + resets =3D <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_2_hsphy2: phy@88e9000 { + compatible =3D "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg =3D <0 0x088e9000 0 0x400>; + clocks =3D <&gcc GCC_USB2_HS2_CLKREF_CLK>; + clock-names =3D "ref"; + resets =3D <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_2_hsphy3: phy@88ea000 { + compatible =3D "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg =3D <0 0x088ea000 0 0x400>; + clocks =3D <&gcc GCC_USB2_HS3_CLKREF_CLK>; + clock-names =3D "ref"; + resets =3D <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + usb_0_qmpphy: phy@88eb000 { compatible =3D "qcom,sc8280xp-qmp-usb43dp-phy"; reg =3D <0 0x088eb000 0 0x4000>; @@ -3256,6 +3208,54 @@ port@2 { }; }; =20 + usb_2_qmpphy0: phy@88ef000 { + compatible =3D "qcom,sc8280xp-qmp-usb3-uni-phy"; + reg =3D <0 0x088ef000 0 0x2000>; + + clocks =3D <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&gcc GCC_USB3_MP0_CLKREF_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; + clock-names =3D "aux", "ref", "com_aux", "pipe"; + + resets =3D <&gcc GCC_USB3_UNIPHY_MP0_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; + reset-names =3D "phy", "phy_phy"; + + power-domains =3D <&gcc USB30_MP_GDSC>; + + #clock-cells =3D <0>; + clock-output-names =3D "usb2_phy0_pipe_clk"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_2_qmpphy1: phy@88f1000 { + compatible =3D "qcom,sc8280xp-qmp-usb3-uni-phy"; + reg =3D <0 0x088f1000 0 0x2000>; + + clocks =3D <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&gcc GCC_USB3_MP1_CLKREF_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; + clock-names =3D "aux", "ref", "com_aux", "pipe"; + + resets =3D <&gcc GCC_USB3_UNIPHY_MP1_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; + reset-names =3D "phy", "phy_phy"; + + power-domains =3D <&gcc USB30_MP_GDSC>; + + #clock-cells =3D <0>; + clock-output-names =3D "usb2_phy1_pipe_clk"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + usb_1_hsphy: phy@8902000 { compatible =3D "qcom,sc8280xp-usb-hs-phy", "qcom,usb-snps-hs-5nm-phy"; --=20 2.49.0 From nobody Fri Dec 19 17:19:50 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A357621019E; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UZtAva41" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 59176C4CEF0; Sat, 17 May 2025 17:28:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747502893; bh=JVEQxDFr1oBoBMSgA9Z2WU+IEPU+6po+f3inf4JbNrI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=UZtAva41q4GAXA2HwnrOi5ktzOhaSYYT3YYMQU+supB9vKILFmS7SqQAJBANycOll TfLEFUywJ5VmAHQv0avZ+nHcsKhn2bCSKcrZurVXmTedmhB9bS1xR0zt0IAOSIO3py vnXqBN8ePRT+MZdEzlXjeLVFb8P+95OJpW7jWzSFmdr9yAd11evPuDrwp2Y2tT4BJD CWj8H2Dw4AsBlOz3w45uZUVsT3SIqR6+lH5Tq/93OUB4jVHQZSihWW6GG22AlJangL cH2XDFF4JwSxeTi086FdfSyiPI1szS37acgRQnpANdQKSP+TB4+QNN9X1PqwmJ8Seb dnxP1Y8kXdG2Q== From: Konrad Dybcio Date: Sat, 17 May 2025 19:27:52 +0200 Subject: [PATCH v2 3/5] arm64: dts: qcom: sc8280xp: Add SLPI Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250517-topic-8280_slpi-v2-3-1f96f86ac3ae@oss.qualcomm.com> References: <20250517-topic-8280_slpi-v2-0-1f96f86ac3ae@oss.qualcomm.com> In-Reply-To: <20250517-topic-8280_slpi-v2-0-1f96f86ac3ae@oss.qualcomm.com> To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Konrad Dybcio Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747502874; l=3655; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=NTpPYjRM1aEKBIJ6EFzGdjafUGuz3bdEpt2oY9zN99A=; b=9wUHo4STnGbHN1nj3RzhYrjAaDl5lpmzfnBkCqlFgtW2ZBEwFiPkLDHw7k2oiTcOG8LWFmEVI 8abX8B+WjciAG0jTGbwAojeIdjDgpIJfW70CtyBwlt31bh3fPdKD5hd X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio SC8280XP features a SLPI (Sensor Low Power Island) core. Describe it. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 99 ++++++++++++++++++++++++++++++= ++++ 1 file changed, 99 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 94dcbccca62e992030bcdd6eb3bc3fcd879c1e8a..87555a119d947dca75415675807= f7965b2f203ac 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -695,6 +695,11 @@ pil_adsp_mem: adsp-region@86c00000 { no-map; }; =20 + pil_slpi_mem: slpi-region@88c00000 { + reg =3D <0 0x88c00000 0 0x1500000>; + no-map; + }; + pil_nsp0_mem: cdsp0-region@8a100000 { reg =3D <0 0x8a100000 0 0x1e00000>; no-map; @@ -783,6 +788,30 @@ smp2p_nsp1_in: slave-kernel { }; }; =20 + smp2p-slpi { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <481>, <430>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_SLPI + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_SLPI + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <3>; + + smp2p_slpi_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_slpi_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + soc: soc@0 { compatible =3D "simple-bus"; #address-cells =3D <2>; @@ -2454,6 +2483,76 @@ tcsr: syscon@1fc0000 { reg =3D <0x0 0x01fc0000 0x0 0x30000>; }; =20 + remoteproc_slpi: remoteproc@2400000 { + compatible =3D "qcom,sc8280xp-slpi-pas", "qcom,sm8350-slpi-pas"; + reg =3D <0 0x02400000 0 0x10000>; + + interrupts-extended =3D <&pdc 9 IRQ_TYPE_EDGE_RISING>, + <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd SC8280XP_LCX>, + <&rpmhpd SC8280XP_LMX>; + power-domain-names =3D "lcx", "lmx"; + + memory-region =3D <&pil_slpi_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_slpi_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc IPCC_CLIENT_SLPI + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_SLPI + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label =3D "slpi"; + qcom,remote-pid =3D <3>; + + fastrpc { + compatible =3D "qcom,fastrpc"; + qcom,glink-channels =3D "fastrpcglink-apps-dsp"; + label =3D "sdsp"; + qcom,non-secure-domain; + #address-cells =3D <1>; + #size-cells =3D <0>; + + compute-cb@1 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <1>; + iommus =3D <&apps_smmu 0x0521 0x0>; + }; + + compute-cb@2 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <2>; + iommus =3D <&apps_smmu 0x0522 0x0>; + }; + + compute-cb@3 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <3>; + iommus =3D <&apps_smmu 0x0523 0x0>; + }; + }; + }; + }; + remoteproc_adsp: remoteproc@3000000 { compatible =3D "qcom,sc8280xp-adsp-pas"; reg =3D <0 0x03000000 0 0x10000>; --=20 2.49.0 From nobody Fri Dec 19 17:19:50 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BB2A1D54FA; Sat, 17 May 2025 17:28:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747502898; cv=none; b=JuoSO2SbY4VmL5qq/v63nyflCSGejWUkYfMFIpcthLJFRhkBm7kO9o/n5d7HZIUG4+RYcAVrAj+2LSK84xCHFDgRVeQr1o3M6IvwSWWiduERlqS9sFSVl/p3nlJqMEXLsONCrwyKXq1UyJ8pGSqy5FZjSh5TC/nhMxWOetmrm6s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747502898; c=relaxed/simple; bh=QXNhEHu2ar499BueqOxPMpoBZrKZEwfn1UQPRy130gk=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250517-topic-8280_slpi-v2-4-1f96f86ac3ae@oss.qualcomm.com> References: <20250517-topic-8280_slpi-v2-0-1f96f86ac3ae@oss.qualcomm.com> In-Reply-To: <20250517-topic-8280_slpi-v2-0-1f96f86ac3ae@oss.qualcomm.com> To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Konrad Dybcio Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747502874; l=933; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=tSOwtYnZZ0SyYAMbjuyBvUPHokHp58zplXRrov7im9o=; b=u3yjIFQufvVbezCszu4kedb9XMQMV0gzKNTDknaZEpa500ho3eaOKa+rv8+L7e8M0OtM2EBHR sS88c5/kzieC1l4JAuRe0B2Kjm1hxdqYBn3Mh5q7ym0ad+6CHLMJ9mi X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Dmitry Baryshkov Enable SLPI / Sensors DSP present on the SC8280XP platforms / Lenovo X13s laptop. Signed-off-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/a= rch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index d36fc1ebe50e8baf73e21bd571f716e0152aa624..ae7a275fd2236a2c71808b003fb= cb66687e6e45e 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -1175,6 +1175,12 @@ &remoteproc_nsp0 { status =3D "okay"; }; =20 +&remoteproc_slpi { + firmware-name =3D "qcom/sc8280xp/LENOVO/21BX/qcslpi8280.mbn"; + + status =3D "okay"; +}; + &rxmacro { status =3D "okay"; }; --=20 2.49.0 From nobody Fri Dec 19 17:19:50 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2326A20E700; Sat, 17 May 2025 17:28:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747502902; cv=none; b=nXzK2QJzt5xKL0Ent+CW/dw9Z9OIOxuMFpDG6QEgM0DS2zYJwcR+o+L2X6jxr+7cnZsdlVNpeRndyqSz/tderhfJhBmczM9NOYnWKVUFI+bTUaXqCYlmZWfMBqxQLF6LKEvL67+O3GOS6+sZEJrtY+uOvGI9Kkr0rchWUF6EaBg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747502902; c=relaxed/simple; bh=bFX99d4iDUfBKROlNQmRvgt2RP+a/LFomqFqS1jbu0I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PiHT/scLHRQDfvAyntjiE9I8myQBQGdWRfMZOdljed1BChiyl3dg9SorASZn4YMlzfidUufjUV1fvxMnrEGGJm2crxgMVcsR4LgDUyk2FxTh+BFIfYa0Mz81hljWMQ/r74VC9DC/iu5QGKKTOAcvJujkEfKWOlocYaLsj+dYJ9E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=LcualHrz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="LcualHrz" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4464CC4CEE3; Sat, 17 May 2025 17:28:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747502902; bh=bFX99d4iDUfBKROlNQmRvgt2RP+a/LFomqFqS1jbu0I=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=LcualHrzutnL8XGO4j7F32DLLaiGZyRVUE44I1SCBpw1I7eCZ9+FnYluVcNjHm2ic r2wf0VUGTqGW3NmNL/ajWipicTKjk5apvm0qEZKT0ZrX1w51uNjRkKWSQdpyYtzjzi TTJ8+gbTnLUbyyYNdos2TDs6MGXSuUiZUO6jOrly6kPhsHkGIKoty0Nq/8+fBkY6l5 MQYuswPvkQV2cCgfTxxSH6SKVysiV0tEK84cB12BVJ+j+gZ/iy7BToP0hKrOmfD72r 8MPXJehEpfe7A/ypA/oR2WgkHdTyevUKy0IlX0XPARegfGVBGFOT4T2Cqutzeo1dND lLm6FbGzrZ4ZA== From: Konrad Dybcio Date: Sat, 17 May 2025 19:27:54 +0200 Subject: [PATCH v2 5/5] arm64: dts: qcom: sc8280xp-crd: Enable SLPI Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250517-topic-8280_slpi-v2-5-1f96f86ac3ae@oss.qualcomm.com> References: <20250517-topic-8280_slpi-v2-0-1f96f86ac3ae@oss.qualcomm.com> In-Reply-To: <20250517-topic-8280_slpi-v2-0-1f96f86ac3ae@oss.qualcomm.com> To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Konrad Dybcio Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747502874; l=786; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=2wD84tJ8gt8pgUvujCw2PohRr6DpmIenOHQLwyQ9MuU=; b=IWLbbVPyTdtTzkwCrpCBhhIMOgyIDpw1RMjdrPri+hyUdSEgbY+jdeGYAlcXJrGAyICnW2+o6 6hDt7w/JEXYDuvaLwMiAR/PmNhdXUoyj2j3GwI0qVGBPxUQHXL/5ATD X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Enable the SLPI remoteproc and declare the firmware path. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dt= s/qcom/sc8280xp-crd.dts index c4a5828be9353de0e4215b71a78ed5ca8e4b6b8a..8e2c02497c05c10a3a5a43a6002= 467736a3b7f95 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -751,6 +751,12 @@ &remoteproc_nsp0 { status =3D "okay"; }; =20 +&remoteproc_slpi { + firmware-name =3D "qcom/sc8280xp/qcslpi8280.mbn"; + + status =3D "okay"; +}; + &sdc2 { pinctrl-0 =3D <&sdc2_default_state>; pinctrl-1 =3D <&sdc2_sleep_state>; --=20 2.49.0