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Fri, 16 May 2025 16:35:29 -0700 (PDT) Received: from danyaPC.localdomain ([192.145.30.107]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-328084ca251sm5952871fa.38.2025.05.16.16.35.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 May 2025 16:35:29 -0700 (PDT) From: Daniil Ryabov To: alexander.deucher@amd.com Cc: christian.koenig@amd.com, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Daniil Ryabov Subject: [PATCH] drm/amd/display: fix typo in comments Date: Sat, 17 May 2025 02:35:16 +0300 Message-ID: <20250516233516.29480-1-daniilryabov4@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Fix double 'u' in 'frequuency' Signed-off-by: Daniil Ryabov --- drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c b/drivers/gp= u/drm/amd/display/dc/basics/dce_calcs.c index 681799468..d897f8a30 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c @@ -1393,7 +1393,7 @@ static void calculate_bandwidth( if ((bw_mtn(data->dram_speed_change_margin, bw_int_to_fixed(0)) && b= w_ltn(data->dram_speed_change_margin, bw_int_to_fixed(9999)))) { /*determine the minimum dram clock change margin for each set of cl= ock frequencies*/ data->min_dram_speed_change_margin[i][j] =3D bw_min2(data->min_dram= _speed_change_margin[i][j], data->dram_speed_change_margin); - /*compute the maximum clock frequuency required for the dram clock = change at each set of clock frequencies*/ + /*compute the maximum clock frequency required for the dram clock c= hange at each set of clock frequencies*/ data->dispclk_required_for_dram_speed_change_pipe[i][j] =3D bw_max2= (bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->di= splay_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub= (bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_stat= e_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_li= ne_source_transfer_time[k][i][j]))), bw_div(bw_div(bw_mul(data->src_pixels_= for_last_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb= _write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(bw_sub(data->maximum_late= ncy_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_bur= st_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j])= , data->active_time[k])))); if ((bw_ltn(data->dispclk_required_for_dram_speed_change_pipe[i][j]= , vbios->high_voltage_max_dispclk))) { data->display_pstate_change_enable[k] =3D 1; @@ -1407,7 +1407,7 @@ static void calculate_bandwidth( if ((bw_mtn(data->dram_speed_change_margin, bw_int_to_fixed(0)) && b= w_ltn(data->dram_speed_change_margin, bw_int_to_fixed(9999)))) { /*determine the minimum dram clock change margin for each display p= ipe*/ data->min_dram_speed_change_margin[i][j] =3D bw_min2(data->min_dram= _speed_change_margin[i][j], data->dram_speed_change_margin); - /*compute the maximum clock frequuency required for the dram clock = change at each set of clock frequencies*/ + /*compute the maximum clock frequency required for the dram clock c= hange at each set of clock frequencies*/ data->dispclk_required_for_dram_speed_change_pipe[i][j] =3D bw_max2= (bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->di= splay_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub= (bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->n= bp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_ch= ange_line_source_transfer_time[k][i][j]), data->mcifwr_burst_time[i][j]))),= bw_div(bw_div(bw_mul(data->src_pixels_for_last_output_pixel[k], dceip->dis= play_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_add(= bw_sub(bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vb= ios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_sp= eed_change_line_source_transfer_time[k][i][j]), data->mcifwr_burst_time[i][= j]), data->active_time[k])))); if ((bw_ltn(data->dispclk_required_for_dram_speed_change_pipe[i][j]= , vbios->high_voltage_max_dispclk))) { data->display_pstate_change_enable[k] =3D 1; --=20 2.43.0