From nobody Fri Dec 19 20:12:12 2025 Received: from mxout3.routing.net (mxout3.routing.net [134.0.28.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3189027A444; Fri, 16 May 2025 18:02:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=134.0.28.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747418530; cv=none; b=sHCeFW+xkC0mfMmG2aDBxp1m/U1OO28gVZ2f7cccvhKSHr2CAAWOA0UxEimDJZ7TIwK9uMDpFu9O6uHFZXQrE8uVpypSI/4pzyFxhvAcaXz0yuXkall6cBs88GB3CTiJdsQgQpdRADw/W617mgr7gOfaCNxfYL3kSuL21EdawLM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747418530; c=relaxed/simple; bh=R9jK5mGO0iMsfsZZ0J6LovdZM+neosEMf09Sxm5GFdY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TexkS3rNTzC+PFVo6vQjNOQjSe+iaPCKY1rkS/NOLjlN3cTWfYlpzw0jVTksfu4Fsb3cuHU8PBh4gXqm7wYs8hdwYryMyquzAIJwPQPRF3motO+dRX2/mlzlUxerURCKB8OcqiBOFAtpOFXQZNQn1EFG4TD/TUGb8/CLV/urH5E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=fw-web.de; spf=pass smtp.mailfrom=fw-web.de; dkim=pass (1024-bit key) header.d=mailerdienst.de header.i=@mailerdienst.de header.b=TchpcRao; arc=none smtp.client-ip=134.0.28.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=fw-web.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fw-web.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mailerdienst.de header.i=@mailerdienst.de header.b="TchpcRao" Received: from mxbulk.masterlogin.de (unknown [192.168.10.85]) by mxout3.routing.net (Postfix) with ESMTP id 7F5CD60531; Fri, 16 May 2025 18:01:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailerdienst.de; s=20200217; t=1747418518; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yzhcuPLDSwh1mzz/nGqTSzBUSDaRDNpTMz/JFqw2TqY=; b=TchpcRaovpOmKZ4Q9J8MIbaUuOE8QKTYzba4otiKgUc3i6MQI77I3poCJhukV8JEpx7ZhG ht88CT1H71e5aYXCmrtlw35Hu46E79GJep4buUQ3EkU+TZ80smGipBCRsSd4rqlFE27VRz Wwzfk7t2XA1o4YjP6Ue2GWkiAJrZZmY= Received: from frank-u24.. (fttx-pool-157.180.226.139.bambit.de [157.180.226.139]) by mxbulk.masterlogin.de (Postfix) with ESMTPSA id 345941226C1; Fri, 16 May 2025 18:01:58 +0000 (UTC) From: Frank Wunderlich To: Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: Frank Wunderlich , =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Landen Chao , DENG Qingfang , Sean Wang , Daniel Golle , Lorenzo Bianconi , Felix Fietkau , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 09/14] arm64: dts: mediatek: mt7988: add switch node Date: Fri, 16 May 2025 20:01:40 +0200 Message-ID: <20250516180147.10416-11-linux@fw-web.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250516180147.10416-1-linux@fw-web.de> References: <20250516180147.10416-1-linux@fw-web.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Frank Wunderlich Add mt7988 builtin mt753x switch nodes. Signed-off-by: Daniel Golle Signed-off-by: Frank Wunderlich --- v2: - drop labels and led-function too (have to be in board) --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 153 ++++++++++++++++++++++ 1 file changed, 153 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dt= s/mediatek/mt7988a.dtsi index aa0947a555aa..f738a025b623 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -742,6 +742,159 @@ ethsys: clock-controller@15000000 { #reset-cells =3D <1>; }; =20 + switch: switch@15020000 { + compatible =3D "mediatek,mt7988-switch"; + reg =3D <0 0x15020000 0 0x8000>; + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + resets =3D <ðwarp MT7988_ETHWARP_RST_SWITCH>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + gsw_port0: port@0 { + reg =3D <0>; + phy-mode =3D "internal"; + phy-handle =3D <&gsw_phy0>; + }; + + gsw_port1: port@1 { + reg =3D <1>; + phy-mode =3D "internal"; + phy-handle =3D <&gsw_phy1>; + }; + + gsw_port2: port@2 { + reg =3D <2>; + phy-mode =3D "internal"; + phy-handle =3D <&gsw_phy2>; + }; + + gsw_port3: port@3 { + reg =3D <3>; + phy-mode =3D "internal"; + phy-handle =3D <&gsw_phy3>; + }; + + port@6 { + reg =3D <6>; + ethernet =3D <&gmac0>; + phy-mode =3D "internal"; + + fixed-link { + speed =3D <10000>; + full-duplex; + pause; + }; + }; + }; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + mediatek,pio =3D <&pio>; + + gsw_phy0: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + interrupts =3D <0>; + phy-mode =3D "internal"; + nvmem-cells =3D <&phy_calibration_p0>; + nvmem-cell-names =3D "phy-cal-data"; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + gsw_phy0_led0: led@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + gsw_phy0_led1: led@1 { + reg =3D <1>; + status =3D "disabled"; + }; + }; + }; + + gsw_phy1: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + interrupts =3D <1>; + phy-mode =3D "internal"; + nvmem-cells =3D <&phy_calibration_p1>; + nvmem-cell-names =3D "phy-cal-data"; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + gsw_phy1_led0: led@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + gsw_phy1_led1: led@1 { + reg =3D <1>; + status =3D "disabled"; + }; + }; + }; + + gsw_phy2: ethernet-phy@2 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <2>; + interrupts =3D <2>; + phy-mode =3D "internal"; + nvmem-cells =3D <&phy_calibration_p2>; + nvmem-cell-names =3D "phy-cal-data"; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + gsw_phy2_led0: led@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + gsw_phy2_led1: led@1 { + reg =3D <1>; + status =3D "disabled"; + }; + }; + }; + + gsw_phy3: ethernet-phy@3 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <3>; + interrupts =3D <3>; + phy-mode =3D "internal"; + nvmem-cells =3D <&phy_calibration_p3>; + nvmem-cell-names =3D "phy-cal-data"; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + gsw_phy3_led0: led@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + gsw_phy3_led1: led@1 { + reg =3D <1>; + status =3D "disabled"; + }; + }; + }; + }; + }; + ethwarp: clock-controller@15031000 { compatible =3D "mediatek,mt7988-ethwarp"; reg =3D <0 0x15031000 0 0x1000>; --=20 2.43.0