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(fttx-pool-157.180.226.139.bambit.de [157.180.226.139]) by mxbulk.masterlogin.de (Postfix) with ESMTPSA id CB6D41226F2; Fri, 16 May 2025 18:01:57 +0000 (UTC) From: Frank Wunderlich To: Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: Frank Wunderlich , =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Landen Chao , DENG Qingfang , Sean Wang , Daniel Golle , Lorenzo Bianconi , Felix Fietkau , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 08/14] arm64: dts: mediatek: mt7988: add basic ethernet-nodes Date: Fri, 16 May 2025 20:01:39 +0200 Message-ID: <20250516180147.10416-10-linux@fw-web.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250516180147.10416-1-linux@fw-web.de> References: <20250516180147.10416-1-linux@fw-web.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Frank Wunderlich Add basic ethernet related nodes. Mac1+2 needs pcs (sgmii+usxgmii) to work correctly which will be linked later when driver is merged. Signed-off-by: Daniel Golle Signed-off-by: Frank Wunderlich --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 124 +++++++++++++++++++++- 1 file changed, 121 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dt= s/mediatek/mt7988a.dtsi index 029699e4eb02..aa0947a555aa 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -680,7 +680,28 @@ xphyu3port0: usb-phy@11e13000 { }; }; =20 - clock-controller@11f40000 { + xfi_tphy0: phy@11f20000 { + compatible =3D "mediatek,mt7988-xfi-tphy"; + reg =3D <0 0x11f20000 0 0x10000>; + resets =3D <&watchdog 14>; + clocks =3D <&xfi_pll CLK_XFIPLL_PLL_EN>, + <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>; + clock-names =3D "xfipll", "topxtal"; + mediatek,usxgmii-performance-errata; + #phy-cells =3D <0>; + }; + + xfi_tphy1: phy@11f30000 { + compatible =3D "mediatek,mt7988-xfi-tphy"; + reg =3D <0 0x11f30000 0 0x10000>; + resets =3D <&watchdog 15>; + clocks =3D <&xfi_pll CLK_XFIPLL_PLL_EN>, + <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>; + clock-names =3D "xfipll", "topxtal"; + #phy-cells =3D <0>; + }; + + xfi_pll: clock-controller@11f40000 { compatible =3D "mediatek,mt7988-xfi-pll"; reg =3D <0 0x11f40000 0 0x1000>; resets =3D <&watchdog 16>; @@ -714,19 +735,116 @@ phy_calibration_p3: calib@97c { }; }; =20 - clock-controller@15000000 { + ethsys: clock-controller@15000000 { compatible =3D "mediatek,mt7988-ethsys", "syscon"; reg =3D <0 0x15000000 0 0x1000>; #clock-cells =3D <1>; #reset-cells =3D <1>; }; =20 - clock-controller@15031000 { + ethwarp: clock-controller@15031000 { compatible =3D "mediatek,mt7988-ethwarp"; reg =3D <0 0x15031000 0 0x1000>; #clock-cells =3D <1>; #reset-cells =3D <1>; }; + + eth: ethernet@15100000 { + compatible =3D "mediatek,mt7988-eth"; + reg =3D <0 0x15100000 0 0x80000>, + <0 0x15400000 0 0x200000>; + interrupts =3D , + , + , + ; + clocks =3D <ðsys CLK_ETHDMA_CRYPT0_EN>, + <ðsys CLK_ETHDMA_FE_EN>, + <ðsys CLK_ETHDMA_GP2_EN>, + <ðsys CLK_ETHDMA_GP1_EN>, + <ðsys CLK_ETHDMA_GP3_EN>, + <ðwarp CLK_ETHWARP_WOCPU2_EN>, + <ðwarp CLK_ETHWARP_WOCPU1_EN>, + <ðwarp CLK_ETHWARP_WOCPU0_EN>, + <ðsys CLK_ETHDMA_ESW_EN>, + <&topckgen CLK_TOP_ETH_GMII_SEL>, + <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>, + <&topckgen CLK_TOP_ETH_SYS_200M_SEL>, + <&topckgen CLK_TOP_ETH_SYS_SEL>, + <&topckgen CLK_TOP_ETH_XGMII_SEL>, + <&topckgen CLK_TOP_ETH_MII_SEL>, + <&topckgen CLK_TOP_NETSYS_SEL>, + <&topckgen CLK_TOP_NETSYS_500M_SEL>, + <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>, + <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>, + <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>, + <&topckgen CLK_TOP_NETSYS_WARP_SEL>, + <ðsys CLK_ETHDMA_XGP1_EN>, + <ðsys CLK_ETHDMA_XGP2_EN>, + <ðsys CLK_ETHDMA_XGP3_EN>; + clock-names =3D "crypto", "fe", "gp2", "gp1", + "gp3", + "ethwarp_wocpu2", "ethwarp_wocpu1", + "ethwarp_wocpu0", "esw", "top_eth_gmii_sel", + "top_eth_refck_50m_sel", "top_eth_sys_200m_sel", + "top_eth_sys_sel", "top_eth_xgmii_sel", + "top_eth_mii_sel", "top_netsys_sel", + "top_netsys_500m_sel", "top_netsys_pao_2x_sel", + "top_netsys_sync_250m_sel", + "top_netsys_ppefb_250m_sel", + "top_netsys_warp_sel","xgp1", "xgp2", "xgp3"; + assigned-clocks =3D <&topckgen CLK_TOP_NETSYS_2X_SEL>, + <&topckgen CLK_TOP_NETSYS_GSW_SEL>, + <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, + <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>, + <&topckgen CLK_TOP_SGM_0_SEL>, + <&topckgen CLK_TOP_SGM_1_SEL>; + assigned-clock-parents =3D <&apmixedsys CLK_APMIXED_NET2PLL>, + <&topckgen CLK_TOP_NET1PLL_D4>, + <&topckgen CLK_TOP_NET1PLL_D8_D4>, + <&topckgen CLK_TOP_NET1PLL_D8_D4>, + <&apmixedsys CLK_APMIXED_SGMPLL>, + <&apmixedsys CLK_APMIXED_SGMPLL>; + mediatek,ethsys =3D <ðsys>; + mediatek,infracfg =3D <&topmisc>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + gmac0: mac@0 { + compatible =3D "mediatek,eth-mac"; + reg =3D <0>; + phy-mode =3D "internal"; + + fixed-link { + speed =3D <10000>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible =3D "mediatek,eth-mac"; + reg =3D <1>; + status =3D "disabled"; + }; + + gmac2: mac@2 { + compatible =3D "mediatek,eth-mac"; + reg =3D <2>; + status =3D "disabled"; + }; + + mdio_bus: mdio-bus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* internal 2.5G PHY */ + int_2p5g_phy: ethernet-phy@f { + reg =3D <15>; + compatible =3D "ethernet-phy-ieee802.3-c45"; + phy-mode =3D "internal"; + }; + }; + }; }; =20 thermal-zones { --=20 2.43.0