From nobody Sun Feb 8 12:16:16 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67A4C22F76B; Fri, 16 May 2025 08:26:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747384019; cv=none; b=icLpSZZeF1E/igxzr3OE4i6bbEaki/77IpWhssUGH9iSIy+kqhInjyY6ok7NtNw3pZ4Su8SJr4P9aN+tenQ3UPW9rYO+OXMVY/H35TDUxN3v9lXKz5x8GF3qmqJv+wL/XUj/nzu+GQzyJxuCCM5qnqsOh5q8KKLuk9Vk1MDlga8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747384019; c=relaxed/simple; bh=lib1A3fpAPB6sNPrna+P3DEECD5SGvBlQArEINqypvA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XoZpqK3AmLn/Agw8HPMqlOESixrXyQp+to+F6z5QAmka5IpD/Wl1DbF1URJJQr8+j8PuUjq2FpYFrtw42r2EonHswIO0Vv407eah7AV0YUtpBgwaGMcSncX7hwRy3HRbuK9OrHLT68QM99QBQGibNCH5Rcd4AW/fJM8kw3AowU4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=h4I9sFdc; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="h4I9sFdc" Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54G5JnqG001902; Fri, 16 May 2025 04:26:55 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=G5SC+ iL8EE9QF2Yd6uESGIy2p4vjU9Xlu1NE0m7I33g=; b=h4I9sFdcVRyDk2H9Hj857 IG5UUqzJl/DxQt7oK3HoWS8oX0rhOMh0SLWHwhkFtqOuIdJc485e46S3tK+eMRGz 9yjkHAHD3y+IrCb7eAtKB4TfV81dwdPLYVr2K3LPboiD9qRvmOIUE2acd/MS/NNN ULW80FwilYAyA6Q5fcC8esDD/03/+3T8WkIBco/9Kfa87lhzYNVlOMTegL5sH00k JC9BIaPsMK1imy8qq2tzJsiE9Mfrvn5RInGyo1VVyT7lCODWa2MN7wHvVH03nAAo Fta5SEzkrx3UMv2LNa/guZKUoDs2rTp9AO1ODfxFwMx3h1RAMVAq8K77zfkofKYD A== Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 46ny4a8qjg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 May 2025 04:26:53 -0400 (EDT) Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 54G8Qj2e033591 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 16 May 2025 04:26:45 -0400 Received: from ASHBCASHYB5.ad.analog.com (10.64.17.133) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 16 May 2025 04:26:44 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBCASHYB5.ad.analog.com (10.64.17.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 16 May 2025 04:26:44 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Fri, 16 May 2025 04:26:44 -0400 Received: from amiclaus-VirtualBox.ad.analog.com (AMICLAUS-L02.ad.analog.com [10.48.65.120]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 54G8QZwf031549; Fri, 16 May 2025 04:26:41 -0400 From: Antoniu Miclaus To: , , , , , CC: Antoniu Miclaus , =?UTF-8?q?Nuno=20S=C3=A1?= Subject: [PATCH v6 01/10] iio: backend: add support for filter config Date: Fri, 16 May 2025 11:26:21 +0300 Message-ID: <20250516082630.8236-2-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250516082630.8236-1-antoniu.miclaus@analog.com> References: <20250516082630.8236-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: ZEwQJPnMMDhudPuepJHY8H6IDgyyXH0C X-Authority-Analysis: v=2.4 cv=MvdS63ae c=1 sm=1 tr=0 ts=6826f6ce cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=gAnH3GRIAAAA:8 a=UD3WkZFi8vOiteFn2FEA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-ORIG-GUID: ZEwQJPnMMDhudPuepJHY8H6IDgyyXH0C X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE2MDA3OSBTYWx0ZWRfX82jYdgsLeHZA v7qoYJpPoUQzXaVkGq0ADoNaDz8r90c1L8dmrH5FtdVNl/PG6JTlfh0vm9gJkK6GiPvKk8bj61p RjPYvrN5Wuee/RoB19m7RcErCgMA5zI3WSoqrtM/3uNIpGpZd5viU1fSoW3N2IJXA0CRa3ENZ2I Foqn2JYdQ/H8JS7rNSZsY0Xxdz71NGTTe/+81qwrnZU46cnt6sGkcbaIRIhDMTnouPKQvtN5rzQ AFhFoyDGW/KbATV7ZB8znR6eYd1dX62xDjgvX79RmwOamwLgu4zvUKKTR+ZofFG+C+57KIImF4b drjq4XF+tZcRx3LTbE1BvcFO13F9Cr5JGYT5+dnU0J2B6uWG4N7GxufULWMxUAhnoLwExAahw3L yVMhpPy4DFcbqMgkFyPGQBY5KDkFx4cOv6uHADe7BhLuE1ymtc4AzHsd7ViJ/4j5WsLkYuYv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-16_03,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 impostorscore=0 adultscore=0 malwarescore=0 mlxlogscore=999 suspectscore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 phishscore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505160079 Add backend support for digital filter type selection. This setting can be adjusted within the IP cores interfacing devices. The IP core can be configured based on the state of the actual digital filter configuration of the part. Reviewed-by: Nuno S=C3=A1 Signed-off-by: Antoniu Miclaus --- no changes in v6. drivers/iio/industrialio-backend.c | 18 ++++++++++++++++++ include/linux/iio/backend.h | 13 +++++++++++++ 2 files changed, 31 insertions(+) diff --git a/drivers/iio/industrialio-backend.c b/drivers/iio/industrialio-= backend.c index d4ad36f54090..038c9e1e2857 100644 --- a/drivers/iio/industrialio-backend.c +++ b/drivers/iio/industrialio-backend.c @@ -778,6 +778,24 @@ static int __devm_iio_backend_get(struct device *dev, = struct iio_backend *back) return 0; } =20 +/** + * iio_backend_filter_type_set - Set filter type + * @back: Backend device + * @type: Filter type. + * + * RETURNS: + * 0 on success, negative error number on failure. + */ +int iio_backend_filter_type_set(struct iio_backend *back, + enum iio_backend_filter_type type) +{ + if (type >=3D IIO_BACKEND_FILTER_TYPE_MAX) + return -EINVAL; + + return iio_backend_op_call(back, filter_type_set, type); +} +EXPORT_SYMBOL_NS_GPL(iio_backend_filter_type_set, "IIO_BACKEND"); + /** * iio_backend_ddr_enable - Enable interface DDR (Double Data Rate) mode * @back: Backend device diff --git a/include/linux/iio/backend.h b/include/linux/iio/backend.h index e45b7dfbec35..5526800f5d4a 100644 --- a/include/linux/iio/backend.h +++ b/include/linux/iio/backend.h @@ -76,6 +76,14 @@ enum iio_backend_interface_type { IIO_BACKEND_INTERFACE_MAX }; =20 +enum iio_backend_filter_type { + IIO_BACKEND_FILTER_TYPE_DISABLED, + IIO_BACKEND_FILTER_TYPE_SINC1, + IIO_BACKEND_FILTER_TYPE_SINC5, + IIO_BACKEND_FILTER_TYPE_SINC5_PLUS_COMP, + IIO_BACKEND_FILTER_TYPE_MAX +}; + /** * struct iio_backend_ops - operations structure for an iio_backend * @enable: Enable backend. @@ -100,6 +108,7 @@ enum iio_backend_interface_type { * @read_raw: Read a channel attribute from a backend device * @debugfs_print_chan_status: Print channel status into a buffer. * @debugfs_reg_access: Read or write register value of backend. + * @filter_type_set: Set filter type. * @ddr_enable: Enable interface DDR (Double Data Rate) mode. * @ddr_disable: Disable interface DDR (Double Data Rate) mode. * @data_stream_enable: Enable data stream. @@ -150,6 +159,8 @@ struct iio_backend_ops { size_t len); int (*debugfs_reg_access)(struct iio_backend *back, unsigned int reg, unsigned int writeval, unsigned int *readval); + int (*filter_type_set)(struct iio_backend *back, + enum iio_backend_filter_type type); int (*ddr_enable)(struct iio_backend *back); int (*ddr_disable)(struct iio_backend *back); int (*data_stream_enable)(struct iio_backend *back); @@ -190,6 +201,8 @@ int iio_backend_data_sample_trigger(struct iio_backend = *back, int devm_iio_backend_request_buffer(struct device *dev, struct iio_backend *back, struct iio_dev *indio_dev); +int iio_backend_filter_type_set(struct iio_backend *back, + enum iio_backend_filter_type type); int iio_backend_ddr_enable(struct iio_backend *back); int iio_backend_ddr_disable(struct iio_backend *back); int iio_backend_data_stream_enable(struct iio_backend *back); --=20 2.49.0 From nobody Sun Feb 8 12:16:16 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E23E41FECB1; Fri, 16 May 2025 08:26:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747384012; cv=none; b=L1a7xGAZx+KRfmxCeDcXznFOEKvLxX5PaRWcHKNzzW3BbvNLHWo8zanPWEReLGFB8iFGMB4CA5TLUGQCPEVNRYASovmRz/TFmIfM2E6fKqQKH5fMmJoxsLXHcOKPJVk0uFU6Txd4FlTSqHNUpcPiDQryxLjKstd5QfXzBI0bUlg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747384012; c=relaxed/simple; bh=PXHQfJ3vn1EsI5Gv7WaYPUScwI3KJ7RIRgAa+nUDW04=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=W0ulcFcTBGCR70B3jkqYyOGUQLd7pDSbJAN90SiPGmxzRF8xnAVkn+Q9jnYNeob70u2FUcdYsQMRGi3KhL9JM0SAZf2UfX6Y08L9hG8OpVKQOcqXgAswaBcL6WIq4fSHBi3+cR555HrYL8seshZF0TIHt9u1YBtM3+ya7IE3YD4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=gt3m7Nd9; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="gt3m7Nd9" Received: from pps.filterd (m0167088.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54G8Ce18016372; Fri, 16 May 2025 04:26:48 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=F5lkZ 1qJDGrYUeQEVHeu7s0q9S89KNko1H1VJOnmKdo=; b=gt3m7Nd9ZepOUhDuvxTZS rp036HM47OLhz5fPU3AbqRI/7Rp5ABhjMvkqJRaGKQ3AH36yQu+fb2DcTwcoY93s fID1ooTBYi+tsab93UgpKo8FOrwAZQYSZ9eTcVwOhmo3Jh2K3Qdy/caw72QQ5PpU rxpWgARFNXow9pdnpcoYlY8YwN2Mdzf9xdG4npSoc7DnyE7GEEW/9AwkNPRuqAS1 33l8M535UU8GlUF1XlvQdv3ngBc6Sbo3mJ+NASgml1Xk8udwx/+qTh4KPinBYfXL YOb05TnPpS+t7IyD/uNNyqQt2wDWWO2ItwlYUU6K9Nc21SJwLw5dYgyhpbYDKvE7 g== Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 46mn654vf9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 May 2025 04:26:47 -0400 (EDT) Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 54G8Qkor033605 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 16 May 2025 04:26:46 -0400 Received: from ASHBCASHYB4.ad.analog.com (10.64.17.132) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 16 May 2025 04:26:46 -0400 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBCASHYB4.ad.analog.com (10.64.17.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 16 May 2025 04:26:46 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Fri, 16 May 2025 04:26:46 -0400 Received: from amiclaus-VirtualBox.ad.analog.com (AMICLAUS-L02.ad.analog.com [10.48.65.120]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 54G8QZwg031549; Fri, 16 May 2025 04:26:42 -0400 From: Antoniu Miclaus To: , , , , , CC: Antoniu Miclaus , =?UTF-8?q?Nuno=20S=C3=A1?= Subject: [PATCH v6 02/10] iio: backend: add support for data alignment Date: Fri, 16 May 2025 11:26:22 +0300 Message-ID: <20250516082630.8236-3-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250516082630.8236-1-antoniu.miclaus@analog.com> References: <20250516082630.8236-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: hjS6tQnkKX2ml0NvlG0KlWXNEtnGfGgG X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE2MDA3OSBTYWx0ZWRfX9swB45JTor+H EEeTJFeibFD0Ix3gv9WVKAjJlQuCxvouOO9YnC9kZUu2+Cw+SpnUE5FWtbhTPoegtv57Jv67S1B sjkEuUK4aI87xdI4kFo8bytawsuzBD21cUczCThXIK4rtLX890+d6DDfbaXKyq0ioNJnFAIXDsC YZ1e6FooPlQQ0pUW2HIDF/C4rhgjM4ZZzPe1mphHUsUgouGS1Ob/5ckJDBJ8nSLXvQJtobl3gyG bL5Ok0CZ7YXzjEzxXE8kfe6jPViS85HEqXQHlHq8HCXpiN1vjfhAgS8js/vCC4q19VukmSr2mco gNb2SWLB46jjfkmXr1O9q6MY8YwcyQqFyrRyAxst4YAlWY6NfIKowfMV6ZbVZArhDqRiZWoX83B FakMsQvtUmSOGafI5Z8A7UkViI59jIXGyPt14FFriTjHnW7XjuiuccI9ipUOK3Y/LSjL4Eu7 X-Authority-Analysis: v=2.4 cv=SZL3duRu c=1 sm=1 tr=0 ts=6826f6c7 cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=gAnH3GRIAAAA:8 a=LieQXdaOVuYbdPten0EA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-ORIG-GUID: hjS6tQnkKX2ml0NvlG0KlWXNEtnGfGgG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-16_03,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 mlxlogscore=999 adultscore=0 priorityscore=1501 mlxscore=0 suspectscore=0 malwarescore=0 spamscore=0 clxscore=1015 phishscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505160079 Add backend support for staring the capture synchronization. When activated, it initates a proccess that aligns the sample's most significant bit (MSB) based solely on the captured data, without considering any other external signals. Reviewed-by: Nuno S=C3=A1 Signed-off-by: Antoniu Miclaus --- no changes in v6. drivers/iio/industrialio-backend.c | 23 +++++++++++++++++++++++ include/linux/iio/backend.h | 3 +++ 2 files changed, 26 insertions(+) diff --git a/drivers/iio/industrialio-backend.c b/drivers/iio/industrialio-= backend.c index 038c9e1e2857..545923310f1f 100644 --- a/drivers/iio/industrialio-backend.c +++ b/drivers/iio/industrialio-backend.c @@ -796,6 +796,29 @@ int iio_backend_filter_type_set(struct iio_backend *ba= ck, } EXPORT_SYMBOL_NS_GPL(iio_backend_filter_type_set, "IIO_BACKEND"); =20 +/** + * iio_backend_data_align - Perform the data alignment process. + * @back: Backend device + * @timeout_us: Timeout value in us. + * + * When activated, it initates a proccess that aligns the sample's most + * significant bit (MSB) based solely on the captured data, without + * considering any other external signals. + * + * The timeout_us value must be greater than 0. + * + * RETURNS: + * 0 on success, negative error number on failure. + */ +int iio_backend_interface_data_align(struct iio_backend *back, u32 timeout= _us) +{ + if (!timeout_us) + return -EINVAL; + + return iio_backend_op_call(back, interface_data_align, timeout_us); +} +EXPORT_SYMBOL_NS_GPL(iio_backend_interface_data_align, "IIO_BACKEND"); + /** * iio_backend_ddr_enable - Enable interface DDR (Double Data Rate) mode * @back: Backend device diff --git a/include/linux/iio/backend.h b/include/linux/iio/backend.h index 5526800f5d4a..a971a83121b7 100644 --- a/include/linux/iio/backend.h +++ b/include/linux/iio/backend.h @@ -109,6 +109,7 @@ enum iio_backend_filter_type { * @debugfs_print_chan_status: Print channel status into a buffer. * @debugfs_reg_access: Read or write register value of backend. * @filter_type_set: Set filter type. + * @interface_data_align: Perform the data alignment process. * @ddr_enable: Enable interface DDR (Double Data Rate) mode. * @ddr_disable: Disable interface DDR (Double Data Rate) mode. * @data_stream_enable: Enable data stream. @@ -161,6 +162,7 @@ struct iio_backend_ops { unsigned int writeval, unsigned int *readval); int (*filter_type_set)(struct iio_backend *back, enum iio_backend_filter_type type); + int (*interface_data_align)(struct iio_backend *back, u32 timeout_us); int (*ddr_enable)(struct iio_backend *back); int (*ddr_disable)(struct iio_backend *back); int (*data_stream_enable)(struct iio_backend *back); @@ -203,6 +205,7 @@ int devm_iio_backend_request_buffer(struct device *dev, struct iio_dev *indio_dev); int iio_backend_filter_type_set(struct iio_backend *back, enum iio_backend_filter_type type); +int iio_backend_interface_data_align(struct iio_backend *back, u32 timeout= _us); int iio_backend_ddr_enable(struct iio_backend *back); int iio_backend_ddr_disable(struct iio_backend *back); int iio_backend_data_stream_enable(struct iio_backend *back); --=20 2.49.0 From nobody Sun Feb 8 12:16:16 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF3FB22D7A3; Fri, 16 May 2025 08:26:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747384015; cv=none; b=pDt1vxKLsZQnZLd5ZrUCU4gLSgO6G+lO1iaBYD+cW8pn58zuKvz+EzRhL4XDN8FEBXECyZ5yz6eFLeT99fjTU8oTkvmwEuj7r0RFySFJ3vNI6CqcAMf/ZhVeItGA5HWxFVYT0NHTlknb2XsO3PAkO+zSEuRC6cBJMiEIHCX2l0k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747384015; c=relaxed/simple; bh=zTgUJp3yfRh24aQRxQ7JpregeB2lmVHnk2oL69bOIfE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=KUl40q/OgmhO/hAVIXn65Ha5JDZV4IsT1oIzyCwAQF/IUQ9A3gFCx/xOiqAWXzdTtNMVC9S66I2j/9gJmYGLqPfQMeJDEaviLogs76tvDhnl4hlftJSq2xTi2VnuR/A62KOckrQVXiqgPOyqRbzrZK40rnISYgS0qPVK6J5z7o8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=HcQNOFbo; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="HcQNOFbo" Received: from pps.filterd (m0167088.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54G8Ce19016372; Fri, 16 May 2025 04:26:51 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=qi1MZ dhtpkjqfPalS3GM0DLpRKCm0ghOFvcuAV7JYPc=; b=HcQNOFboZuNtgNltPu2D4 QquMWycAZLCAZ68+Tu/TP2b5gosYBLcr6DzXFVWSCXkw2y+Nc4N80LQxL1eltv2m YYuaZRzKaAGerRzG7AlTXQMDbzN9UQkLdKI9n5NEw+ixfR/0S/T0gzaU525Fxfpi xvolNaCMHrg7ZeB/XBfXXxBs3KI8OaSs9bxaCZDXf5wPB1IgQVNdAsB2e+/oJFDd 2EnXQoYUwOMP8M5gVlM3uKxi2bCQR5rBO8OfZQK5UzOBD/trkM0bCwk/o3jD1+jp niUu/9rwekkW1syIRS7NIQQM0XlDJgtek+kO9J5ZwARBHhZJHe41MNz209cRQWnk g== Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 46mn654vff-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 May 2025 04:26:51 -0400 (EDT) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 54G8QoYN033614 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 16 May 2025 04:26:50 -0400 Received: from ASHBCASHYB5.ad.analog.com (10.64.17.133) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 16 May 2025 04:26:50 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBCASHYB5.ad.analog.com (10.64.17.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 16 May 2025 04:26:49 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Fri, 16 May 2025 04:26:49 -0400 Received: from amiclaus-VirtualBox.ad.analog.com (AMICLAUS-L02.ad.analog.com [10.48.65.120]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 54G8QZwh031549; Fri, 16 May 2025 04:26:44 -0400 From: Antoniu Miclaus To: , , , , , CC: Antoniu Miclaus , =?UTF-8?q?Nuno=20S=C3=A1?= Subject: [PATCH v6 03/10] iio: backend: add support for number of lanes Date: Fri, 16 May 2025 11:26:23 +0300 Message-ID: <20250516082630.8236-4-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250516082630.8236-1-antoniu.miclaus@analog.com> References: <20250516082630.8236-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: 5QdY2yX3sOi9U51_Y-YoQ0EUXhDqvAck X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE2MDA3OSBTYWx0ZWRfX30OvPaReHpU0 BRWnMjkSsoY9AZCKYjkCWzhgtcSPspTjLx+vAAkHxNfr4VQPzTLetx0vBcRF10BK5dMTajlSyaY NrjcB/UvflhP5en9yGMkzPhmjuZBnce1drVMXeOGb2TzhyR1gGSg7TUVOiRuXQ/S8u4FYag8OKK porxf55yqmeotQfqe55crPZq3MX7z7O0ghYLroyE7zeHGK8G1UeCx/fYf8fhfG//2zZkBm0GxWh rT2Lqa61OsWsFD3s37RA+fTE7gL+twPLaignhxzjwPkLcEBtTN3XBVLQStse0kSD4PMjMU5gRfW E86XTECBo2lCXJHMCiaYnol4Y0uYbQJ/a+yGu37j5edxjKYKgMBb/fOH725Bvi/+EZnd93Sob0d jV/8ybVkif7QdunLlU9jPuaO/IVUY32rYX+s7b4aG3/7ZRRCHAHBRAnnEecPHo1FRX/IR9hV X-Authority-Analysis: v=2.4 cv=SZL3duRu c=1 sm=1 tr=0 ts=6826f6cb cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=gAnH3GRIAAAA:8 a=Ge_Sr372ckFWHCXdfyYA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-ORIG-GUID: 5QdY2yX3sOi9U51_Y-YoQ0EUXhDqvAck X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-16_03,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 mlxlogscore=999 adultscore=0 priorityscore=1501 mlxscore=0 suspectscore=0 malwarescore=0 spamscore=0 clxscore=1015 phishscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505160079 Add iio backend support for number of lanes to be enabled. Reviewed-by: Nuno S=C3=A1 Signed-off-by: Antoniu Miclaus --- no changes in v6. drivers/iio/industrialio-backend.c | 17 +++++++++++++++++ include/linux/iio/backend.h | 3 +++ 2 files changed, 20 insertions(+) diff --git a/drivers/iio/industrialio-backend.c b/drivers/iio/industrialio-= backend.c index 545923310f1f..537fb3202783 100644 --- a/drivers/iio/industrialio-backend.c +++ b/drivers/iio/industrialio-backend.c @@ -819,6 +819,23 @@ int iio_backend_interface_data_align(struct iio_backen= d *back, u32 timeout_us) } EXPORT_SYMBOL_NS_GPL(iio_backend_interface_data_align, "IIO_BACKEND"); =20 +/** + * iio_backend_num_lanes_set - Number of lanes enabled. + * @back: Backend device + * @num_lanes: Number of lanes. + * + * RETURNS: + * 0 on success, negative error number on failure. + */ +int iio_backend_num_lanes_set(struct iio_backend *back, unsigned int num_l= anes) +{ + if (!num_lanes) + return -EINVAL; + + return iio_backend_op_call(back, num_lanes_set, num_lanes); +} +EXPORT_SYMBOL_NS_GPL(iio_backend_num_lanes_set, "IIO_BACKEND"); + /** * iio_backend_ddr_enable - Enable interface DDR (Double Data Rate) mode * @back: Backend device diff --git a/include/linux/iio/backend.h b/include/linux/iio/backend.h index a971a83121b7..1be4671c8c07 100644 --- a/include/linux/iio/backend.h +++ b/include/linux/iio/backend.h @@ -110,6 +110,7 @@ enum iio_backend_filter_type { * @debugfs_reg_access: Read or write register value of backend. * @filter_type_set: Set filter type. * @interface_data_align: Perform the data alignment process. + * @num_lanes_set: Set the number of lanes enabled. * @ddr_enable: Enable interface DDR (Double Data Rate) mode. * @ddr_disable: Disable interface DDR (Double Data Rate) mode. * @data_stream_enable: Enable data stream. @@ -163,6 +164,7 @@ struct iio_backend_ops { int (*filter_type_set)(struct iio_backend *back, enum iio_backend_filter_type type); int (*interface_data_align)(struct iio_backend *back, u32 timeout_us); + int (*num_lanes_set)(struct iio_backend *back, unsigned int num_lanes); int (*ddr_enable)(struct iio_backend *back); int (*ddr_disable)(struct iio_backend *back); int (*data_stream_enable)(struct iio_backend *back); @@ -206,6 +208,7 @@ int devm_iio_backend_request_buffer(struct device *dev, int iio_backend_filter_type_set(struct iio_backend *back, enum iio_backend_filter_type type); int iio_backend_interface_data_align(struct iio_backend *back, u32 timeout= _us); +int iio_backend_num_lanes_set(struct iio_backend *back, unsigned int num_l= anes); int iio_backend_ddr_enable(struct iio_backend *back); int iio_backend_ddr_disable(struct iio_backend *back); int iio_backend_data_stream_enable(struct iio_backend *back); --=20 2.49.0 From nobody Sun Feb 8 12:16:16 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C484822CBE2; Fri, 16 May 2025 08:26:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747384014; cv=none; b=VVOTBOQ6mPv3WbXVkkgWQRuVD+SaJVxcp1ifL0grd4hSrul5FtPrAG4+AFDmIYkBlsYTfXLm1hD9/y+ayn0b4D+fkAmSithTzYbjHQzGOZJcyqtGSALuqoVGgJwQV25TAwMj/AJK2zjAUUar9Mk0CJxFUCHlcNv9sveceIkFERI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747384014; c=relaxed/simple; bh=4hfqqLCYnvX4cIiYK6kuNxNTn4dZ4USWwVsOOGg5dmM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=g8J5uBrzVItkf53sJ8HxSYVIjpHiz/5uTxG5e5TcAv6XKQsVfXhEXWUSyrj9ZQxUTrMtJaBQoKFB79W23t2+96xiubWsdURijoXcLn+yZISTRzfjs1MgDEM88haUXbgpydOFn4Kn1Eg38QayaPTmpmi+1ypxrRzmiUCtf4gslXc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=uUNTlPuR; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="uUNTlPuR" Received: from pps.filterd (m0167088.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54G6CokK016353; Fri, 16 May 2025 04:26:50 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=VlVSg 3Pa/GYE3i4e4eVU1Vl0LeTwTvA/67Iw0CGs2Kg=; b=uUNTlPuRmWwQNI5DW5TVw 9teeyWNeqq3dWoP4hXlbat+RjM7Mou9V9qDYIKmGXMiumOJV7gZTbALHBAw04tGo j2GpD/q/asmZpiH9X8XApvXRzuIAIIWkgnPw2igmaNGclWoTEXGo1nUkzr4rxZOS hVpe0MBHSqZEM/7WTqjoVtbMLJOUImEeBnW0aUnTViS/a09WUjPAX/uT226fkmVv sR1N49WhUwj1QxrycraihGjytSzNZMYguhAMN32I6XHAre52fZNCqczIBboxXVer Gu3gCr6JRDFjWyMT/oMstigLY6J/oVfkrPFyezCgpph6AYraxah4CAJbO/znPib7 A== Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 46mn654vfc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 May 2025 04:26:50 -0400 (EDT) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 54G8QnHO033610 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 16 May 2025 04:26:49 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 16 May 2025 04:26:48 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Fri, 16 May 2025 04:26:48 -0400 Received: from amiclaus-VirtualBox.ad.analog.com (AMICLAUS-L02.ad.analog.com [10.48.65.120]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 54G8QZwi031549; Fri, 16 May 2025 04:26:45 -0400 From: Antoniu Miclaus To: , , , , , CC: Antoniu Miclaus Subject: [PATCH v6 04/10] dt-bindings: iio: adc: add ad408x axi variant Date: Fri, 16 May 2025 11:26:24 +0300 Message-ID: <20250516082630.8236-5-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250516082630.8236-1-antoniu.miclaus@analog.com> References: <20250516082630.8236-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: eEWDR_NnOP7FLMrb7rf7Qc6AsIVdnm1q X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE2MDA3OSBTYWx0ZWRfXx1741pSaHSpi lA48yDVoIbf164X6j75si/46zX8MJeuuqApJN97DqwwwYyD8VL0rzCxY2nsuo5ZGhJg/QKmbGa1 ane8lFKS8IGr/6zJ5mbn633/JEtOR/Kyxx1Xu1Ll5SEzVolQhlA6KcF5XGYN7N7/AJWaIu5ngd+ yjgdWvDb4np+WtqSwkaf5QSfyiLZkRluBAUormJj5DGRBa/s5GrIb4hZJmHmZfVdXcW0R35KWe6 7Z3Us/RbkTDTNo/tnboaAaBa7B4yz/lBMwUQjd//v16OWUmc8bP8yxfkO7z3uCIH4OZX56unIwz 49erC/1fy+MswVUWmYdaQMspAexBhuUNR7AwhQcVG+dHlNhZvvmdGa19FGa2t4tLshMuLbyWbmP TMMGnDPZXMJ2P7XKTqVxG3NavuxCKZFmv8mD+kLYIuOnza65k/SrUKx4LU6LM4rQXLbzzl4f X-Authority-Analysis: v=2.4 cv=SZL3duRu c=1 sm=1 tr=0 ts=6826f6ca cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=dt9VzEwgFbYA:10 a=gAnH3GRIAAAA:8 a=wI1k2SEZAAAA:8 a=VwQbUJbxAAAA:8 a=q2Ulk47HLb923_f0sX4A:9 a=6HWbV-4b7c7AdzY24d_u:22 X-Proofpoint-ORIG-GUID: eEWDR_NnOP7FLMrb7rf7Qc6AsIVdnm1q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-16_03,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 mlxlogscore=999 adultscore=0 priorityscore=1501 mlxscore=0 suspectscore=0 malwarescore=0 spamscore=0 clxscore=1015 phishscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505160079 Content-Type: text/plain; charset="utf-8" Add a new compatible and related bindings for the fpga-based AD408x AXI IP core, a variant of the generic AXI ADC IP. The AXI AD408x IP is a very similar HDL (fpga) variant of the generic AXI ADC IP, intended to control ad408x familiy. Although there are some particularities added for extended control of the ad408x devices such as the filter configuration. Wildcard naming is used to match the naming of the published firmware. Reviewed-by: Rob Herring (Arm) Signed-off-by: Antoniu Miclaus --- no changes in v6. Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml b/D= ocumentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml index cf74f84d6103..e91e421a3d6b 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml @@ -27,6 +27,7 @@ description: | the ad7606 family. =20 https://wiki.analog.com/resources/fpga/docs/axi_adc_ip + https://analogdevicesinc.github.io/hdl/library/axi_ad408x/index.html https://analogdevicesinc.github.io/hdl/library/axi_ad485x/index.html http://analogdevicesinc.github.io/hdl/library/axi_ad7606x/index.html =20 @@ -34,6 +35,7 @@ properties: compatible: enum: - adi,axi-adc-10.0.a + - adi,axi-ad408x - adi,axi-ad7606x - adi,axi-ad485x =20 --=20 2.49.0 From nobody Sun Feb 8 12:16:16 2026 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61E9622DA12; Fri, 16 May 2025 08:27:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747384042; cv=none; b=fW+w7/gmOub/Q6lQH25w2vdUIpS8QQx0mwfoSjZoYZcTo3nhnHK3GKPiZ0mJAFEEVWzXVFUhELtno6Rm75cF0IIOugjv0yRXRtgKCLewEFM+PwvAAbvT1pw71CU4cVGDWVKjVHsTi3xPjGOvkj0vmVGwHlQfRxx3ijl7BLN8N6A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747384042; c=relaxed/simple; bh=3q/GKFuplJbG4mV3MADRU/64WOlMdWW2JP+DRIqFOKA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ZFQMdUMHt7mTiUHhTl0NoZyBN9h/uYzeOBKry/Rr93ZVgPsx3VHUrO3+pkLuydpVM21iT0ottbcZBPjF/Pcce7idGo3pdNmfQQG46HmB1iUaLhSLE+yJhAnVjib7WXoL4Umrce4/Y0UCsPONhlmOAgISgxqXHcoJq8nzEi9UT00= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=DP2qG5nF; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="DP2qG5nF" Received: from pps.filterd (m0375855.ppops.net [127.0.0.1]) by mx0b-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54G6XkgK010053; Fri, 16 May 2025 04:27:17 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=xBl0e 5N3fGGp+F1afaexSwGmJ3XYC9+flArzGOheeWY=; b=DP2qG5nFwny6k0vd8LdYH O31alMSgys6oMU6N7h/didTsuHh8iGIZyUjwHisLx72+R71DwARZgOrBlLVgYos+ iwk8k2RxzSaJ6gy66EITwK8L06I4djY6kPFVvAcI8WQ4jYJmjFctv/69WrTwMlTw QNY7DlWF49wxh7UZuOnWFbkthfaGvfBBI5w2Vqioyin2kAtMDxHbynxdy1sVByft i8caec4Jb3h1UC+gZ2B5cz0NA/nqw2kLTdJaBd3ROG0GhOyEyxO3G3QkgEDl/vnX 3iXUIqsDYaQSCKigx4fdMt/O2PE1X6wEVsHhjTvmCaVnxBWCZpxCwtuh0DhQ20pi A== Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0b-00128a01.pphosted.com (PPS) with ESMTPS id 46p070retx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 May 2025 04:27:15 -0400 (EDT) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 54G8Qqgq033628 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 16 May 2025 04:26:52 -0400 Received: from ASHBCASHYB5.ad.analog.com (10.64.17.133) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 16 May 2025 04:26:52 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBCASHYB5.ad.analog.com (10.64.17.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 16 May 2025 04:26:52 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Fri, 16 May 2025 04:26:52 -0400 Received: from amiclaus-VirtualBox.ad.analog.com (AMICLAUS-L02.ad.analog.com [10.48.65.120]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 54G8QZwj031549; Fri, 16 May 2025 04:26:46 -0400 From: Antoniu Miclaus To: , , , , , CC: Antoniu Miclaus , =?UTF-8?q?Nuno=20S=C3=A1?= Subject: [PATCH v6 05/10] iio: adc: adi-axi-adc: add filter type config Date: Fri, 16 May 2025 11:26:25 +0300 Message-ID: <20250516082630.8236-6-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250516082630.8236-1-antoniu.miclaus@analog.com> References: <20250516082630.8236-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: hH4JEMf-_uKzKlPzOc5IPHacqJK82xrP X-Proofpoint-GUID: hH4JEMf-_uKzKlPzOc5IPHacqJK82xrP X-Authority-Analysis: v=2.4 cv=A/9sP7WG c=1 sm=1 tr=0 ts=6826f6e3 cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=gAnH3GRIAAAA:8 a=Gqha4wrVLCtXpNfHMFMA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE2MDA3OSBTYWx0ZWRfX2QcDhQpyjzXK 2RhOEEdoqkJvvaD/ZdVtxBG4jX1tHzB25UqA7OgS+IXvHYP8F2BI46LmNmJmmP8nqLU6bwkULQW Fscros1t/LVU2L++GLEGq0GgVu+DRfbI0Olw4lLJ+SXStPXpPZ6H5Uaio3XAXn0VPvT20+/fBdh W6TzK6rY2pO7cwTgc3WY8FOncQy+3VxqkpMfcqlLm9rvNf3BUFmwJbwdazPGE/bZo+4Qxth4ODx laqUboiWVApsr5TFXc0uYQEEorICkdPTpWDc6DpqMWIX+KB8wW8pZHpIyP2FoCgXV+NTk4RrwpZ LtYV0zPOgqVebeprTwbhKiTcsrRQxCjMkRTQaoyH+d5fOgX5zcyde8mNdHlxfIfUaQliYQgTZY/ 2/1Ze/m7Z4Oo9dXCMgnxv9LEJMRG/ps78Dvrz/V4aS7jArfSFsgjL3N1HybJmbCGv+8+AGW2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-16_03,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 mlxscore=0 impostorscore=0 clxscore=1015 adultscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505160079 Add support for enabling/disabling filter based on the filter type provided. This feature is specific to the axi ad408x IP core, therefore add new compatible string and corresponding iio_backend_ops. Reviewed-by: Nuno S=C3=A1 Signed-off-by: Antoniu Miclaus --- no changes in v6. drivers/iio/adc/adi-axi-adc.c | 38 +++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c index 61ab7dce43be..2a3a6c3f5e59 100644 --- a/drivers/iio/adc/adi-axi-adc.c +++ b/drivers/iio/adc/adi-axi-adc.c @@ -52,6 +52,7 @@ #define AXI_AD485X_PACKET_FORMAT_20BIT 0x0 #define AXI_AD485X_PACKET_FORMAT_24BIT 0x1 #define AXI_AD485X_PACKET_FORMAT_32BIT 0x2 +#define AXI_AD408X_CNTRL_3_FILTER_EN_MSK BIT(0) =20 #define ADI_AXI_ADC_REG_DRP_STATUS 0x0074 #define ADI_AXI_ADC_DRP_LOCKED BIT(17) @@ -402,6 +403,19 @@ static int axi_adc_ad485x_oversampling_ratio_set(struc= t iio_backend *back, } } =20 +static int axi_adc_ad408x_filter_type_set(struct iio_backend *back, + enum iio_backend_filter_type type) +{ + struct adi_axi_adc_state *st =3D iio_backend_get_priv(back); + + if (type) + return regmap_set_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3, + AXI_AD408X_CNTRL_3_FILTER_EN_MSK); + + return regmap_clear_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3, + AXI_AD408X_CNTRL_3_FILTER_EN_MSK); +} + static struct iio_buffer *axi_adc_request_buffer(struct iio_backend *back, struct iio_dev *indio_dev) { @@ -582,6 +596,24 @@ static const struct iio_backend_info axi_ad485x =3D { .ops =3D &adi_ad485x_ops, }; =20 +static const struct iio_backend_ops adi_ad408x_ops =3D { + .enable =3D axi_adc_enable, + .disable =3D axi_adc_disable, + .chan_enable =3D axi_adc_chan_enable, + .chan_disable =3D axi_adc_chan_disable, + .request_buffer =3D axi_adc_request_buffer, + .free_buffer =3D axi_adc_free_buffer, + .data_sample_trigger =3D axi_adc_data_sample_trigger, + .filter_type_set =3D axi_adc_ad408x_filter_type_set, + .debugfs_reg_access =3D iio_backend_debugfs_ptr(axi_adc_reg_access), + .debugfs_print_chan_status =3D iio_backend_debugfs_ptr(axi_adc_debugfs_pr= int_chan_status), +}; + +static const struct iio_backend_info axi_ad408x =3D { + .name =3D "axi-ad408x", + .ops =3D &adi_ad408x_ops, +}; + static int adi_axi_adc_probe(struct platform_device *pdev) { struct adi_axi_adc_state *st; @@ -697,9 +729,15 @@ static const struct axi_adc_info adc_ad7606 =3D { .has_child_nodes =3D true, }; =20 +static const struct axi_adc_info adi_axi_ad408x =3D { + .version =3D ADI_AXI_PCORE_VER(10, 0, 'a'), + .backend_info =3D &axi_ad408x, +}; + /* Match table for of_platform binding */ static const struct of_device_id adi_axi_adc_of_match[] =3D { { .compatible =3D "adi,axi-adc-10.0.a", .data =3D &adc_generic }, + { .compatible =3D "adi,axi-ad408x", .data =3D &adi_axi_ad408x }, { .compatible =3D "adi,axi-ad485x", .data =3D &adi_axi_ad485x }, { .compatible =3D "adi,axi-ad7606x", .data =3D &adc_ad7606 }, { /* end of list */ } --=20 2.49.0 From nobody Sun Feb 8 12:16:16 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8EE0222F77B; Fri, 16 May 2025 08:26:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747384019; cv=none; b=YiCMXQxDoeqni4QwAMw4xAiYNDZLP1VZfmKg3te12+pBqRthnYni9xOuyqwA0LVwX4+b5Q13Y1BOtqb3oRvgdgOEsadGirNIwkImfZtHBwPCyq3fdnoWfAWxwakHNl5Ib6xAt0C4SrtMgXFlZhUaJ1BwcqYdfuTvGrDwtFsEdNs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747384019; c=relaxed/simple; bh=TUYc48z0lNgqLqi1vHJYv8MyyzFgasv82sjTQl5P+kc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VIYonDCQ9aM5ZjQVgauWvOTorESQ2v0x78QlogSYBQaHNBedlh8n7TKCgyjSrP+UGkyTALdqUJ+rgF3yd5vvqjEFjMmpGJ8sicxyQ/okzmOU+Id0i10o0nvyLTMfvxGhSZYry2BXexTcA0MF+WD44XP79FK931Ef0V48IcIfJ1A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=gRWb44UN; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="gRWb44UN" Received: from pps.filterd (m0167088.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54G8Ce1A016372; Fri, 16 May 2025 04:26:55 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=0hvsd +G13KfwN/n8/HSXfh/s/bV6cQeB/WSq4KwPF9U=; b=gRWb44UNUtQefLyzgogkt 4/Y4Tbv9yJvUHgLsjkpLSEpeqx7X8+XYL1QhkhZXGYSDoDwtrmCK2dTmKR66lagZ 2w/pUoHF7DC7jp48adEvHRYGweK3hO7e68qOc/jDCbzrdWLf6omiPgXqYRnuWyW1 ot4rf8MLKXts4uVeT4ZE48nxdvuHWBIY0McKLbPp2JwtFq81P2RHP+k1Y1qzVaFN iCwxcM6+TXw0mMqwJM83PmS888nNohNwm5MUS+tiVefKP2OFqNCncOtH+mrtYfiZ 5uSaNpbuUO62tyxpwA3NvxHWn0KKswlEayeT3lS+d5FZasxkuYsWwLR7IoqO1nds g== Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 46mn654vfr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 May 2025 04:26:54 -0400 (EDT) Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 54G8Qrdh033635 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 16 May 2025 04:26:53 -0400 Received: from ASHBCASHYB5.ad.analog.com (10.64.17.133) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 16 May 2025 04:26:53 -0400 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBCASHYB5.ad.analog.com (10.64.17.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 16 May 2025 04:26:53 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Fri, 16 May 2025 04:26:53 -0400 Received: from amiclaus-VirtualBox.ad.analog.com (AMICLAUS-L02.ad.analog.com [10.48.65.120]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 54G8QZwk031549; Fri, 16 May 2025 04:26:47 -0400 From: Antoniu Miclaus To: , , , , , CC: Antoniu Miclaus , =?UTF-8?q?Nuno=20S=C3=A1?= Subject: [PATCH v6 06/10] iio: adc: adi-axi-adc: add data align process Date: Fri, 16 May 2025 11:26:26 +0300 Message-ID: <20250516082630.8236-7-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250516082630.8236-1-antoniu.miclaus@analog.com> References: <20250516082630.8236-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: WhYAjsJHnEcmtUeEHxOTSTPlFKl0I72b X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE2MDA3OSBTYWx0ZWRfX76NLYOhj+brk dDmRfwTJ1eiOGyztEynR/h2QZNBB8PBC7xlGNnnfkeJ0l5Pp+SVOWGtAj6p+4BfMVY5vpGOvgLd mQADNCqHkIvV068I1tfjOWNBa0tI5YLT/N6EthEN6JaLh5W2ed4sf/8GFWWbZbwR5fUTIvrxyc3 FBtw6Q2UuiwgTY5yYo6Wxdee2IxoKz+0Qoq/RafBySNRow/HJq9VucyPcqpQEUpV9R2sOHum8z0 WFrdHX8sYV2yC+PrsGv7ZSvgnFJHqVwtH6ZUlHkFCRX1jaVh5pWYLGNaDc8UdeCaRgazvobcEKl 2axL9XSA0tarCj69xX0HX2oAiZcx1laXs/OUko1lhXggcNkqZX/8xnaHd9cbmPglwXz0uM6IPGv eNLq1HrFzUfI4IDZcHBpibBLvzE4F4JdSc3qeK2h+iI08akTJ5/F6zEApcG43rnGgAyRX0fA X-Authority-Analysis: v=2.4 cv=SZL3duRu c=1 sm=1 tr=0 ts=6826f6cf cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=gAnH3GRIAAAA:8 a=wxM4B6g2en942FlrxLsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-ORIG-GUID: WhYAjsJHnEcmtUeEHxOTSTPlFKl0I72b X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-16_03,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 mlxlogscore=999 adultscore=0 priorityscore=1501 mlxscore=0 suspectscore=0 malwarescore=0 spamscore=0 clxscore=1015 phishscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505160079 Add support for starting the sync process used for data capture alignment. Reviewed-by: Nuno S=C3=A1 Signed-off-by: Antoniu Miclaus --- no changes in v6. drivers/iio/adc/adi-axi-adc.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c index 2a3a6c3f5e59..f9c4018e3b41 100644 --- a/drivers/iio/adc/adi-axi-adc.c +++ b/drivers/iio/adc/adi-axi-adc.c @@ -44,6 +44,7 @@ #define ADI_AXI_ADC_REG_CONFIG_CMOS_OR_LVDS_N BIT(7) =20 #define ADI_AXI_ADC_REG_CTRL 0x0044 +#define ADI_AXI_ADC_CTRL_SYNC_MSK BIT(3) #define ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK BIT(1) =20 #define ADI_AXI_ADC_REG_CNTRL_3 0x004c @@ -54,6 +55,9 @@ #define AXI_AD485X_PACKET_FORMAT_32BIT 0x2 #define AXI_AD408X_CNTRL_3_FILTER_EN_MSK BIT(0) =20 +#define ADI_AXI_ADC_REG_SYNC_STATUS 0x0068 +#define ADI_AXI_ADC_SYNC_STATUS_ADC_SYNC_MSK BIT(0) + #define ADI_AXI_ADC_REG_DRP_STATUS 0x0074 #define ADI_AXI_ADC_DRP_LOCKED BIT(17) =20 @@ -416,6 +420,25 @@ static int axi_adc_ad408x_filter_type_set(struct iio_b= ackend *back, AXI_AD408X_CNTRL_3_FILTER_EN_MSK); } =20 +static int axi_adc_ad408x_interface_data_align(struct iio_backend *back, + u32 timeout_us) +{ + struct adi_axi_adc_state *st =3D iio_backend_get_priv(back); + bool sync_en; + u32 val; + int ret; + + ret =3D regmap_set_bits(st->regmap, ADI_AXI_ADC_REG_CTRL, + ADI_AXI_ADC_CTRL_SYNC_MSK); + if (ret) + return ret; + + return regmap_read_poll_timeout(st->regmap, ADI_AXI_ADC_REG_SYNC_STATUS, + val, + FIELD_GET(ADI_AXI_ADC_SYNC_STATUS_ADC_SYNC_MSK, val), + 1, timeout_us); +} + static struct iio_buffer *axi_adc_request_buffer(struct iio_backend *back, struct iio_dev *indio_dev) { @@ -605,6 +628,7 @@ static const struct iio_backend_ops adi_ad408x_ops =3D { .free_buffer =3D axi_adc_free_buffer, .data_sample_trigger =3D axi_adc_data_sample_trigger, .filter_type_set =3D axi_adc_ad408x_filter_type_set, + .interface_data_align =3D axi_adc_ad408x_interface_data_align, .debugfs_reg_access =3D iio_backend_debugfs_ptr(axi_adc_reg_access), .debugfs_print_chan_status =3D iio_backend_debugfs_ptr(axi_adc_debugfs_pr= int_chan_status), }; --=20 2.49.0 From nobody Sun Feb 8 12:16:16 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B982B22FDF1; Fri, 16 May 2025 08:26:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747384020; cv=none; b=pgE63f6CTFqSfJSS3ELaegHiGXCytcxZExhVWNC7KIV5UGIloKLFvUdqKLW8CnWIaYfA63TAKWcxTXZkOikPWvApntZ4nO8D1QpXYQkvjmaWRtHaXUgyXGXx+iOUVou7BzZnHBf/4T8i3AaatsGZekq6T+vv9h22UqDhWi/AEdU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747384020; c=relaxed/simple; bh=ScSAyCK0HvQAe5UL0JgYS4SVnZb2FnQcIOkvm3RuSUU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ajRsYZ8wBXQ/d03yckTvNz3c+dhKtNp7/b/9Osu2wIdnTWb9gQ6qmLdTgjKrhljcourKiPyZoVCQ93fJuhC45a/mM9P/xc8J0uO4TGTs4CqADbE3KMxG1acjBW8Y+FpMt+CrzEOnBB4xOElYbZeFbRjrldqfodJIgfYHvIpOYmQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=l589M83c; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="l589M83c" Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54G5Jecn001259; Fri, 16 May 2025 04:26:56 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=0/TzE ylyZqjFXZZGxngmENbv6a/CxvMui1d6M10xyCo=; b=l589M83cR6aaXfeZmK4/g 3POAM2405VLmJ9KInjXg7C1Yg2VT/asgfGygbnH32LcIIyYW+RT4XFYyVEBvn882 OG2CvFQCk06dwfZuRhzLr9Tdkf5/DZ3me6LKGC0QkaY3nGJUDInXhcz5DST2RJlr uZw/7iDah+AqUWrg2NJkbPmzYC3htBJS+nd0HGBDGctoctIUL9I1jrCOEVYVaLZ7 ws9ovBBT95RxkcwZb6dB6CjXjKWcuJ/fjJkP7WcANxB9yOkHY1bLb+VDh9dY37c6 QDinFg2nVUtQgGfsNSE+QwCgQZJsdU2hj55f9ZdJZcFc/vLbn2msUJOf0DfocYAd Q== Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 46ny4a8qju-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 May 2025 04:26:56 -0400 (EDT) Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 54G8QtCs033643 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 16 May 2025 04:26:55 -0400 Received: from ASHBCASHYB5.ad.analog.com (10.64.17.133) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 16 May 2025 04:26:55 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBCASHYB5.ad.analog.com (10.64.17.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 16 May 2025 04:26:54 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Fri, 16 May 2025 04:26:54 -0400 Received: from amiclaus-VirtualBox.ad.analog.com (AMICLAUS-L02.ad.analog.com [10.48.65.120]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 54G8QZwl031549; Fri, 16 May 2025 04:26:49 -0400 From: Antoniu Miclaus To: , , , , , CC: Antoniu Miclaus , =?UTF-8?q?Nuno=20S=C3=A1?= Subject: [PATCH v6 07/10] iio: adc: adi-axi-adc: add num lanes support Date: Fri, 16 May 2025 11:26:27 +0300 Message-ID: <20250516082630.8236-8-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250516082630.8236-1-antoniu.miclaus@analog.com> References: <20250516082630.8236-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: -_uAEg0jDYyWMf0mK5ot8Os2je2MZczU X-Authority-Analysis: v=2.4 cv=MvdS63ae c=1 sm=1 tr=0 ts=6826f6d0 cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=gAnH3GRIAAAA:8 a=MtuLGBRfhagEvKnVNLsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-ORIG-GUID: -_uAEg0jDYyWMf0mK5ot8Os2je2MZczU X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE2MDA3OSBTYWx0ZWRfX7MgyCAw8iGrO GGtUJk8h1o6rBN95xdd3Io1oIQvoiYTTKdQcaBlbun+PykJeS1X6zljJePsk+1uYJij9YyiLCs7 CmAr18qRiQtHVldVRiHJhKYe/Fz7bxo+bRs+BTR03bXHi9UZW7u2EmZq8q6cDRfxjXAeK29Y2rO lCnzgucLvQw4rlchUtF4sSFfiTfymMgI0Ud7bqrgSY/N65wVSjHRFzSCilNzfhAxjadIhDhjxTa lzE+e4QAMDROLWK/gvJlWqWpJM/kIe6T2tEn3lOFecBLXBBsMO3yi87pWmZjIjmOq0D16+BnE/z EFGJ4XhM2pwNg4ohRK2ioAp0CgdDQSiSODxmRdbrxC+eyuyysNOyr8TkpjOeU+y3V/rE0f+QC+v lCn2OKSGT9ddlXDdjZ/rDjoHvVppBis8APFqWyRDGmE3ZaRSxDiFM5S+Y6D1bTZvv+TRmsYU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-16_03,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 impostorscore=0 adultscore=0 malwarescore=0 mlxlogscore=999 suspectscore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 phishscore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505160079 Add support for setting the number of lanes enabled. Reviewed-by: Nuno S=C3=A1 Signed-off-by: Antoniu Miclaus --- no changes in v6. drivers/iio/adc/adi-axi-adc.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c index f9c4018e3b41..d9a14fb6b8e8 100644 --- a/drivers/iio/adc/adi-axi-adc.c +++ b/drivers/iio/adc/adi-axi-adc.c @@ -44,6 +44,7 @@ #define ADI_AXI_ADC_REG_CONFIG_CMOS_OR_LVDS_N BIT(7) =20 #define ADI_AXI_ADC_REG_CTRL 0x0044 +#define ADI_AXI_ADC_CTRL_NUM_LANES_MSK GENMASK(12, 8) #define ADI_AXI_ADC_CTRL_SYNC_MSK BIT(3) #define ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK BIT(1) =20 @@ -439,6 +440,19 @@ static int axi_adc_ad408x_interface_data_align(struct = iio_backend *back, 1, timeout_us); } =20 +static int axi_adc_num_lanes_set(struct iio_backend *back, + unsigned int num_lanes) +{ + struct adi_axi_adc_state *st =3D iio_backend_get_priv(back); + + if (!num_lanes) + return -EINVAL; + + return regmap_update_bits(st->regmap, ADI_AXI_ADC_REG_CTRL, + ADI_AXI_ADC_CTRL_NUM_LANES_MSK, + FIELD_PREP(ADI_AXI_ADC_CTRL_NUM_LANES_MSK, num_lanes)); +} + static struct iio_buffer *axi_adc_request_buffer(struct iio_backend *back, struct iio_dev *indio_dev) { @@ -629,6 +643,7 @@ static const struct iio_backend_ops adi_ad408x_ops =3D { .data_sample_trigger =3D axi_adc_data_sample_trigger, .filter_type_set =3D axi_adc_ad408x_filter_type_set, .interface_data_align =3D axi_adc_ad408x_interface_data_align, + .num_lanes_set =3D axi_adc_num_lanes_set, .debugfs_reg_access =3D iio_backend_debugfs_ptr(axi_adc_reg_access), .debugfs_print_chan_status =3D iio_backend_debugfs_ptr(axi_adc_debugfs_pr= int_chan_status), }; --=20 2.49.0 From nobody Sun Feb 8 12:16:16 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0071F22FAE1; Fri, 16 May 2025 08:26:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747384019; cv=none; b=rPOSNTKE8A4abw1cfQJDhSVrA0s8razpUSkGvUV75ofqjEBBiMe6PkJvwql20CXMyH9WKmOUv4CW2fSyMNwne15h6Z31wS19FmYNo+xTITDeyGVH+y2adE294K8gAX3xdGUIFaimVtPjEk3siYHgunYYbLns8VWWE4f4vDY1LWw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747384019; c=relaxed/simple; bh=1xGy41PBzlTZekwUqX/QKoC1rUJGaAtrasgQtx3pbBU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=rfjnz+mOPGJSqxMrnyzq7tx4kpwFht2IJW83jSZe66iFperYc7eWFmir8xmAppdiI32iUFGHBLSqUaplYIdZrgGbKNCcQLa3UQOkTVly0AUQgnnwh6ukqeaW65tvSKtCvWgOiCuGOsV+DrlTPa6P2nZxshQcmhac0jIagOA3eMg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=hhgAlXp2; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="hhgAlXp2" Received: from pps.filterd (m0167088.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54G4dOSe016366; Fri, 16 May 2025 04:26:55 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=q7NgU JXX5Ks4psOwbYOMNAw1fzeUGVLZFPCTR1rPn5k=; b=hhgAlXp2W90y8Iky6oqjy P5VZ9/KelwUEahb33miRXJ366Mhxvc2GV7tK7rLmR27aEi2etz2E7O6AHGivhXIB RXYm8A0RsmYz123I5cQenWQ/o27z8r4me8Zl/s+wp09bQy+KazYSQVjwABb/jnAB 9YH4Dcy21SsA4h8HQVCtw8kttJgOKWWGqL0oC1rgQ23JknDTZarH5SH331N8gg3I +FOP1HGJwPAij+CCcyCfAic0GjtLapOx1FPJKFj/xid9hyu3QaK8SALgiuZEcVoG 4JqD56Cmkb5z2u4OC+kWhT/aheLuaBZqe2yoW1eahy73F2Mg5cY4ld5fQnW2Cr7K Q== Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 46mn654vfs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 May 2025 04:26:55 -0400 (EDT) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 54G8Qs7T033639 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 16 May 2025 04:26:54 -0400 Received: from ASHBCASHYB5.ad.analog.com (10.64.17.133) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 16 May 2025 04:26:54 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBCASHYB5.ad.analog.com (10.64.17.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 16 May 2025 04:26:54 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Fri, 16 May 2025 04:26:54 -0400 Received: from amiclaus-VirtualBox.ad.analog.com (AMICLAUS-L02.ad.analog.com [10.48.65.120]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 54G8QZwm031549; Fri, 16 May 2025 04:26:50 -0400 From: Antoniu Miclaus To: , , , , , CC: Antoniu Miclaus Subject: [PATCH v6 08/10] dt-bindings: iio: adc: add ad4080 Date: Fri, 16 May 2025 11:26:28 +0300 Message-ID: <20250516082630.8236-9-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250516082630.8236-1-antoniu.miclaus@analog.com> References: <20250516082630.8236-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: h-lHookt7zlpaEV3RC15ba3hF29FzAPp X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE2MDA3OSBTYWx0ZWRfXzItGJeN7vF+k r2kU4lrRylyXjEucKur4ipgGKmF4d0cp4NU91eQGVnlmXkoXwvu5zx2EIq02nNJQ9zor/LYoYDn TRDTwBVdZdnjXweVeAuLKMxAL59IaZLxC63Y7L/rZGcHfUCSZcUg/mABJHtJKZiIxPZjngbXbul Uy9eNGyH9oIJq+LKsPh+4dow8PDx9WP9hgPvBCrOBesFiV2obYqS0b24X6e9DmB6jbzM9uVtjZe j+V4SS1IY113uL/Ui7t47sSffKfrt8mRnTYdWhcOJDhp8T3Tnyl7iGxJx6aJbEZz2YGEg3/r/Wg QO6+4QCEofTF7BMTvizjzQM+WRIfLoNsukzo9rWw6ODWBbZe1uqZvAV8LDIh4bJhLmcKOhTYpwq bwtiXf9RyUu8dbIIRT/ffuf3aHcfbjS4oHrpC6U7EKfSpT9z86t+13NEZ8Oh71U9sHlT0I7d X-Authority-Analysis: v=2.4 cv=SZL3duRu c=1 sm=1 tr=0 ts=6826f6cf cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=dt9VzEwgFbYA:10 a=gEfo2CItAAAA:8 a=gAnH3GRIAAAA:8 a=VwQbUJbxAAAA:8 a=s-jUAG74_yLYYRHcQYIA:9 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-ORIG-GUID: h-lHookt7zlpaEV3RC15ba3hF29FzAPp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-16_03,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 mlxlogscore=999 adultscore=0 priorityscore=1501 mlxscore=0 suspectscore=0 malwarescore=0 spamscore=0 clxscore=1015 phishscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505160079 Content-Type: text/plain; charset="utf-8" Add devicetree bindings for ad4080 family. Reviewed-by: Rob Herring (Arm) Signed-off-by: Antoniu Miclaus --- changes in v6: - add MAINTAINERS changes. .../bindings/iio/adc/adi,ad4080.yaml | 96 +++++++++++++++++++ MAINTAINERS | 7 ++ 2 files changed, 103 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,ad4080.ya= ml diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4080.yaml new file mode 100644 index 000000000000..ed849ba1b77b --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2025 Analog Devices Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad4080.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD4080 20-Bit, 40 MSPS, Differential SAR ADC + +maintainers: + - Antoniu Miclaus + +description: | + The AD4080 is a high speed, low noise, low distortion, 20-bit, Easy Driv= e, + successive approximation register (SAR) analog-to-digital converter (ADC= ). + Maintaining high performance (signal-to-noise and distortion (SINAD) rat= io + > 90 dBFS) at signal frequencies in excess of 1 MHz enables the AD4080 to + service a wide variety of precision, wide bandwidth data acquisition + applications. + + https://www.analog.com/media/en/technical-documentation/data-sheets/ad40= 80.pdf + +$ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - adi,ad4080 + + reg: + maxItems: 1 + + spi-max-frequency: + description: Configuration of the SPI bus. + maximum: 50000000 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: cnv + + vdd33-supply: true + + vdd11-supply: true + + vddldo-supply: true + + iovdd-supply: true + + vrefin-supply: true + + io-backends: + maxItems: 1 + + adi,lvds-cnv-enable: + description: Enable the LVDS signal type on the CNV pin. Default is CM= OS. + type: boolean + + adi,num-lanes: + description: + Number of lanes on which the data is sent on the output (DA, DB pins= ). + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2] + default: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - vdd33-supply + - vrefin-supply + +additionalProperties: false + +examples: + - | + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,ad4080"; + reg =3D <0>; + spi-max-frequency =3D <10000000>; + vdd33-supply =3D <&vdd33>; + vddldo-supply =3D <&vddldo>; + vrefin-supply =3D <&vrefin>; + clocks =3D <&cnv>; + clock-names =3D "cnv"; + io-backends =3D <&iio_backend>; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index bd04375ab4a2..244a4510bbc8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1317,6 +1317,13 @@ F: Documentation/devicetree/bindings/iio/adc/adi,ad4= 030.yaml F: Documentation/iio/ad4030.rst F: drivers/iio/adc/ad4030.c =20 +ANALOG DEVICES INC AD4080 DRIVER +M: Antoniu Miclaus +L: linux-iio@vger.kernel.org +S: Supported +W: https://ez.analog.com/linux-software-drivers +F: Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml + ANALOG DEVICES INC AD4130 DRIVER M: Cosmin Tanislav L: linux-iio@vger.kernel.org --=20 2.49.0 From nobody Sun Feb 8 12:16:16 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD9CC22D4EB; Fri, 16 May 2025 08:27:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747384023; cv=none; b=GU75chwdDvxxicsN5kQ2CIt7/9Z1DRBFXXvZfBawxBy1n1LN+nyBQpVD4/Gi7iRFxk7bixNB2P0wp1d1Hli9+rLZRwnyoLsM55AJiMHDDXGBa11f9V1nFZV8A2XWMIrgBV0/mwzRJgZtAoyuguhyFgj0zjdi4scN/1LVAadkU6U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747384023; c=relaxed/simple; bh=V4dbu7o5GxugvNEiDqVhETWdivv9mY9YWoXw3IYIhAM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jrWXQFW5B/0YBzxRpwJRQ9rGA3uvr3bcu1l2csMCCQ7RlDNWU6Vh6fno5F/5vEXCXJq8L6qRk2HLniz1XMzLflq6FWi41e9qK4ab+QfXs6+sJ8llvmLwWxsgDx/kAdX037Cg65P1YoAjySZnscm7uy7QXxGhQekJ9Vo7kgXrIK4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=0Nyzax30; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="0Nyzax30" Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54G5Je3x001264; Fri, 16 May 2025 04:26:58 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=jLMrd hx45i4EVP4ZMXMDqSQxvSW9iK66a67dggCUVnM=; b=0Nyzax30YQ5hT7D10gKrs prrHnG4lsOujg2ErjwAXBQPkB4X7f01rPuqdtkDvsi7++icH2oIkIFCpOPkePW+4 IJDf1Yp2IfwCB+wpMGmvw6tlUr571USrsDTm7zH2GwvINyOH/ZkGfljlcgyOhWiw 6mIsGnGA2IFyY8sCXpk3mGiCv6L6BWkRS9jpeLav191r1xIiYqIC1MswuwI/NvVU OB1VC0c+B5CG/H5Ic0pd/s2RhP6FcD94jnAEVE/R46AuPBb6Q16GJOLCanfPWSWy 73ookw5oiMXcGFESZp+CiVyzv6xz9Z971xQ3f3FkR0zK2hOt1V6OPsS1l10pSFL0 A== Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 46ny4a8qjx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 May 2025 04:26:58 -0400 (EDT) Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 54G8Qv45033654 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 16 May 2025 04:26:57 -0400 Received: from ASHBCASHYB4.ad.analog.com (10.64.17.132) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 16 May 2025 04:26:57 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBCASHYB4.ad.analog.com (10.64.17.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 16 May 2025 04:26:56 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Fri, 16 May 2025 04:26:56 -0400 Received: from amiclaus-VirtualBox.ad.analog.com (AMICLAUS-L02.ad.analog.com [10.48.65.120]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 54G8QZwn031549; Fri, 16 May 2025 04:26:51 -0400 From: Antoniu Miclaus To: , , , , , CC: Antoniu Miclaus Subject: [PATCH v6 09/10] iio: adc: ad4080: add driver support Date: Fri, 16 May 2025 11:26:29 +0300 Message-ID: <20250516082630.8236-10-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250516082630.8236-1-antoniu.miclaus@analog.com> References: <20250516082630.8236-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: KiT57I4d2xzrZv0uGMTR-ZF6wtBotYf6 X-Authority-Analysis: v=2.4 cv=MvdS63ae c=1 sm=1 tr=0 ts=6826f6d2 cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=dt9VzEwgFbYA:10 a=gAnH3GRIAAAA:8 a=VwQbUJbxAAAA:8 a=XWQM0tir05fXBLfBid0A:9 X-Proofpoint-ORIG-GUID: KiT57I4d2xzrZv0uGMTR-ZF6wtBotYf6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE2MDA3OSBTYWx0ZWRfX6pOqXvLu4kdQ TG2uhKYTqPGkreuU231+0hFeRBSwj5lGF2zKgw56q9gd0Rakm8bCJTrsLJAUySPEsWgtGYrR3mu H8p1+7vDANeBmKM/bRG0OFb95KzT5HrujcRVcFcAH4XEwA01ykEKPx9pDYwjLfWnJUhh/mQNQ66 GnSHT+CD8V3t2udmwBiJaqmAl3hkZlRH8RjMgWZRcwymCdqtKwOEW7L2VXFxv8/TMmI9pBOuo/y q9mSOXW6l3QXTdCzsoKsoNXpssr7TDZICtHxrk/xmqFcuiDYvga1w9oCGR4ewKpWPnGvAr12e7E +XlmLUN0zZmvte6XKeLNrjhCTjgw4KaBuYutAi5BDEQrVOJyAyf8i0p9smXJSPjWQHFYAZ1PlOs uHMmI9spBbQ7zvM9BMNbvDfibeoSmG1r4jjv4obe8vjTidi7swAhPIJHyYobH0MBfSvwkha+ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-16_03,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 impostorscore=0 adultscore=0 malwarescore=0 mlxlogscore=999 suspectscore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 phishscore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505160079 Content-Type: text/plain; charset="utf-8" Add support for AD4080 high-speed, low noise, low distortion, 20-bit, Easy Drive, successive approximation register (SAR) analog-to-digital converter (ADC). Signed-off-by: Antoniu Miclaus --- changes in v6: - use _avail suffix - drop clk from ad4080_state - check ad4080_get_dec_rate return values for error codes - check if st->filter_type =3D=3D FILTER_NONE and update read/write raw fu= nctions. - update read_avail function for different filter types. - add extra macros/comments where needed. MAINTAINERS | 1 + drivers/iio/adc/Kconfig | 14 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/ad4080.c | 620 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 636 insertions(+) create mode 100644 drivers/iio/adc/ad4080.c diff --git a/MAINTAINERS b/MAINTAINERS index 244a4510bbc8..0038f7a078ae 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1323,6 +1323,7 @@ L: linux-iio@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml +F: drivers/iio/adc/ad4080.c =20 ANALOG DEVICES INC AD4130 DRIVER M: Cosmin Tanislav diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 27413516216c..17df328f5322 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -47,6 +47,20 @@ config AD4030 To compile this driver as a module, choose M here: the module will be called ad4030. =20 +config AD4080 + tristate "Analog Devices AD4080 high speed ADC" + depends on SPI + select REGMAP_SPI + select IIO_BACKEND + help + Say yes here to build support for Analog Devices AD4080 + high speed, low noise, low distortion, 20-bit, Easy Drive, + successive approximation register (SAR) analog-to-digital + converter (ADC). Supports iio_backended devices for AD4080. + + To compile this driver as a module, choose M here: the module will be + called ad4080. + config AD4130 tristate "Analog Device AD4130 ADC Driver" depends on SPI diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 9f26d5eca822..e6efed5b4e7a 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_AB8500_GPADC) +=3D ab8500-gpadc.o obj-$(CONFIG_AD_SIGMA_DELTA) +=3D ad_sigma_delta.o obj-$(CONFIG_AD4000) +=3D ad4000.o obj-$(CONFIG_AD4030) +=3D ad4030.o +obj-$(CONFIG_AD4080) +=3D ad4080.o obj-$(CONFIG_AD4130) +=3D ad4130.o obj-$(CONFIG_AD4695) +=3D ad4695.o obj-$(CONFIG_AD4851) +=3D ad4851.o diff --git a/drivers/iio/adc/ad4080.c b/drivers/iio/adc/ad4080.c new file mode 100644 index 000000000000..db79b754e065 --- /dev/null +++ b/drivers/iio/adc/ad4080.c @@ -0,0 +1,620 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Analog Devices AD4080 SPI ADC driver + * + * Copyright 2025 Analog Devices Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Register Definition */ +#define AD4080_REG_INTERFACE_CONFIG_A 0x00 +#define AD4080_REG_INTERFACE_CONFIG_B 0x01 +#define AD4080_REG_DEVICE_CONFIG 0x02 +#define AD4080_REG_CHIP_TYPE 0x03 +#define AD4080_REG_PRODUCT_ID_L 0x04 +#define AD4080_REG_PRODUCT_ID_H 0x05 +#define AD4080_REG_CHIP_GRADE 0x06 +#define AD4080_REG_SCRATCH_PAD 0x0A +#define AD4080_REG_SPI_REVISION 0x0B +#define AD4080_REG_VENDOR_L 0x0C +#define AD4080_REG_VENDOR_H 0x0D +#define AD4080_REG_STREAM_MODE 0x0E +#define AD4080_REG_TRANSFER_CONFIG 0x0F +#define AD4080_REG_INTERFACE_CONFIG_C 0x10 +#define AD4080_REG_INTERFACE_STATUS_A 0x11 +#define AD4080_REG_DEVICE_STATUS 0x14 +#define AD4080_REG_ADC_DATA_INTF_CONFIG_A 0x15 +#define AD4080_REG_ADC_DATA_INTF_CONFIG_B 0x16 +#define AD4080_REG_ADC_DATA_INTF_CONFIG_C 0x17 +#define AD4080_REG_PWR_CTRL 0x18 +#define AD4080_REG_GPIO_CONFIG_A 0x19 +#define AD4080_REG_GPIO_CONFIG_B 0x1A +#define AD4080_REG_GPIO_CONFIG_C 0x1B +#define AD4080_REG_GENERAL_CONFIG 0x1C +#define AD4080_REG_FIFO_WATERMARK_LSB 0x1D +#define AD4080_REG_FIFO_WATERMARK_MSB 0x1E +#define AD4080_REG_EVENT_HYSTERESIS_LSB 0x1F +#define AD4080_REG_EVENT_HYSTERESIS_MSB 0x20 +#define AD4080_REG_EVENT_DETECTION_HI_LSB 0x21 +#define AD4080_REG_EVENT_DETECTION_HI_MSB 0x22 +#define AD4080_REG_EVENT_DETECTION_LO_LSB 0x23 +#define AD4080_REG_EVENT_DETECTION_LO_MSB 0x24 +#define AD4080_REG_OFFSET_LSB 0x25 +#define AD4080_REG_OFFSET_MSB 0x26 +#define AD4080_REG_GAIN_LSB 0x27 +#define AD4080_REG_GAIN_MSB 0x28 +#define AD4080_REG_FILTER_CONFIG 0x29 + +/* AD4080_REG_INTERFACE_CONFIG_A Bit Definition */ +#define AD4080_INTERFACE_CONFIG_A_SW_RESET (BIT(7) | BIT(0)) +#define AD4080_INTERFACE_CONFIG_A_ADDR_ASC BIT(5) +#define AD4080_INTERFACE_CONFIG_A_SDO_ENABLE BIT(4) + +/* AD4080_REG_INTERFACE_CONFIG_B Bit Definition */ +#define AD4080_INTERFACE_CONFIG_B_SINGLE_INST BIT(7) +#define AD4080_INTERFACE_CONFIG_B_SHORT_INST BIT(3) + +/* AD4080_REG_DEVICE_CONFIG Bit Definition */ +#define AD4080_DEVICE_CONFIG_OPERATING_MODES_MSK GENMASK(1, 0) + +/* AD4080_REG_TRANSFER_CONFIG Bit Definition */ +#define AD4080_TRANSFER_CONFIG_KEEP_STREAM_LENGTH_VAL BIT(2) + +/* AD4080_REG_INTERFACE_CONFIG_C Bit Definition */ +#define AD4080_INTERFACE_CONFIG_C_STRICT_REG_ACCESS BIT(5) + +/* AD4080_REG_ADC_DATA_INTF_CONFIG_A Bit Definition */ +#define AD4080_ADC_DATA_INTF_CONFIG_A_RESERVED_CONFIG_A BIT(6) +#define AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN BIT(4) +#define AD4080_ADC_DATA_INTF_CONFIG_A_SPI_LVDS_LANES BIT(2) +#define AD4080_ADC_DATA_INTF_CONFIG_A_DATA_INTF_MODE BIT(0) + +/* AD4080_REG_ADC_DATA_INTF_CONFIG_B Bit Definition */ +#define AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK GENMASK(7, 4) +#define AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_SELF_CLK_MODE BIT(3) +#define AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_EN BIT(0) + +/* AD4080_REG_ADC_DATA_INTF_CONFIG_C Bit Definition */ +#define AD4080_ADC_DATA_INTF_CONFIG_C_LVDS_VOD_MSK GENMASK(6, 4) + +/* AD4080_REG_PWR_CTRL Bit Definition */ +#define AD4080_PWR_CTRL_ANA_DIG_LDO_PD BIT(1) +#define AD4080_PWR_CTRL_INTF_LDO_PD BIT(0) + +/* AD4080_REG_GPIO_CONFIG_A Bit Definition */ +#define AD4080_GPIO_CONFIG_A_GPO_1_EN BIT(1) +#define AD4080_GPIO_CONFIG_A_GPO_0_EN BIT(0) + +/* AD4080_REG_GPIO_CONFIG_B Bit Definition */ +#define AD4080_GPIO_CONFIG_B_GPIO_1_SEL_MSK GENMASK(7, 4) +#define AD4080_GPIO_CONFIG_B_GPIO_0_SEL_MSK GENMASK(3, 0) +#define AD4080_GPIO_CONFIG_B_GPIO_SPI_SDO 0 +#define AD4080_GPIO_CONFIG_B_GPIO_FIFO_FULL 1 +#define AD4080_GPIO_CONFIG_B_GPIO_FIFO_READ_DONE 2 +#define AD4080_GPIO_CONFIG_B_GPIO_FILTER_RES_RDY 3 +#define AD4080_GPIO_CONFIG_B_GPIO_H_THRESH 4 +#define AD4080_GPIO_CONFIG_B_GPIO_L_THRESH 5 +#define AD4080_GPIO_CONFIG_B_GPIO_STATUS_ALERT 6 +#define AD4080_GPIO_CONFIG_B_GPIO_GPIO_DATA 7 +#define AD4080_GPIO_CONFIG_B_GPIO_FILTER_SYNC 8 +#define AD4080_GPIO_CONFIG_B_GPIO_EXTERNAL_EVENT 9 + +/* AD4080_REG_FIFO_CONFIG Bit Definition */ +#define AD4080_FIFO_CONFIG_FIFO_MODE_MSK GENMASK(1, 0) + +/* AD4080_REG_FILTER_CONFIG Bit Definition */ +#define AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK GENMASK(6, 3) +#define AD4080_FILTER_CONFIG_FILTER_SEL_MSK GENMASK(1, 0) + +/* Miscellaneous Definitions */ +#define AD4080_SPI_READ BIT(7) +#define AD4080_CHIP_ID GENMASK(2, 0) + +#define AD4080_LVDS_CNV_CLK_CNT_MAX 7 + +#define AD4080_MAX_SAMP_FREQ 40000000 +#define AD4080_MIN_SAMP_FREQ 1250000 + +enum ad4080_filter_type { + FILTER_NONE, + SINC_1, + SINC_5, + SINC_5_COMP +}; + +static const unsigned int ad4080_scale_table[][2] =3D { + { 6000, 0 }, +}; + +static const char *const ad4080_filter_type_iio_enum[] =3D { + [FILTER_NONE] =3D "none", + [SINC_1] =3D "sinc1", + [SINC_5] =3D "sinc5", + [SINC_5_COMP] =3D "sinc5+pf1", +}; + +static const int ad4080_dec_rate_avail[] =3D { + 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, +}; + +static const int ad4080_dec_rate_none[] =3D { 1 }; + +static const char * const ad4080_power_supplies[] =3D { + "vdd33", "vdd11", "vddldo", "iovdd", "vrefin", +}; + +struct ad4080_chip_info { + const char *name; + unsigned int product_id; + int num_scales; + const unsigned int (*scale_table)[2]; + const struct iio_chan_spec *channels; + unsigned int num_channels; +}; + +struct ad4080_state { + struct regmap *regmap; + struct iio_backend *back; + const struct ad4080_chip_info *info; + /* + * Synchronize access to members the of driver state, and ensure + * atomicity of consecutive regmap operations. + */ + struct mutex lock; + unsigned int num_lanes; + unsigned int dec_rate; + unsigned long clk_rate; + enum ad4080_filter_type filter_type; + bool lvds_cnv_en; +}; + +static const struct regmap_config ad4080_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 8, + .read_flag_mask =3D BIT(7), + .max_register =3D 0x29, +}; + +static int ad4080_reg_access(struct iio_dev *indio_dev, unsigned int reg, + unsigned int writeval, unsigned int *readval) +{ + struct ad4080_state *st =3D iio_priv(indio_dev); + + if (readval) + return regmap_read(st->regmap, reg, readval); + + return regmap_write(st->regmap, reg, writeval); +} + +static int ad4080_get_scale(struct ad4080_state *st, int *val, int *val2) +{ + unsigned int tmp; + + tmp =3D (st->info->scale_table[0][0] * 1000000ULL) >> + st->info->channels[0].scan_type.realbits; + *val =3D tmp / 1000000; + *val2 =3D tmp % 1000000; + + return IIO_VAL_INT_PLUS_NANO; +} + +static unsigned int ad4080_get_dec_rate(struct iio_dev *dev, + const struct iio_chan_spec *chan) +{ + struct ad4080_state *st =3D iio_priv(dev); + int ret; + unsigned int data; + + ret =3D regmap_read(st->regmap, AD4080_REG_FILTER_CONFIG, &data); + if (ret) + return ret; + + return 1 << (FIELD_GET(AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK, data) + 1); +} + +static int ad4080_set_dec_rate(struct iio_dev *dev, + const struct iio_chan_spec *chan, + unsigned int mode) +{ + struct ad4080_state *st =3D iio_priv(dev); + + guard(mutex)(&st->lock); + + if ((st->filter_type >=3D SINC_5 && mode >=3D 512) || mode < 2) + return -EINVAL; + + return regmap_update_bits(st->regmap, AD4080_REG_FILTER_CONFIG, + AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK, + FIELD_PREP(AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK, + (ilog2(mode) - 1))); +} + +static int ad4080_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long m) +{ + struct ad4080_state *st =3D iio_priv(indio_dev); + int dec_rate; + + switch (m) { + case IIO_CHAN_INFO_SCALE: + return ad4080_get_scale(st, val, val2); + case IIO_CHAN_INFO_SAMP_FREQ: + dec_rate =3D ad4080_get_dec_rate(indio_dev, chan); + if (dec_rate < 0) + return dec_rate; + if (st->filter_type =3D=3D SINC_5_COMP) + dec_rate *=3D 2; + if (st->filter_type) + *val =3D DIV_ROUND_CLOSEST(st->clk_rate, dec_rate); + else + *val =3D st->clk_rate; + return IIO_VAL_INT; + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + if (st->filter_type =3D=3D FILTER_NONE) { + *val =3D 1; + } else { + *val =3D ad4080_get_dec_rate(indio_dev, chan); + if (*val < 0) + return *val; + } + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static int ad4080_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long mask) +{ + struct ad4080_state *st =3D iio_priv(indio_dev); + + switch (mask) { + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + if (st->filter_type =3D=3D FILTER_NONE && val > 1) + return -EINVAL; + + return ad4080_set_dec_rate(indio_dev, chan, val); + default: + return -EINVAL; + } +} + +static int ad4080_lvds_sync_write(struct ad4080_state *st) +{ + struct device *dev =3D regmap_get_device(st->regmap); + int ret; + + ret =3D regmap_set_bits(st->regmap, AD4080_REG_ADC_DATA_INTF_CONFIG_A, + AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN); + if (ret) + return ret; + + ret =3D iio_backend_interface_data_align(st->back, 10000); + if (ret) + return dev_err_probe(dev, ret, + "Data alignment process failed\n"); + + dev_dbg(dev, "Success: Pattern correct and Locked!\n"); + return regmap_clear_bits(st->regmap, AD4080_REG_ADC_DATA_INTF_CONFIG_A, + AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN); +} + +static ssize_t ad4080_get_filter_type(struct iio_dev *dev, + const struct iio_chan_spec *chan) +{ + struct ad4080_state *st =3D iio_priv(dev); + unsigned int data; + int ret; + + ret =3D regmap_read(st->regmap, AD4080_REG_FILTER_CONFIG, &data); + if (ret) + return ret; + + return FIELD_GET(AD4080_FILTER_CONFIG_FILTER_SEL_MSK, data); +} + +static int ad4080_set_filter_type(struct iio_dev *dev, + const struct iio_chan_spec *chan, + unsigned int mode) +{ + struct ad4080_state *st =3D iio_priv(dev); + int dec_rate; + int ret; + + guard(mutex)(&st->lock); + + dec_rate =3D ad4080_get_dec_rate(dev, chan); + if (dec_rate < 0) + return dec_rate; + + if (mode >=3D SINC_5 && dec_rate >=3D 512) + return -EINVAL; + + ret =3D iio_backend_filter_type_set(st->back, mode); + if (ret) + return ret; + + ret =3D regmap_update_bits(st->regmap, AD4080_REG_FILTER_CONFIG, + AD4080_FILTER_CONFIG_FILTER_SEL_MSK, + FIELD_PREP(AD4080_FILTER_CONFIG_FILTER_SEL_MSK, + mode)); + if (ret) + return ret; + + st->filter_type =3D mode; + + return 0; +} + +static int ad4080_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, int *length, + long mask) +{ + struct ad4080_state *st =3D iio_priv(indio_dev); + + switch (mask) { + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + switch (st->filter_type) { + case FILTER_NONE: + *vals =3D ad4080_dec_rate_none; + *length =3D ARRAY_SIZE(ad4080_dec_rate_none); + break; + default: + *vals =3D ad4080_dec_rate_avail; + *length =3D st->filter_type >=3D SINC_5 ? + (ARRAY_SIZE(ad4080_dec_rate_avail) - 2) : + ARRAY_SIZE(ad4080_dec_rate_avail); + break; + } + *type =3D IIO_VAL_INT; + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } +} + +static const struct iio_info ad4080_iio_info =3D { + .debugfs_reg_access =3D ad4080_reg_access, + .read_raw =3D ad4080_read_raw, + .write_raw =3D ad4080_write_raw, + .read_avail =3D ad4080_read_avail, +}; + +static const struct iio_enum ad4080_filter_type_enum =3D { + .items =3D ad4080_filter_type_iio_enum, + .num_items =3D ARRAY_SIZE(ad4080_filter_type_iio_enum), + .set =3D ad4080_set_filter_type, + .get =3D ad4080_get_filter_type, +}; + +static struct iio_chan_spec_ext_info ad4080_ext_info[] =3D { + IIO_ENUM("filter_type", IIO_SHARED_BY_ALL, &ad4080_filter_type_enum), + IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_ALL, + &ad4080_filter_type_enum), + { } +}; + +static const struct iio_chan_spec ad4080_channel =3D { + .type =3D IIO_VOLTAGE, + .indexed =3D 1, + .channel =3D 0, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_SCALE), + .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SAMP_FREQ) | + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + .info_mask_shared_by_all_available =3D + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + .ext_info =3D ad4080_ext_info, + .scan_index =3D 0, + .scan_type =3D { + .sign =3D 's', + .realbits =3D 20, + .storagebits =3D 32, + }, +}; + +static const struct ad4080_chip_info ad4080_chip_info =3D { + .name =3D "AD4080", + .product_id =3D AD4080_CHIP_ID, + .scale_table =3D ad4080_scale_table, + .num_scales =3D ARRAY_SIZE(ad4080_scale_table), + .num_channels =3D 1, + .channels =3D &ad4080_channel, +}; + +static int ad4080_setup(struct iio_dev *indio_dev) +{ + struct ad4080_state *st =3D iio_priv(indio_dev); + struct device *dev =3D regmap_get_device(st->regmap); + unsigned int id; + int ret; + + ret =3D regmap_write(st->regmap, AD4080_REG_INTERFACE_CONFIG_A, + AD4080_INTERFACE_CONFIG_A_SW_RESET); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4080_REG_INTERFACE_CONFIG_A, + AD4080_INTERFACE_CONFIG_A_SDO_ENABLE); + if (ret) + return ret; + + ret =3D regmap_read(st->regmap, AD4080_REG_CHIP_TYPE, &id); + if (ret) + return ret; + + if (id !=3D AD4080_CHIP_ID) + dev_info(dev, "Unrecognized CHIP_ID 0x%X\n", id); + + ret =3D regmap_set_bits(st->regmap, AD4080_REG_GPIO_CONFIG_A, + AD4080_GPIO_CONFIG_A_GPO_1_EN); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4080_REG_GPIO_CONFIG_B, + FIELD_PREP(AD4080_GPIO_CONFIG_B_GPIO_1_SEL_MSK, + AD4080_GPIO_CONFIG_B_GPIO_FILTER_RES_RDY)); + if (ret) + return ret; + + ret =3D iio_backend_num_lanes_set(st->back, st->num_lanes); + if (ret) + return ret; + + if (!st->lvds_cnv_en) + return 0; + + /* Set maximum LVDS Data Transfer Latency */ + ret =3D regmap_update_bits(st->regmap, + AD4080_REG_ADC_DATA_INTF_CONFIG_B, + AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK, + FIELD_PREP(AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK, + AD4080_LVDS_CNV_CLK_CNT_MAX)); + if (ret) + return ret; + + if (st->num_lanes > 1) { + ret =3D regmap_set_bits(st->regmap, AD4080_REG_ADC_DATA_INTF_CONFIG_A, + AD4080_ADC_DATA_INTF_CONFIG_A_SPI_LVDS_LANES); + if (ret) + return ret; + } + + ret =3D regmap_set_bits(st->regmap, + AD4080_REG_ADC_DATA_INTF_CONFIG_B, + AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_EN); + if (ret) + return ret; + + return ad4080_lvds_sync_write(st); +} + +static int ad4080_properties_parse(struct ad4080_state *st) +{ + struct device *dev =3D regmap_get_device(st->regmap); + + st->lvds_cnv_en =3D device_property_read_bool(dev, "adi,lvds-cnv-enable"); + + st->num_lanes =3D 1; + device_property_read_u32(dev, "adi,num-lanes", &st->num_lanes); + if (!st->num_lanes) + return dev_err_probe(dev, -EINVAL, + "Invalid 'adi,num-lanes' value: %u", + st->num_lanes); + + return 0; +} + +static int ad4080_probe(struct spi_device *spi) +{ + struct iio_dev *indio_dev; + struct device *dev =3D &spi->dev; + struct ad4080_state *st; + struct clk *clk; + int ret; + + indio_dev =3D devm_iio_device_alloc(&spi->dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st =3D iio_priv(indio_dev); + + ret =3D devm_regulator_bulk_get_enable(dev, + ARRAY_SIZE(ad4080_power_supplies), + ad4080_power_supplies); + if (ret) + return dev_err_probe(dev, ret, + "failed to get and enable supplies\n"); + + st->regmap =3D devm_regmap_init_spi(spi, &ad4080_regmap_config); + if (IS_ERR(st->regmap)) + return PTR_ERR(st->regmap); + + st->info =3D spi_get_device_match_data(spi); + if (!st->info) + return -ENODEV; + + ret =3D devm_mutex_init(dev, &st->lock); + if (ret) + return ret; + + indio_dev->name =3D st->info->name; + indio_dev->channels =3D st->info->channels; + indio_dev->num_channels =3D st->info->num_channels; + indio_dev->info =3D &ad4080_iio_info; + + ret =3D ad4080_properties_parse(st); + if (ret) + return ret; + + clk =3D devm_clk_get_enabled(&spi->dev, "cnv"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + st->clk_rate =3D clk_get_rate(clk); + + st->back =3D devm_iio_backend_get(dev, NULL); + if (IS_ERR(st->back)) + return PTR_ERR(st->back); + + ret =3D devm_iio_backend_request_buffer(dev, st->back, indio_dev); + if (ret) + return ret; + + ret =3D devm_iio_backend_enable(dev, st->back); + if (ret) + return ret; + + ret =3D ad4080_setup(indio_dev); + if (ret) + return ret; + + return devm_iio_device_register(&spi->dev, indio_dev); +} + +static const struct spi_device_id ad4080_id[] =3D { + { "ad4080", (kernel_ulong_t)&ad4080_chip_info }, + { } +}; +MODULE_DEVICE_TABLE(spi, ad4080_id); + +static const struct of_device_id ad4080_of_match[] =3D { + { .compatible =3D "adi,ad4080", &ad4080_chip_info }, + { } +}; +MODULE_DEVICE_TABLE(of, ad4080_of_match); + +static struct spi_driver ad4080_driver =3D { + .driver =3D { + .name =3D "ad4080", + .of_match_table =3D ad4080_of_match, + }, + .probe =3D ad4080_probe, + .id_table =3D ad4080_id, +}; +module_spi_driver(ad4080_driver); + +MODULE_AUTHOR("Antoniu Miclaus To: , , , , , CC: Antoniu Miclaus Subject: [PATCH v6 10/10] Documetation: ABI: add sinc1 and sinc5+pf1 filter Date: Fri, 16 May 2025 11:26:30 +0300 Message-ID: <20250516082630.8236-11-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250516082630.8236-1-antoniu.miclaus@analog.com> References: <20250516082630.8236-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: m04rQ1e6JqtfprfUJ3SBYs11rhIP_iMb X-Authority-Analysis: v=2.4 cv=MvdS63ae c=1 sm=1 tr=0 ts=6826f6d3 cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=dt9VzEwgFbYA:10 a=gAnH3GRIAAAA:8 a=BGrlU3uRz5xgvmwuAssA:9 a=+jEqtf1s3R9VXZ0wqowq2kgwd+I=:19 X-Proofpoint-ORIG-GUID: m04rQ1e6JqtfprfUJ3SBYs11rhIP_iMb X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE2MDA3OSBTYWx0ZWRfX+91QNo+Ok3zL rBNe1xhpWIEcw0M7U0HpFpYFxjA37bK7jWoqBHKwoKqNuxV504ph4+JZuVtFXFysbFLu2exZ6LQ vxI/Ru1u+W90PG7qkxt04XOwBaoYa6x+taxqFMdUrUXDLdGDVViEEpJyQJ7YL7x8s37fSGPCh1n YWoMBoFnNYlqDcXhVoTFPtyVyMEkzd6M/3xyuqvD2MrtCO6jofEpWPmBxgglh/X6Y689uUbZqUC lQWhk+Q9Kx53CRdac2dqzPnBlHo3J23H4DvME2tiLMY28B6TX2D449gTY+Dvbj1EEI6aFyIAcrC cLDcoRSy9PdYnshhmqFupYZ5ct1zrjYbpXA0csTsCzOpyh2XiWy+pwLTFA19ZHGcL3454iyXUlB RL8t2pHJDQHr91l1z4KXs0bVZuRYM+RnTXGzWIpAVqePrZOvBVJtWIxGy2/OF1wXlmalJ6fD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-16_03,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 impostorscore=0 adultscore=0 malwarescore=0 mlxlogscore=999 suspectscore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 phishscore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505160079 Content-Type: text/plain; charset="utf-8" Add sinc1 and sinc5+pf1 filter types used for ad4080 device. Include these two options into the filter_type available attribute. Add also the option for filter disabled. Signed-off-by: Antoniu Miclaus --- changes in v6: - add doc for filter "none". Documentation/ABI/testing/sysfs-bus-iio | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/te= sting/sysfs-bus-iio index b8838cb92d38..c67b63653441 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio +++ b/Documentation/ABI/testing/sysfs-bus-iio @@ -2275,6 +2275,9 @@ Description: Reading returns a list with the possible filter modes. Options for the attribute: =20 + * "none" - Filter is disabled/bypassed. + * "sinc1" - The digital sinc1 filter. Fast 1st + conversion time. Poor noise performance. * "sinc3" - The digital sinc3 filter. Moderate 1st conversion time. Good noise performance. * "sinc4" - Sinc 4. Excellent noise performance. Long @@ -2290,6 +2293,7 @@ Description: * "sinc3+pf2" - Sinc3 + device specific Post Filter 2. * "sinc3+pf3" - Sinc3 + device specific Post Filter 3. * "sinc3+pf4" - Sinc3 + device specific Post Filter 4. + * "sinc5+pf1" - Sinc5 + device specific Post Filter 1. =20 What: /sys/bus/iio/devices/iio:deviceX/filter_type What: /sys/bus/iio/devices/iio:deviceX/in_voltageY-voltageZ_filter_type --=20 2.49.0