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Thu, 15 May 2025 17:27:26 -0700 (PDT) From: John Clark To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Quentin Schulz , Jonas Karlman , Nicolas Frattaroli , Andrew Lunn , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, John Clark , Conor Dooley , Krzysztof Kozlowski Subject: [PATCH v5 1/3] dt-bindings: vendor-prefixes: Add luckfox prefix Date: Thu, 15 May 2025 20:27:11 -0400 Message-Id: <20250516002713.145026-2-inindev@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250516002713.145026-1-inindev@gmail.com> References: <20250516002713.145026-1-inindev@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add vendor prefix for Shenzhen Luckfox Technology Co., Ltd., which produces development boards like the Luckfox Omni3576. Signed-off-by: John Clark Acked-by: Conor Dooley Acked-by: Krzysztof Kozlowski Reviewed-by: Quentin Schulz --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 86f6a19b28ae..4fc73fbd592b 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -884,6 +884,8 @@ patternProperties: description: Nanjing Loongmasses Ltd. "^lsi,.*": description: LSI Corp. (LSI Logic) + "^luckfox,.*": + description: Shenzhen Luckfox Technology Co., Ltd. "^lunzn,.*": description: Shenzhen Lunzn Technology Co., Ltd. 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Thu, 15 May 2025 17:27:28 -0700 (PDT) From: John Clark To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Quentin Schulz , Jonas Karlman , Nicolas Frattaroli , Andrew Lunn , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, John Clark Subject: [PATCH v5 2/3] dt-bindings: arm: rockchip: Add Luckfox Omni3576 and Core3576 bindings Date: Thu, 15 May 2025 20:27:12 -0400 Message-Id: <20250516002713.145026-3-inindev@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250516002713.145026-1-inindev@gmail.com> References: <20250516002713.145026-1-inindev@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree binding for Luckfox Core3576 Module based boards, specifically the Luckfox Omni3576, with compatibility for the Rockchip RK3576 SoC. Signed-off-by: John Clark Reviewed-by: Quentin Schulz Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 5772d905f390..6e0b6e49a3bc 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -715,6 +715,13 @@ properties: - const: lckfb,tspi-rk3566 - const: rockchip,rk3566 =20 + - description: Luckfox Core3576 Module based boards + items: + - enum: + - luckfox,omni3576 + - const: luckfox,core3576 + - const: rockchip,rk3576 + - description: Lunzn FastRhino R66S / R68S items: - enum: --=20 2.39.5 From nobody Fri Dec 19 22:01:05 2025 Received: from mail-qt1-f181.google.com (mail-qt1-f181.google.com [209.85.160.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6ED9B2AD31; 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Thu, 15 May 2025 17:27:31 -0700 (PDT) Received: from localhost.localdomain ([216.237.233.165]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-494ae3cef1fsm4563991cf.9.2025.05.15.17.27.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 17:27:30 -0700 (PDT) From: John Clark To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Quentin Schulz , Jonas Karlman , Nicolas Frattaroli , Andrew Lunn , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, John Clark Subject: [PATCH v5 3/3] arm64: dts: rockchip: Add Luckfox Omni3576 Board support Date: Thu, 15 May 2025 20:27:13 -0400 Message-Id: <20250516002713.145026-4-inindev@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250516002713.145026-1-inindev@gmail.com> References: <20250516002713.145026-1-inindev@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add device tree for the Luckfox Omni3576 Carrier Board with Core3576 Module, powered by the Rockchip RK3576 SoC with four Cortex-A72 cores, four Cortex-A53 cores, and a Mali-G52 MC3 GPU. This initial implementation enables essential functionality for booting Linux and basic connectivity. Supported and tested features: - UART for serial console - SD card for storage - PCIe with NVMe SSD (detected, mounted, and fully functional) - USB 2.0 host ports - RK806 PMIC for power management - RTC with timekeeping and wake-up - GPIO-controlled LED with heartbeat trigger - eMMC (enabled, not populated on tested board) The device tree provides a foundation for further peripheral support, such as WiFi, MIPI-DSI, HDMI, and Ethernet, in future updates. Tested on Linux 6.15-rc4 Based on the Luckfox SDK, which derives from Rockchip=E2=80=99s SDK example= s, with relevant changes to align with upstream Linux. Signed-off-by: John Clark --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3576-luckfox-core3576.dtsi | 749 ++++++++++++++++++ .../dts/rockchip/rk3576-luckfox-omni3576.dts | 51 ++ 3 files changed, 801 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dt= si create mode 100644 arch/arm64/boot/dts/rockchip/rk3576-luckfox-omni3576.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 4bf84622db47..7fccebb7cdef 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -144,6 +144,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-wolfvision-pf5-= display-vz.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-wolfvision-pf5-io-expander.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3576-armsom-sige5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3576-evb1-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3576-luckfox-omni3576.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3576-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3576-rock-4d.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3582-radxa-e52c.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dtsi b/ar= ch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dtsi new file mode 100644 index 000000000000..9187012d6fa4 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dtsi @@ -0,0 +1,749 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * Copyright (c) 2025 John Clark + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "rk3576.dtsi" + +/ { + model =3D "Luckfox Core3576 Module"; + compatible =3D "luckfox,core3576","rockchip,rk3576"; + + aliases { + mmc0 =3D &sdhci; + }; + + chosen { + stdout-path =3D "serial0:1500000n8"; + }; + + hdmi-con { + compatible =3D "hdmi-connector"; + hdmi-pwr-supply =3D <&vcc_5v0_hdmi>; + type =3D "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint =3D <&hdmi_out_con>; + }; + }; + }; + + vbus_5v0_typec: regulator-vbus-5v0-typec { + compatible =3D "regulator-fixed"; + enable-active-high; + gpios =3D <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb_otg0_pwr_en>; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-name =3D "vbus5v0_typec"; + vin-supply =3D <&vcc_5v0_device>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-name =3D "vcc_1v1_nldo_s3"; + vin-supply =3D <&vcc_5v0_sys>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <2000000>; + regulator-max-microvolt =3D <2000000>; + regulator-name =3D "vcc_2v0_pldo_s3"; + vin-supply =3D <&vcc_5v0_sys>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3_pcie: regulator-vcc-3v3-pcie { + compatible =3D "regulator-fixed"; + enable-active-high; + gpios =3D <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie_pwr_en>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc_3v3_pcie"; + startup-delay-us =3D <1000>; + vin-supply =3D <&vcc_5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_rtc_s5: regulator-vcc-3v3-rtc-s5 { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc_3v3_rtc_s5"; + vin-supply =3D <&vcc_5v0_sys>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_5v0_dcin: regulator-vcc-5v0-dcin { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-name =3D "vcc_5v0_dcin"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_5v0_device: regulator-vcc-5v0-device { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-name =3D "vcc_5v0_device"; + vin-supply =3D <&vcc_5v0_dcin>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_5v0_hdmi: regulator-vcc-5v0-hdmi { + compatible =3D "regulator-fixed"; + enable-active-high; + gpios =3D <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hdmi_con_en>; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-name =3D "vcc_5v0_hdmi"; + vin-supply =3D <&vcc_5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_5v0_host: regulator-vcc-5v0-host { + compatible =3D "regulator-fixed"; + enable-active-high; + gpios =3D <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb_host_pwr_en>; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-name =3D "vcc_5v0_host"; + vin-supply =3D <&vcc_5v0_device>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_5v0_sys: regulator-vcc-5v0-sys { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-name =3D "vcc_5v0_sys"; + vin-supply =3D <&vcc_5v0_dcin>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; +}; + +&combphy0_ps { + status =3D "okay"; +}; + +&combphy1_psu { + status =3D "okay"; +}; + +&cpu_b0 { + cpu-supply =3D <&vdd_cpu_big_s0>; +}; + +&cpu_b1 { + cpu-supply =3D <&vdd_cpu_big_s0>; +}; + +&cpu_b2 { + cpu-supply =3D <&vdd_cpu_big_s0>; +}; + +&cpu_b3 { + cpu-supply =3D <&vdd_cpu_big_s0>; +}; + +&cpu_l0 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&gpu { + mali-supply =3D <&vdd_gpu_s0>; + status =3D "okay"; +}; + +&hdmi { + status =3D "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint =3D <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint =3D <&hdmi_con_in>; + }; +}; + +&hdptxphy { + status =3D "okay"; +}; + +&i2c1 { + status =3D "okay"; + + pmic@23 { + compatible =3D "rockchip,rk806"; + reg =3D <0x23>; + #gpio-cells =3D <2>; + gpio-controller; + interrupt-parent =3D <&gpio0>; + interrupts =3D <6 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + system-power-controller; + + vcc1-supply =3D <&vcc_5v0_sys>; + vcc2-supply =3D <&vcc_5v0_sys>; + vcc3-supply =3D <&vcc_5v0_sys>; + vcc4-supply =3D <&vcc_5v0_sys>; + vcc5-supply =3D <&vcc_5v0_sys>; + vcc6-supply =3D <&vcc_5v0_sys>; + vcc7-supply =3D <&vcc_5v0_sys>; + vcc8-supply =3D <&vcc_5v0_sys>; + vcc9-supply =3D <&vcc_5v0_sys>; + vcc10-supply =3D <&vcc_5v0_sys>; + vcc11-supply =3D <&vcc_2v0_pldo_s3>; + vcc12-supply =3D <&vcc_5v0_sys>; + vcc13-supply =3D <&vcc_1v1_nldo_s3>; + vcc14-supply =3D <&vcc_1v1_nldo_s3>; + vcca-supply =3D <&vcc_5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun0"; + }; + + rk806_dvs1_slp: dvs1-slp-pins { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun1"; + }; + + rk806_dvs1_pwrdn: dvs1-pwrdn-pins { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun2"; + }; + + rk806_dvs1_rst: dvs1-rst-pins { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun3"; + }; + + rk806_dvs2_slp: dvs2-slp-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun1"; + }; + + rk806_dvs2_pwrdn: dvs2-pwrdn-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun2"; + }; + + rk806_dvs2_rst: dvs2-rst-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun3"; + }; + + rk806_dvs2_dvs: dvs2-dvs-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun4"; + }; + + rk806_dvs2_gpio: dvs2-gpio-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun5"; + }; + + + rk806_dvs3_slp: dvs3-slp-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun1"; + }; + + rk806_dvs3_pwrdn: dvs3-pwrdn-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun2"; + }; + + rk806_dvs3_rst: dvs3-rst-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun3"; + }; + + rk806_dvs3_dvs: dvs3-dvs-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun4"; + }; + + rk806_dvs3_gpio: dvs3-gpio-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun5"; + }; + + regulators { + vdd_cpu_big_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_cpu_big_s0"; + regulator-enable-ramp-delay =3D <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_npu_s0"; + regulator-enable-ramp-delay =3D <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vcc_3v3_s3: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vdd_gpu_s0: dcdc-reg5 { + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <900000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_gpu_s0"; + regulator-enable-ramp-delay =3D <400>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + vddq_ddr_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_logic_s0: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <800000>; + regulator-name =3D "vdd_logic_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <1200000>; + regulator-name =3D "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcca_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo2_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcca1v8_pldo2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-name =3D "vdda_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcca_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcca1v8_pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "vdda_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v75_hdmi_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <837500>; + regulator-max-microvolt =3D <837500>; + regulator-name =3D "vdda0v75_hdmi_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "vdda_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "vdda_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c2 { + status =3D "okay"; + + hym8563: rtc@51 { + compatible =3D "haoyu,hym8563"; + reg =3D <0x51>; + #clock-cells =3D <0>; + clock-output-names =3D "hym8563"; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hym8563_int>; + wakeup-source; + }; +}; + +&pcie0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie_reset>; + reset-gpios =3D <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc_3v3_pcie>; + status =3D "okay"; +}; + +&pinctrl { + hdmi { + hdmi_con_en: hdmi-con-en { + rockchip,pins =3D <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins =3D <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcie { + pcie_pwr_en: pcie-pwr-en { + rockchip,pins =3D <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pcie_reset: pcie-reset { + rockchip,pins =3D <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + usb_host_pwr_en: usb-host-pwr-en { + rockchip,pins =3D <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg0_pwr_en: usb-otg0-pwr-en { + rockchip,pins =3D <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbc0_int: usbc0-int { + rockchip,pins =3D <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&rng { + status =3D "okay"; +}; + +&saradc { + vref-supply =3D <&vcca_1v8_s0>; + status =3D "okay"; +}; + +&sdhci { + bus-width =3D <8>; + full-pwr-cycle-in-suspend; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sd; + no-sdio; + non-removable; + vmmc-supply =3D <&vcc_3v3_s3>; + vqmmc-supply =3D <&vccio_sd_s0>; + status =3D "okay"; +}; + +&uart0 { + status =3D "okay"; +}; + +&uart4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart4m1_xfer &uart4m1_ctsn>; + status =3D "okay"; +}; + +&u2phy1 { + status =3D "okay"; +}; + +&u2phy1_otg { + phy-supply =3D <&vcc_5v0_host>; + status =3D "okay"; +}; + +&usb_drd1_dwc3 { + dr_mode =3D "host"; + status =3D "okay"; +}; + +&vop { + status =3D "okay"; +}; + +&vop_mmu { + status =3D "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg =3D ; + remote-endpoint =3D <&hdmi_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-luckfox-omni3576.dts b/arc= h/arm64/boot/dts/rockchip/rk3576-luckfox-omni3576.dts new file mode 100644 index 000000000000..6c75959adfe1 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-luckfox-omni3576.dts @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * Copyright (c) 2025 John Clark + */ + +/dts-v1/; + +#include "rk3576-luckfox-core3576.dtsi" + +/ { + model =3D "Luckfox Omni3576 Carrier Board"; + compatible =3D "luckfox,omni3576", "luckfox,core3576", "rockchip,rk3576"; + + aliases { + mmc1 =3D &sdmmc; + }; + + leds: leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&led_green_pin>; + + green_led: green-led { + color =3D ; + function =3D LED_FUNCTION_HEARTBEAT; + gpios =3D <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + }; + }; +}; + +&pinctrl { + leds { + led_green_pin: led-green-pin { + rockchip,pins =3D <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + bus-width =3D <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + no-sdio; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc_3v3_s3>; + vqmmc-supply =3D <&vccio_sd_s0>; + status =3D "okay"; +}; --=20 2.39.5