From nobody Fri Dec 19 20:19:08 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC0A423E34F; Fri, 16 May 2025 12:36:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747398971; cv=none; b=GtVBpY4OEu+xjngNGhnfb9JpeZiSEpB5wz0nfS4Az9ue+vB0V91jcw9fxnezRGHlbzm5zgn0gdUsIN/VUj8sHhxRErASVEfvNXtU5lbdz29r7+KQcDEhHTIP3oCmXJll1Xg7Cabpje68ZZ9/Hk0fxRXiXGEbJzIzDQZUGH2r1SM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747398971; c=relaxed/simple; bh=JWoWSWI2iFDqq31hCJJ8HrX1GSFoCvibN7mj9LxkFS0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VYVfcBfxWSOmZndlvQvRYKu/oyXey5G74F64sSXdFVGU2NJxz3LCqHWGfJGfwa7pLOj1c4xksMN9vS7ia8JHxVkG/gg99LSt4H/GIOpoJvGN842wXPuM8llVEWv7CawjHuaGotATJb4Prns+XOKy0/IwIKYDKZBwE6TEAzJjZ1E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=IiQ1cDHZ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="IiQ1cDHZ" Received: by smtp.kernel.org (Postfix) with ESMTPS id 5A7EDC4CEED; Fri, 16 May 2025 12:36:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747398970; bh=JWoWSWI2iFDqq31hCJJ8HrX1GSFoCvibN7mj9LxkFS0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=IiQ1cDHZbFjKJUyX8gXRWhq8zaa5TuQa6fJPmlKtYlungIBLP2uvjy1pJoilTjkEp jo+sypM3RkEUzfKnGIXChFNwGAz9yPan9TtO529WU+X6sGir4W4Jvfy+DLY0vcirIj R9JcAVyWQ6VmPs9v4kFYhiIODSWYar6KvdJ4cgjtqNO0VOgyKfCiyekqOm4R8XKCAp vaMst+lC11VA/OKn5VW/pbVg0VJxLk5DXy6c+jUEQH5JZlPp0qPc6k5/Ax8s0YlVLo yIXvtE5kWuvd5YOqLcwZQIzTcVEuz/jovGYydaylJHyxYnSGmLO7vfa8JpdlSaK8aQ 0r5Usd2TQUP6A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 474C9C3ABD8; Fri, 16 May 2025 12:36:10 +0000 (UTC) From: George Moussalem via B4 Relay Date: Fri, 16 May 2025 16:36:08 +0400 Subject: [PATCH v4 1/5] clk: qcom: ipq5018: keep XO clock always on Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250516-ipq5018-cmn-pll-v4-1-389a6b30e504@outlook.com> References: <20250516-ipq5018-cmn-pll-v4-0-389a6b30e504@outlook.com> In-Reply-To: <20250516-ipq5018-cmn-pll-v4-0-389a6b30e504@outlook.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Lee Jones , Konrad Dybcio , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747398968; l=3176; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=76iGGwYN7iao5R8Jw8ULkb9PNnmzQQ/WRzYbsqPI52M=; b=JWejKyFJlKcW3HeECybz+Ts56u28T+SVQOi5IdHrfuZ4/Nrcj6l4Kte/SMbl2bqIbGQIsaakQ SgQptU03TkuA1gFNPWB+H2rQcC1XkMPnxuFRH0qNQ0x/C2t6LkRqQqK X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The XO clock must not be disabled to avoid the kernel trying to disable the it. As such, keep the XO clock always on by flagging it as critical. Signed-off-by: George Moussalem Reviewed-by: Konrad Dybcio --- The kernel will panic when parenting it under the CMN PLL reference clock and the below message will appear in the kernel logs. [ 0.916515] ------------[ cut here ]------------ [ 0.918890] gcc_xo_clk_src status stuck at 'on' [ 0.918944] WARNING: CPU: 0 PID: 8 at drivers/clk/qcom/clk-branch.c:86 c= lk_branch_wait+0x114/0x124 [ 0.927926] Modules linked in: [ 0.936945] CPU: 0 PID: 8 Comm: kworker/0:0 Not tainted 6.6.74 #0 [ 0.939982] Hardware name: Linksys MX2000 (DT) [ 0.946151] Workqueue: pm pm_runtime_work [ 0.950489] pstate: 604000c5 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE= =3D--) [ 0.954566] pc : clk_branch_wait+0x114/0x124 [ 0.961335] lr : clk_branch_wait+0x114/0x124 [ 0.965849] sp : ffffffc08181bb50 [ 0.970101] x29: ffffffc08181bb50 x28: 0000000000000000 x27: 61c8864680b= 583eb [ 0.973317] x26: ffffff801fec2168 x25: ffffff800000abc0 x24: 00000000000= 00002 [ 0.980437] x23: ffffffc0809f6fd8 x22: 0000000000000000 x21: ffffffc0804= 4193c [ 0.985276] loop: module loaded [ 0.987554] x20: 0000000000000000 x19: ffffffc081749278 x18: 00000000000= 0007c [ 0.987573] x17: 0000000091706274 x16: 000000001985c4f7 x15: ffffffc0816= bbdf0 [ 0.987587] x14: 0000000000000174 x13: 000000000000007c x12: 00000000fff= fffea [ 0.987601] x11: 00000000ffffefff x10: ffffffc081713df0 x9 : ffffffc0816= bbd98 [ 0.987615] x8 : 0000000000017fe8 x7 : c0000000ffffefff x6 : 00000000000= 57fa8 [ 1.026268] x5 : 0000000000000fff x4 : 0000000000000000 x3 : ffffffc0818= 1b950 [ 1.033385] x2 : ffffffc0816bbd30 x1 : ffffffc0816bbd30 x0 : 00000000000= 00023 [ 1.040507] Call trace: [ 1.047618] clk_branch_wait+0x114/0x124 [ 1.049875] clk_branch2_disable+0x2c/0x3c [ 1.054043] clk_core_disable+0x60/0xac [ 1.057948] clk_core_disable+0x68/0xac [ 1.061681] clk_disable+0x30/0x4c [ 1.065499] pm_clk_suspend+0xd4/0xfc [ 1.068971] pm_generic_runtime_suspend+0x2c/0x44 [ 1.072705] __rpm_callback+0x40/0x1bc [ 1.077392] rpm_callback+0x6c/0x78 [ 1.081038] rpm_suspend+0xf0/0x5c0 [ 1.084423] pm_runtime_work+0xf0/0xfc [ 1.087895] process_one_work+0x17c/0x2f8 [ 1.091716] worker_thread+0x2e8/0x4d4 [ 1.095795] kthread+0xdc/0xe0 [ 1.099440] ret_from_fork+0x10/0x20 [ 1.102480] ---[ end trace 0000000000000000 ]--- --- drivers/clk/qcom/gcc-ipq5018.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c index 70f5dcb96700f55da1fb19fc893d22350a7e63bf..24eb4c40da63462077ee2e5714e= 838aa30ced2e3 100644 --- a/drivers/clk/qcom/gcc-ipq5018.c +++ b/drivers/clk/qcom/gcc-ipq5018.c @@ -1371,7 +1371,7 @@ static struct clk_branch gcc_xo_clk =3D { &gcc_xo_clk_src.clkr.hw, }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, + .flags =3D CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops =3D &clk_branch2_ops, }, }, --=20 2.49.0 From nobody Fri Dec 19 20:19:08 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1852523E354; Fri, 16 May 2025 12:36:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747398971; cv=none; b=QfAmzuk5TJ/pXppinK9wYAdmZfTqLpPWQxUxBBMvdiLAYEGQh61occk8EISC17OPNftNkRIogtXqm7SwUr4vo8eFdV3gOnM/C0xOaN0RC3nxw4F2Q0hvpH+zv6Y2qlmMXERKK5klDIFwwfweJCCxhCuOcUUYoB+h/eYVIV06qQA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747398971; c=relaxed/simple; bh=s6mJVg2trpUHXaM+kQ70RjDGFK4205sObTq4U0KZQ4U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bYxDgwGy4pvWo0qc3HD9CgS0aiIjrNg0TEfXCYFBONvXGKIpG4F1HRrK0fFr9GXSDZvHNX48ZVGrs43wYhaNmYL8ejQOwXnRRCZ3EDcXH6+TaLRyOWkeZtWHCkTHi9ekyAqvCEkhx1hZHDDisKQd3dTI1kuwM29SyW8xQ55BVjA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Cw3RtLGo; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Cw3RtLGo" Received: by smtp.kernel.org (Postfix) with ESMTPS id 6A531C4CEEB; Fri, 16 May 2025 12:36:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747398970; bh=s6mJVg2trpUHXaM+kQ70RjDGFK4205sObTq4U0KZQ4U=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Cw3RtLGoAbw+RG9lbPGU5gHUy/54hp1o8X2le+UEYHKoNEczQN3oL4+1j/XOrA/y6 xEeTrmp/bGBi9s5BuYbXf42Ox3sAs8qbeFi9a9gc6O2I1lcLKsyMduD4aOHPVXWqJJ Y5K4w+HGmz12ZO+RzlEGXa9CEKDspOnCZ9XBq2CsPDvmSloZhPbZStVu/4UbyQNlvR Y+1834R0ueOnOzxDwQE7yA/npc/CwGr3UGMdUH1GF4ZZiepgw6VBpobwr2XBSo20F+ AysmZ6Qpt5e5mL5M7w8k6MdIDyx8LUOV2qwvvM/ZHq6Ln+3eSI68zonDGag7m+MDZ9 RmH0NmWXOLAoQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58A9DC54756; Fri, 16 May 2025 12:36:10 +0000 (UTC) From: George Moussalem via B4 Relay Date: Fri, 16 May 2025 16:36:09 +0400 Subject: [PATCH v4 2/5] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250516-ipq5018-cmn-pll-v4-2-389a6b30e504@outlook.com> References: <20250516-ipq5018-cmn-pll-v4-0-389a6b30e504@outlook.com> In-Reply-To: <20250516-ipq5018-cmn-pll-v4-0-389a6b30e504@outlook.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Lee Jones , Konrad Dybcio , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747398968; l=1855; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=aD8B+18ScDcHtu0wgN3a3xFwWsO42AOs4yTmUEt8w/0=; b=1t7T12dLAup2G5W/T5ptKD9g4I6S+cJNO9uRGkXcoO+o320Sw+adzuRnOeew6OUTq8OiKr6kD lRxe0LFukJ/A3XaiUv9gDV0SR0/J1oM9sbUBK978u3TjwbTVH2si9oJ X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The CMN PLL block in the IPQ5018 SoC takes 96 MHZ as the reference input clock. Its output clocks are the XO (24Mhz), sleep (32Khz), and ethernet (50Mhz) clocks. Reviewed-by: Rob Herring (Arm) Signed-off-by: George Moussalem --- .../devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml | 1 + include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h | 16 ++++++++++++= ++++ 2 files changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.y= aml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml index cb6e09f4247f4b25105b25f4ae746c0b3ef47616..817d51135fbfdf0f518af1007ec= 7d6b120a91818 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml @@ -24,6 +24,7 @@ description: properties: compatible: enum: + - qcom,ipq5018-cmn-pll - qcom,ipq5424-cmn-pll - qcom,ipq9574-cmn-pll =20 diff --git a/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h b/include/dt-= bindings/clock/qcom,ipq5018-cmn-pll.h new file mode 100644 index 0000000000000000000000000000000000000000..586d1c9b33b374331bef413f543= c526212c18494 --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_IPQ5018_CMN_PLL_H +#define _DT_BINDINGS_CLK_QCOM_IPQ5018_CMN_PLL_H + +/* CMN PLL core clock. */ +#define IPQ5018_CMN_PLL_CLK 0 + +/* The output clocks from CMN PLL of IPQ5018. */ +#define IPQ5018_XO_24MHZ_CLK 1 +#define IPQ5018_SLEEP_32KHZ_CLK 2 +#define IPQ5018_ETH_50MHZ_CLK 3 +#endif --=20 2.49.0 From nobody Fri Dec 19 20:19:08 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 185E423E35D; Fri, 16 May 2025 12:36:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747398971; cv=none; b=FkJH7Eywl6ZwL+Rr0zHD9jHtQFEwG5AnNa+tLZpJr+/hw93L8Q8m9EzI0XOTvLMLd1SU8hOSvIQj2o/D0JFnBBaxPfbCi8H6qatC83LgKtVoHD23BJJ/223dqVmw8lWO7nCoC/MEcl69WV+Xz1dEAhZ75BOXbmm56zCYKexo8Lw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747398971; c=relaxed/simple; bh=WmKcPjeSa4QcrzycLdW5+c1w5YVhsYcAFwCdcwW0SVg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BuV++mHnV3Bmh7EZ+LIrZWFCn9rcgVPKcjglEpRcmEXoTgTDkD//Bc+q/9Kj6lzNfsLD7BzyLlSbckUlOpdS+3gIHBGD4jCJKhmDk5ab8YRwNBRPXDRqwSdrbY++SMHtdNV/4imR02Ui9oVwaJ55CLeJksnuPUehoXS2/wLdnFY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZhLcNiMG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZhLcNiMG" Received: by smtp.kernel.org (Postfix) with ESMTPS id 7D7EAC4CEF3; Fri, 16 May 2025 12:36:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747398970; bh=WmKcPjeSa4QcrzycLdW5+c1w5YVhsYcAFwCdcwW0SVg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ZhLcNiMG+mBR3uPrtHWprcN8tga2LIUBjviMFA4oNhmuUtu8ZDAPaP4BfRxqSuYXz hsLqOq/IG+3C3QptdeQD5du2KrtflO2xopB0Yq+f9zh6xdGVL3pvvdRe0hVGOOvKIH +90AaW1zTG35nv5uko9E133mTftzChzPJ/KLsJ4ndM4sX1AI/4c7p5UUNFN5PUvCCm AMqdzZOoXuFf/mZoH1FdUlb84pLLpO0N/EI4g6A84GnCwer+cwOoSyK28mkKHkhjpk d2CH3doIaSIysNwLJtTLUQNDSUCL5miaP2tYmwrXZBVmk3Gmg/yWexj65OOxL2KQwG 3JtHbUz//aQdg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7174CC3DA6D; Fri, 16 May 2025 12:36:10 +0000 (UTC) From: George Moussalem via B4 Relay Date: Fri, 16 May 2025 16:36:10 +0400 Subject: [PATCH v4 3/5] clk: qcom: ipq-cmn-pll: Add IPQ5018 SoC support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250516-ipq5018-cmn-pll-v4-3-389a6b30e504@outlook.com> References: <20250516-ipq5018-cmn-pll-v4-0-389a6b30e504@outlook.com> In-Reply-To: <20250516-ipq5018-cmn-pll-v4-0-389a6b30e504@outlook.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Lee Jones , Konrad Dybcio , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747398968; l=4052; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=S1ht5tbqwChz5d/8M60AjKhgKOu4DbMAJtGD2WfstW0=; b=cVIl4bA6gtpQmW+97QyVMEQnktjFtHLpItj4cl6LnltuQ2Dd6XnA8NdI2VkVFJixZSiP+q3yR GcKC7HxXuYtApwsYk0H+n5lFL2w+GD5Y5pJctVXjcDanUBFIGKf3EQH X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The CMN PLL in IPQ5018 SoC supplies fixed clocks to XO, sleep, and the ethernet block. Signed-off-by: George Moussalem --- drivers/clk/qcom/ipq-cmn-pll.c | 37 +++++++++++++++++++++++-------------- 1 file changed, 23 insertions(+), 14 deletions(-) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index b34d6faf67b8dd74402fabdb8dfe5ea52edd52f4..b3d7169c63e5fa7638fee80094a= 47746a0b6845e 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -50,6 +50,7 @@ #include =20 #include +#include #include =20 #define CMN_PLL_REFCLK_SRC_SELECTION 0x28 @@ -110,16 +111,10 @@ static const struct regmap_config ipq_cmn_pll_regmap_= config =3D { .fast_io =3D true, }; =20 -static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] =3D { - CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL), - CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), - CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), - CLK_PLL_OUTPUT(NSS_1200MHZ_CLK, "nss-1200mhz", 1200000000UL), - CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL), - CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL), - CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), - CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), - CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), +static const struct cmn_pll_fixed_output_clk ipq5018_output_clks[] =3D { + CLK_PLL_OUTPUT(IPQ5018_XO_24MHZ_CLK, "xo-24mhz", 24000000UL), + CLK_PLL_OUTPUT(IPQ5018_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), + CLK_PLL_OUTPUT(IPQ5018_ETH_50MHZ_CLK, "eth-50mhz", 50000000UL), { /* Sentinel */ } }; =20 @@ -136,6 +131,19 @@ static const struct cmn_pll_fixed_output_clk ipq5424_o= utput_clks[] =3D { { /* Sentinel */ } }; =20 +static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] =3D { + CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL), + CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), + CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), + CLK_PLL_OUTPUT(NSS_1200MHZ_CLK, "nss-1200mhz", 1200000000UL), + CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL), + CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL), + CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), + CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), + CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), + { /* Sentinel */ } +}; + /* * CMN PLL has the single parent clock, which supports the several * possible parent clock rates, each parent clock rate is reflected @@ -399,11 +407,11 @@ static int ipq_cmn_pll_clk_probe(struct platform_devi= ce *pdev) */ ret =3D pm_clk_add(dev, "ahb"); if (ret) - return dev_err_probe(dev, ret, "Fail to add AHB clock\n"); + return dev_err_probe(dev, ret, "Failed to add AHB clock\n"); =20 ret =3D pm_clk_add(dev, "sys"); if (ret) - return dev_err_probe(dev, ret, "Fail to add SYS clock\n"); + return dev_err_probe(dev, ret, "Failed to add SYS clock\n"); =20 ret =3D pm_runtime_resume_and_get(dev); if (ret) @@ -414,7 +422,7 @@ static int ipq_cmn_pll_clk_probe(struct platform_device= *pdev) pm_runtime_put(dev); if (ret) return dev_err_probe(dev, ret, - "Fail to register CMN PLL clocks\n"); + "Failed to register CMN PLL clocks\n"); =20 return 0; } @@ -439,8 +447,9 @@ static const struct dev_pm_ops ipq_cmn_pll_pm_ops =3D { }; =20 static const struct of_device_id ipq_cmn_pll_clk_ids[] =3D { - { .compatible =3D "qcom,ipq9574-cmn-pll", .data =3D &ipq9574_output_clks = }, + { .compatible =3D "qcom,ipq5018-cmn-pll", .data =3D &ipq5018_output_clks = }, { .compatible =3D "qcom,ipq5424-cmn-pll", .data =3D &ipq5424_output_clks = }, + { .compatible =3D "qcom,ipq9574-cmn-pll", .data =3D &ipq9574_output_clks = }, { } }; MODULE_DEVICE_TABLE(of, ipq_cmn_pll_clk_ids); --=20 2.49.0 From nobody Fri Dec 19 20:19:08 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1858823E35B; Fri, 16 May 2025 12:36:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747398971; cv=none; b=gCBWxZo02+iIZe9p0CjR8SkEi9kIdIqtFSpIOagUd3YhVaCXEIi7eMYnkugSTypndzw3ZNKBZ2ElHuwrYGL2t1DcFUTz1706Us+pn0fo9dast93AO8l6o/CSXtUAFikv70jERvYbSZO19bFUj3ucYByR6PnGEcYdkKebDa8qAPE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747398971; c=relaxed/simple; bh=tH7q3yefPxb4IsooUEN+J7VkPvPiR8uC8TZKq1fLbew=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NZuS75kgMmHlK9n9EFTiafMoIrTGMMtvD5FSZCFJ+2YodLDnHPiCwNp0azr1AB9W5DGwt9OPxCOa8zigINyUI3fMewszMerWhzYiTWhHSjLhB1LcdRZee6fMmYz4CAR9Jv5PSIKA4/WoNDLt0umvrqDfxIVb2n89pTC+7VEWB2U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=sarxlvIq; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="sarxlvIq" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8F5A7C4CEEF; Fri, 16 May 2025 12:36:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747398970; bh=tH7q3yefPxb4IsooUEN+J7VkPvPiR8uC8TZKq1fLbew=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=sarxlvIqDWP0UW1cOCdStom/lRxmOMupQtQ1xVMEOGVJnI/ZE1I8WJ5PSyH+XxiV8 75JSjbt6YaqSWtnVxdht18O7TyYA6mAdpA5CWVSc0FxXRpDKzTReLgBb/CdJxjZiJW f1TL5YTL7BX1rGMYg0bH5jNX0vbjz0zn7UzhI8eJAe3fDqgJBZ2Cj+oOtN7ioTTHLV QmGUV4xeCOZlHllRfI58WhtZ4jVLAJ0/7KMr4DVx4AtYbCQrr53YMfPjKmffp9YwUQ aEk35Vo38RqodNdEFRAjZAmjn4/RlN8bijGUimy8kMNGa4lzlNKXsRnOkfvFxJ4HU8 LZMFUNL0GlDCw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84F9BC3ABD8; Fri, 16 May 2025 12:36:10 +0000 (UTC) From: George Moussalem via B4 Relay Date: Fri, 16 May 2025 16:36:11 +0400 Subject: [PATCH v4 4/5] arm64: dts: ipq5018: Add CMN PLL node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250516-ipq5018-cmn-pll-v4-4-389a6b30e504@outlook.com> References: <20250516-ipq5018-cmn-pll-v4-0-389a6b30e504@outlook.com> In-Reply-To: <20250516-ipq5018-cmn-pll-v4-0-389a6b30e504@outlook.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Lee Jones , Konrad Dybcio , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747398968; l=2487; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=/8MkwsA8tkiEOngrTa6pfTHAzpGz2h90R2FK3FYJTt8=; b=XYGqWejlJkkk2QOrQ4iHC4vWGyTQHibWeBLP+ybPHgM+4pWwEHKPBsAsi+8tB1JI7Fzf+TmZu mEDeGuE2AtGCDD6oxgjgNAXdj7UMQ2bsRXsZ+UAQFwPLVDgyV9huMHe X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Add CMN PLL node for enabling output clocks to the networking hardware blocks on IPQ5018 devices. The reference clock of CMN PLL is routed from XO to the CMN PLL through the internal WiFi block. .XO (48 MHZ) --> WiFi (multiplier/divider)--> 96 MHZ to CMN PLL. Signed-off-by: George Moussalem Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 33 +++++++++++++++++++++++++++++++= -- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qc= om/ipq5018.dtsi index 130360014c5e14c778e348d37e601f60325b0b14..632caa94df51197ddaa85d17241= 2553e87cf89f3 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -2,12 +2,13 @@ /* * IPQ5018 SoC device tree source * - * Copyright (c) 2023 The Linux Foundation. All rights reserved. + * Copyright (c) 2023-2025 The Linux Foundation. All rights reserved. */ =20 #include -#include #include +#include +#include #include =20 / { @@ -16,6 +17,14 @@ / { #size-cells =3D <2>; =20 clocks { + ref_96mhz_clk: ref-96mhz-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&xo_clk>; + #clock-cells =3D <0>; + clock-div =3D <1>; + clock-mult =3D <2>; + }; + sleep_clk: sleep-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -25,6 +34,12 @@ xo_board_clk: xo-board-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; }; + + xo_clk: xo-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <48000000>; + }; }; =20 cpus { @@ -182,6 +197,20 @@ pcie0_phy: phy@86000 { status =3D "disabled"; }; =20 + cmn_pll: clock-controller@9b000 { + compatible =3D "qcom,ipq5018-cmn-pll"; + reg =3D <0x0009b000 0x800>; + clocks =3D <&ref_96mhz_clk>, + <&gcc GCC_CMN_BLK_AHB_CLK>, + <&gcc GCC_CMN_BLK_SYS_CLK>; + clock-names =3D "ref", + "ahb", + "sys"; + #clock-cells =3D <1>; + assigned-clocks =3D <&cmn_pll IPQ5018_CMN_PLL_CLK>; + assigned-clock-rates-u64 =3D /bits/ 64 <9600000000>; + }; + tlmm: pinctrl@1000000 { compatible =3D "qcom,ipq5018-tlmm"; reg =3D <0x01000000 0x300000>; --=20 2.49.0 From nobody Fri Dec 19 20:19:08 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CBBC23F42A; Fri, 16 May 2025 12:36:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747398971; cv=none; b=HIR0WKZIPSV2PYPe6MT7O7dU1abJN5WXQQlGxJp2ilxDcB9yJqAJD4dvqT1cw6sO6zGUt+b/4ZKGBBszOwc8ctsxGq7TAJoO9YIfJuUS8UmyzLgr0Cty8YXyb7Zp+KTPr3C/OyodVnUKYlMCV2btjfwaxSVCDdVc+AWaawhwOp0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747398971; c=relaxed/simple; bh=NlcddhlIsvALpOymexjZNwlcKloZ+Zh8gzl7Vb1hliA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BqNTAkJQQmrWVwsqugX9YDcCxepVLkOQJy8QjhOFRS7f0+8nVigBcvSlWzyXykF9UPB5GNV6pWNtDSS+d8z/dktF580QUureWScQNH7fNYaeY/xigWUV+gsmQ4gHyZDnwNS4ZKcG+hpXdjskX026BDUnyTU4JDOiJ6bh6K4xpi0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CRWj3jFx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CRWj3jFx" Received: by smtp.kernel.org (Postfix) with ESMTPS id A0FF6C4CEF1; Fri, 16 May 2025 12:36:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747398970; bh=NlcddhlIsvALpOymexjZNwlcKloZ+Zh8gzl7Vb1hliA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=CRWj3jFxm2/pMxV2zXXL7ANY/b5ILysunUlbfZ0N0ZrvBHbiuqejWrxzLDTpTjL9m Gn3wZFtkNqgrZfh412enTTkLfKSPxpqt6opJIwZXYBApZ3H+2/syM+Z+p049YI75T/ wfB3VtmRNedmQ53n2uryhl+EOUz4+HVAG6m2e7otJCj0FdybzGx/WOVp2WXAt2dg98 RYLkGoTJDKfNd2aaNIfKizWGySmqtheeO7DW5K7cHYSBL5PN/zs3zfKdVa9w2dncdA 0J9psMCxCEephZyGmkXbTjxqNdUzbtCEE/TaWvC/znjHopE571lAGH83A0HALibuNN RjhbMh/MjNLyw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9710EC54756; Fri, 16 May 2025 12:36:10 +0000 (UTC) From: George Moussalem via B4 Relay Date: Fri, 16 May 2025 16:36:12 +0400 Subject: [PATCH v4 5/5] arm64: dts: qcom: Update IPQ5018 xo_board_clk to use fixed factor clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250516-ipq5018-cmn-pll-v4-5-389a6b30e504@outlook.com> References: <20250516-ipq5018-cmn-pll-v4-0-389a6b30e504@outlook.com> In-Reply-To: <20250516-ipq5018-cmn-pll-v4-0-389a6b30e504@outlook.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Lee Jones , Konrad Dybcio , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747398968; l=2156; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=58pP2s4zb8WJ+mE2mDMygGM8IPCe9qeMD2Y23FgyIbQ=; b=FrSDQbOUgaNz6XJgeVsJrqrOzsAP/Gx3Bvptqc1MTQZ25bxlsplT7WTiNYh5xjzGEOyEirs9h OQrb5PrZBcHA1VmV+tRgvM/4VOr2ca+pwWtRi1YDadeAAqslHVyAg81 X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The xo_board_clk is fixed to 24 MHZ, which is routed from WiFi output clock 96 MHZ (also being the reference clock of CMN PLL) divided by 4 to the analog block routing channel. Update the xo_board_clk nodes in the board DTS files to use clock-div/clock-mult accordingly. Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 3 ++- arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts | 3 ++- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/bo= ot/dts/qcom/ipq5018-rdp432-c2.dts index 43def95e9275258041e7522ba4098a3767be3df1..df3cbb7c79c4e6c58cba7695691= 827fb8b84e451 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts @@ -120,5 +120,6 @@ &usbphy0 { }; =20 &xo_board_clk { - clock-frequency =3D <24000000>; + clock-div =3D <4>; + clock-mult =3D <1>; }; diff --git a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts b/a= rch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts index 5bb021cb29cd39cb95035bfac1bdbc976439838b..7a25af57749c8e8c9a6a1854378= 86b04b0d99e8e 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts +++ b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts @@ -124,5 +124,6 @@ uart_pins: uart-pins-state { }; =20 &xo_board_clk { - clock-frequency =3D <24000000>; + clock-div =3D <4>; + clock-mult =3D <1>; }; diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qc= om/ipq5018.dtsi index 632caa94df51197ddaa85d172412553e87cf89f3..8b5203554b170619f0c796c832b= a688ed45e656d 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -31,7 +31,8 @@ sleep_clk: sleep-clk { }; =20 xo_board_clk: xo-board-clk { - compatible =3D "fixed-clock"; + compatible =3D "fixed-factor-clock"; + clocks =3D <&ref_96mhz_clk>; #clock-cells =3D <0>; }; =20 --=20 2.49.0