From nobody Fri Dec 19 20:19:35 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E2B3F23771E; Fri, 16 May 2025 11:43:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747395788; cv=none; b=VdUEf2/LRFwK7uQikTciS6x+VcrSsJAlnDy77A5VjIyX8JFceS2RM5jnP/mehj2fqqGx0Wv39HC4b5yNxja90s2cc5Kkl4+EAIxTJDP1u7/LrzP0cNG1/Ph80SUZSuEVdAoqEfVtxTBweZWU8YGWFxhntL4vdDv1+b/NSBS3yMY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747395788; c=relaxed/simple; bh=JWoWSWI2iFDqq31hCJJ8HrX1GSFoCvibN7mj9LxkFS0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fFshRhajjuby0zuPAB4vY2QnhQAddLIwcb65cgqZJe3e+F4AU3zTyLeCxhq0sCPA8cTShtBxhyE3sVzcpekX1jMyVV8+fRmbrk3ABFBGAyrvcii1b6DMBwF0NzfpRyWm/j5atngFTH+jdNflsjBGe3fy67snUd4ehrwg1b29v/w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RFWZkolJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RFWZkolJ" Received: by smtp.kernel.org (Postfix) with ESMTPS id 698AFC4CEEB; Fri, 16 May 2025 11:43:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747395787; bh=JWoWSWI2iFDqq31hCJJ8HrX1GSFoCvibN7mj9LxkFS0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=RFWZkolJyy8sEv1iPgdNonksCqMhpINt97f3PoViysX0o+BSqRFMWfIrtIz82O46I qVqp6mMwuYRCQ90I7VG9vgESKSRlI9YTXaS+xhehuUJqPFIQiQZQHTjzv/VqMqr8Ij SFqVfvEr1cCooIFVCO/7f0qgFQcX5+zFZ0gDAxljXbTlwJH24bzhJgjcqr5bbTEfsZ qFWPDWcdECCgIoTYB4hq6etFR92TPaq35OQTZu3ZnhK1elal0v296CmpGPKPTuncNl xW//qowS6a6aB4//9I1CRE20bXE6f2TT29zFIIoS5NTUYubB+gjpJQVAiOI455v1Ka r3ZTbAvPy2+yg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56661C3ABD8; Fri, 16 May 2025 11:43:07 +0000 (UTC) From: George Moussalem via B4 Relay Date: Fri, 16 May 2025 15:43:04 +0400 Subject: [PATCH v3 1/5] clk: qcom: ipq5018: keep XO clock always on Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250516-ipq5018-cmn-pll-v3-1-f3867c5a2076@outlook.com> References: <20250516-ipq5018-cmn-pll-v3-0-f3867c5a2076@outlook.com> In-Reply-To: <20250516-ipq5018-cmn-pll-v3-0-f3867c5a2076@outlook.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Lee Jones , Konrad Dybcio , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747395784; l=3176; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=76iGGwYN7iao5R8Jw8ULkb9PNnmzQQ/WRzYbsqPI52M=; b=lRIKoG4O8Y6ZVZLIGRnXWA908cm1Q2k3Ghla9NIw/CI/f/mohI6TgZUlEDOcikSxo0Shbripz IMv57YIbhUHCkV+wZTR2lD7gbTgNrcWAt7Hi0ce9sf9kon1+SDIzEBp X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The XO clock must not be disabled to avoid the kernel trying to disable the it. As such, keep the XO clock always on by flagging it as critical. Signed-off-by: George Moussalem --- The kernel will panic when parenting it under the CMN PLL reference clock and the below message will appear in the kernel logs. [ 0.916515] ------------[ cut here ]------------ [ 0.918890] gcc_xo_clk_src status stuck at 'on' [ 0.918944] WARNING: CPU: 0 PID: 8 at drivers/clk/qcom/clk-branch.c:86 c= lk_branch_wait+0x114/0x124 [ 0.927926] Modules linked in: [ 0.936945] CPU: 0 PID: 8 Comm: kworker/0:0 Not tainted 6.6.74 #0 [ 0.939982] Hardware name: Linksys MX2000 (DT) [ 0.946151] Workqueue: pm pm_runtime_work [ 0.950489] pstate: 604000c5 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE= =3D--) [ 0.954566] pc : clk_branch_wait+0x114/0x124 [ 0.961335] lr : clk_branch_wait+0x114/0x124 [ 0.965849] sp : ffffffc08181bb50 [ 0.970101] x29: ffffffc08181bb50 x28: 0000000000000000 x27: 61c8864680b= 583eb [ 0.973317] x26: ffffff801fec2168 x25: ffffff800000abc0 x24: 00000000000= 00002 [ 0.980437] x23: ffffffc0809f6fd8 x22: 0000000000000000 x21: ffffffc0804= 4193c [ 0.985276] loop: module loaded [ 0.987554] x20: 0000000000000000 x19: ffffffc081749278 x18: 00000000000= 0007c [ 0.987573] x17: 0000000091706274 x16: 000000001985c4f7 x15: ffffffc0816= bbdf0 [ 0.987587] x14: 0000000000000174 x13: 000000000000007c x12: 00000000fff= fffea [ 0.987601] x11: 00000000ffffefff x10: ffffffc081713df0 x9 : ffffffc0816= bbd98 [ 0.987615] x8 : 0000000000017fe8 x7 : c0000000ffffefff x6 : 00000000000= 57fa8 [ 1.026268] x5 : 0000000000000fff x4 : 0000000000000000 x3 : ffffffc0818= 1b950 [ 1.033385] x2 : ffffffc0816bbd30 x1 : ffffffc0816bbd30 x0 : 00000000000= 00023 [ 1.040507] Call trace: [ 1.047618] clk_branch_wait+0x114/0x124 [ 1.049875] clk_branch2_disable+0x2c/0x3c [ 1.054043] clk_core_disable+0x60/0xac [ 1.057948] clk_core_disable+0x68/0xac [ 1.061681] clk_disable+0x30/0x4c [ 1.065499] pm_clk_suspend+0xd4/0xfc [ 1.068971] pm_generic_runtime_suspend+0x2c/0x44 [ 1.072705] __rpm_callback+0x40/0x1bc [ 1.077392] rpm_callback+0x6c/0x78 [ 1.081038] rpm_suspend+0xf0/0x5c0 [ 1.084423] pm_runtime_work+0xf0/0xfc [ 1.087895] process_one_work+0x17c/0x2f8 [ 1.091716] worker_thread+0x2e8/0x4d4 [ 1.095795] kthread+0xdc/0xe0 [ 1.099440] ret_from_fork+0x10/0x20 [ 1.102480] ---[ end trace 0000000000000000 ]--- --- drivers/clk/qcom/gcc-ipq5018.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c index 70f5dcb96700f55da1fb19fc893d22350a7e63bf..24eb4c40da63462077ee2e5714e= 838aa30ced2e3 100644 --- a/drivers/clk/qcom/gcc-ipq5018.c +++ b/drivers/clk/qcom/gcc-ipq5018.c @@ -1371,7 +1371,7 @@ static struct clk_branch gcc_xo_clk =3D { &gcc_xo_clk_src.clkr.hw, }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, + .flags =3D CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops =3D &clk_branch2_ops, }, }, --=20 2.49.0 From nobody Fri Dec 19 20:19:35 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E2AE42376EB; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kfflWfnH" Received: by smtp.kernel.org (Postfix) with ESMTPS id 75BD9C4CEED; Fri, 16 May 2025 11:43:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747395787; bh=s6mJVg2trpUHXaM+kQ70RjDGFK4205sObTq4U0KZQ4U=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=kfflWfnH7Ko8lZDRBiL0AoQD7Gk6lYLgrj9carIlh9ISwYCn7LqGX+zJoxoI241jW Vw1VNOC5MikzGA2Og5ZJDbefWUHsQkMhxVZm4vL10N0c8DgArsq+kSvIRWkLoiKl3W HzK1ZcO3DEMUgW9BHWS3mGrDZ8vVNXYe0VLxQim9MderFPDqBswa+GWMuYMdSNEVfK NEldpPuVrcPANKB5uqvcwzUfs3Z0UVuYFHS9cLdFWPwIzPBIJ0irAuL96TGerEoeIe EQ8eQk4RhkaI5uX5Uv7sDEeE86d5WemBD+VF3ynsX1Qnc5zZ2A+esQKNxtdnLnYYmM 28sUoeJ2S5+Iw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64C96C3ABDD; Fri, 16 May 2025 11:43:07 +0000 (UTC) From: George Moussalem via B4 Relay Date: Fri, 16 May 2025 15:43:05 +0400 Subject: [PATCH v3 2/5] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250516-ipq5018-cmn-pll-v3-2-f3867c5a2076@outlook.com> References: <20250516-ipq5018-cmn-pll-v3-0-f3867c5a2076@outlook.com> In-Reply-To: <20250516-ipq5018-cmn-pll-v3-0-f3867c5a2076@outlook.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Lee Jones , Konrad Dybcio , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747395784; l=1855; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=aD8B+18ScDcHtu0wgN3a3xFwWsO42AOs4yTmUEt8w/0=; b=ggusxMAiNh1P6l+yIUj0dmH5Os8r/sWqU5XPHACRD/cF4pzbLw0cctLk1clr6ipW8ItEiHCYe yuzi8BSLpy/AEpj2ZYmbxYA5lH4GzXcGAHJ7DDNg8S8FuPOJlCnFKht X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The CMN PLL block in the IPQ5018 SoC takes 96 MHZ as the reference input clock. Its output clocks are the XO (24Mhz), sleep (32Khz), and ethernet (50Mhz) clocks. Reviewed-by: Rob Herring (Arm) Signed-off-by: George Moussalem --- .../devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml | 1 + include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h | 16 ++++++++++++= ++++ 2 files changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.y= aml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml index cb6e09f4247f4b25105b25f4ae746c0b3ef47616..817d51135fbfdf0f518af1007ec= 7d6b120a91818 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml @@ -24,6 +24,7 @@ description: properties: compatible: enum: + - qcom,ipq5018-cmn-pll - qcom,ipq5424-cmn-pll - qcom,ipq9574-cmn-pll =20 diff --git a/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h b/include/dt-= bindings/clock/qcom,ipq5018-cmn-pll.h new file mode 100644 index 0000000000000000000000000000000000000000..586d1c9b33b374331bef413f543= c526212c18494 --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_IPQ5018_CMN_PLL_H +#define _DT_BINDINGS_CLK_QCOM_IPQ5018_CMN_PLL_H + +/* CMN PLL core clock. */ +#define IPQ5018_CMN_PLL_CLK 0 + +/* The output clocks from CMN PLL of IPQ5018. */ +#define IPQ5018_XO_24MHZ_CLK 1 +#define IPQ5018_SLEEP_32KHZ_CLK 2 +#define IPQ5018_ETH_50MHZ_CLK 3 +#endif --=20 2.49.0 From nobody Fri Dec 19 20:19:35 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E29B641760; Fri, 16 May 2025 11:43:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747395788; cv=none; b=V6r4gMbMFapdoTEIkjL20l4jrHKYZVOuzJGtn7TH3qwrRLURkcnEAip2aT0ezFQAMZFRGDMi3PH3r2bk1OW68uxBXW+xWk5C8M4k7PGYHsen+2g+IarKofuhYmtXip+a+AXoRNwqro1XlV38VhhZrAIDVApM72263AslTuquO5g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747395788; c=relaxed/simple; bh=WmKcPjeSa4QcrzycLdW5+c1w5YVhsYcAFwCdcwW0SVg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GiSW/+wv2ofIYZ2TxkD5zq1pdcoujW7QYSqR/fdryjnhHJBZPg2CeMxVYd0JcnLVh5lYvu/LrijHjQGbDzTS29TXhfTndBK3dvFkphA4sfLTS+kvErcZJi93xdEdWeFKv6gw3MCwz9hUR9iV6sAIMoyMuPtL78t4mB0u+Ks64yg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SJKMPaLg; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SJKMPaLg" Received: by smtp.kernel.org (Postfix) with ESMTPS id 81A35C4CEEF; Fri, 16 May 2025 11:43:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747395787; bh=WmKcPjeSa4QcrzycLdW5+c1w5YVhsYcAFwCdcwW0SVg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=SJKMPaLgPydrXPIPj8zoYrEEbN9C0EVTvh7nEYywmBPRze+k4qEV2YC4Jkp79Z3fN mDCmEipAG25DqH9ojHYIsGbx4UYF53xzpMr2ClLYr6B3P5RAphZBb0T1MqPlJS2PmH UousGbkXNkgDfSvS7GWwOGnw0SCw2cY6o0Dh8FVtCrZ9edOOghffSTZ0mmItB2PaNG XncUdOJubi4x0hXl2Eg+Ge4mHf40IKWtQIptYP+KQVy8HGaOXxHSQ9Hjf+eSPyXrzN +YP88ojB/BdC89WIQr45dCTRay06FBJbj/pdfzxDCMrd1a47gxgO1g97rpq1uWFiex rHiz/PExCmgZQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71A86C54756; Fri, 16 May 2025 11:43:07 +0000 (UTC) From: George Moussalem via B4 Relay Date: Fri, 16 May 2025 15:43:06 +0400 Subject: [PATCH v3 3/5] clk: qcom: ipq-cmn-pll: Add IPQ5018 SoC support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250516-ipq5018-cmn-pll-v3-3-f3867c5a2076@outlook.com> References: <20250516-ipq5018-cmn-pll-v3-0-f3867c5a2076@outlook.com> In-Reply-To: <20250516-ipq5018-cmn-pll-v3-0-f3867c5a2076@outlook.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Lee Jones , Konrad Dybcio , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747395784; l=4052; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=S1ht5tbqwChz5d/8M60AjKhgKOu4DbMAJtGD2WfstW0=; b=Hi+M4YQe40Iv0r8LXUpsPGkIzCPL0+6ho7VpJ9E+kfYL3jn4K9YWzVr9jgYkpRubgnKKqsVzN ruOkaOZS07dDHpJxdy7+aGx8DZVHgF8rBX9cbPeki5bDks+b4vKYDTB X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The CMN PLL in IPQ5018 SoC supplies fixed clocks to XO, sleep, and the ethernet block. Signed-off-by: George Moussalem --- drivers/clk/qcom/ipq-cmn-pll.c | 37 +++++++++++++++++++++++-------------- 1 file changed, 23 insertions(+), 14 deletions(-) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index b34d6faf67b8dd74402fabdb8dfe5ea52edd52f4..b3d7169c63e5fa7638fee80094a= 47746a0b6845e 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -50,6 +50,7 @@ #include =20 #include +#include #include =20 #define CMN_PLL_REFCLK_SRC_SELECTION 0x28 @@ -110,16 +111,10 @@ static const struct regmap_config ipq_cmn_pll_regmap_= config =3D { .fast_io =3D true, }; =20 -static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] =3D { - CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL), - CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), - CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), - CLK_PLL_OUTPUT(NSS_1200MHZ_CLK, "nss-1200mhz", 1200000000UL), - CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL), - CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL), - CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), - CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), - CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), +static const struct cmn_pll_fixed_output_clk ipq5018_output_clks[] =3D { + CLK_PLL_OUTPUT(IPQ5018_XO_24MHZ_CLK, "xo-24mhz", 24000000UL), + CLK_PLL_OUTPUT(IPQ5018_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), + CLK_PLL_OUTPUT(IPQ5018_ETH_50MHZ_CLK, "eth-50mhz", 50000000UL), { /* Sentinel */ } }; =20 @@ -136,6 +131,19 @@ static const struct cmn_pll_fixed_output_clk ipq5424_o= utput_clks[] =3D { { /* Sentinel */ } }; =20 +static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] =3D { + CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL), + CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), + CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), + CLK_PLL_OUTPUT(NSS_1200MHZ_CLK, "nss-1200mhz", 1200000000UL), + CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL), + CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL), + CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), + CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), + CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), + { /* Sentinel */ } +}; + /* * CMN PLL has the single parent clock, which supports the several * possible parent clock rates, each parent clock rate is reflected @@ -399,11 +407,11 @@ static int ipq_cmn_pll_clk_probe(struct platform_devi= ce *pdev) */ ret =3D pm_clk_add(dev, "ahb"); if (ret) - return dev_err_probe(dev, ret, "Fail to add AHB clock\n"); + return dev_err_probe(dev, ret, "Failed to add AHB clock\n"); =20 ret =3D pm_clk_add(dev, "sys"); if (ret) - return dev_err_probe(dev, ret, "Fail to add SYS clock\n"); + return dev_err_probe(dev, ret, "Failed to add SYS clock\n"); =20 ret =3D pm_runtime_resume_and_get(dev); if (ret) @@ -414,7 +422,7 @@ static int ipq_cmn_pll_clk_probe(struct platform_device= *pdev) pm_runtime_put(dev); if (ret) return dev_err_probe(dev, ret, - "Fail to register CMN PLL clocks\n"); + "Failed to register CMN PLL clocks\n"); =20 return 0; } @@ -439,8 +447,9 @@ static const struct dev_pm_ops ipq_cmn_pll_pm_ops =3D { }; =20 static const struct of_device_id ipq_cmn_pll_clk_ids[] =3D { - { .compatible =3D "qcom,ipq9574-cmn-pll", .data =3D &ipq9574_output_clks = }, + { .compatible =3D "qcom,ipq5018-cmn-pll", .data =3D &ipq5018_output_clks = }, { .compatible =3D "qcom,ipq5424-cmn-pll", .data =3D &ipq5424_output_clks = }, + { .compatible =3D "qcom,ipq9574-cmn-pll", .data =3D &ipq9574_output_clks = }, { } }; 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Fri, 16 May 2025 11:43:07 +0000 (UTC) From: George Moussalem via B4 Relay Date: Fri, 16 May 2025 15:43:07 +0400 Subject: [PATCH v3 4/5] arm64: dts: ipq5018: Add CMN PLL node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250516-ipq5018-cmn-pll-v3-4-f3867c5a2076@outlook.com> References: <20250516-ipq5018-cmn-pll-v3-0-f3867c5a2076@outlook.com> In-Reply-To: <20250516-ipq5018-cmn-pll-v3-0-f3867c5a2076@outlook.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Lee Jones , Konrad Dybcio , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747395784; l=1868; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=i8rlTNHd6kvpsl8Y56j+yL6A694vfBenSJxiKk+mwOY=; b=Ykxm8UWWNr4u121oM6w2fcnntkQq94oohD7NCtZWepN0eqnthG8/eKoKUs0mNtMeg2icbra7j dI5u5HMcFe8DaNQ3c7sCVs2dMPkNE5lHbxiefMLvSNfR30co/Wc4X/Y X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Add CMN PLL node for enabling output clocks to the networking hardware blocks on IPQ5018 devices. The reference clock of CMN PLL is routed from XO to the CMN PLL through the internal WiFi block. .XO (48 MHZ) --> WiFi (multiplier/divider)--> 96 MHZ to CMN PLL. Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qc= om/ipq5018.dtsi index 130360014c5e14c778e348d37e601f60325b0b14..6d33cc196f8e61e30deb485b071= 5255c5e833e38 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -2,12 +2,13 @@ /* * IPQ5018 SoC device tree source * - * Copyright (c) 2023 The Linux Foundation. All rights reserved. + * Copyright (c) 2023-2025 The Linux Foundation. All rights reserved. */ =20 #include -#include #include +#include +#include #include =20 / { @@ -16,6 +17,14 @@ / { #size-cells =3D <2>; =20 clocks { + ref_96mhz_clk: ref-96mhz-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&xo_clk>; + #clock-cells =3D <0>; + clock-div =3D <1>; + clock-mult =3D <2>; + }; + sleep_clk: sleep-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -25,6 +34,12 @@ xo_board_clk: xo-board-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; }; + + xo_clk: xo-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <48000000>; + }; }; =20 cpus { --=20 2.49.0 From nobody Fri Dec 19 20:19:35 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8ABF523C50B; Fri, 16 May 2025 11:43:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747395788; cv=none; b=hzwswlPOa+mkJA3ik6cSciXo61SgeCw5FrLwbMefPgElFn+LzYjigtzFv4+CQHPMX/YTiKot9zrOcaW+21QAOG12bBkOFt5bWOI/53xp+061SlmoxyqPJhIpYr5izkb6FtIdG10IR/tKnc1VBMlXUq5CWYHHB0bwNAd3w9MzCiA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747395788; c=relaxed/simple; bh=37F8XH+GAKZ//Tj61nrwPRcylir/pNEVzfMJfqa3dVI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uATQq50tPELjBmZ2f0nuV/fVx6w0ZOJSjk2UNY6aC7bUgd+TApoqHuyvfoSjySK6MBlQ+3DKVPZ4cYdVN09SRM1X8Rn42QWGiZNAOIAd8rlSzZbAyTAJSx2n5rfkMGzfbvCF9pJTmLCH6Yge4rKmr3lMmrtzfK+0aBa8C4CzDfo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cf73/0jB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cf73/0jB" Received: by smtp.kernel.org (Postfix) with ESMTPS id 97792C4AF1B; Fri, 16 May 2025 11:43:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747395787; bh=37F8XH+GAKZ//Tj61nrwPRcylir/pNEVzfMJfqa3dVI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=cf73/0jBEXl0G0qXWNj2P5vV9DisDxxfBC+NfDvScoSxDB7Mb3shrXx1aFpVJ2Wwg +z6MGwv2kYUld1l9CMEX+0OcYMCIKXG3I7pI1odT5o+RYle3QZCrN01fFQl/W5z65B UwiwK0U4blRKDtwxXeYBQVjoOc+PC596r3cfvfR/QsRBSHnwf93wwJW/imDc39MRCa hpECFOHaPgCTylVGCmqqGlcHoOZ2V+S0hkUKT83hvJM4UQRQ8TzpfLAsQcGFJhweLh ojkOmfcAlLKvRoYlkB2p3adNs/nE/35cOjeZnrxguhdVnIkqALOs1IT9rLNmrF6qBj M1BPHjWAtZTDg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D692C3ABD8; Fri, 16 May 2025 11:43:07 +0000 (UTC) From: George Moussalem via B4 Relay Date: Fri, 16 May 2025 15:43:08 +0400 Subject: [PATCH v3 5/5] arm64: dts: qcom: Update IPQ5018 xo_board_clk to use fixed factor clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250516-ipq5018-cmn-pll-v3-5-f3867c5a2076@outlook.com> References: <20250516-ipq5018-cmn-pll-v3-0-f3867c5a2076@outlook.com> In-Reply-To: <20250516-ipq5018-cmn-pll-v3-0-f3867c5a2076@outlook.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Lee Jones , Konrad Dybcio , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747395784; l=2156; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=Kavlla7VqPYVz8RPprQ6zbDxT2pqDYQ1B/kyLZsoD2U=; b=VFJNeLuEWwF+md2+fD/y3r4F6cnclXmET2DLsNq5Zi2l8RPBeJ82mK/NpVIATCI0RX2LNURaO psPl7qt5+zvCJLA+pWBkpSNbY44FHwAlkYbT2V0BlRThD5V7f3DZ+BA X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The xo_board_clk is fixed to 24 MHZ, which is routed from WiFi output clock 96 MHZ (also being the reference clock of CMN PLL) divided by 4 to the analog block routing channel. Update the xo_board_clk nodes in the board DTS files to use clock-div/clock-mult accordingly. Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 3 ++- arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts | 3 ++- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/bo= ot/dts/qcom/ipq5018-rdp432-c2.dts index 43def95e9275258041e7522ba4098a3767be3df1..df3cbb7c79c4e6c58cba7695691= 827fb8b84e451 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts @@ -120,5 +120,6 @@ &usbphy0 { }; =20 &xo_board_clk { - clock-frequency =3D <24000000>; + clock-div =3D <4>; + clock-mult =3D <1>; }; diff --git a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts b/a= rch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts index 5bb021cb29cd39cb95035bfac1bdbc976439838b..7a25af57749c8e8c9a6a1854378= 86b04b0d99e8e 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts +++ b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts @@ -124,5 +124,6 @@ uart_pins: uart-pins-state { }; =20 &xo_board_clk { - clock-frequency =3D <24000000>; + clock-div =3D <4>; + clock-mult =3D <1>; }; diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qc= om/ipq5018.dtsi index 6d33cc196f8e61e30deb485b0715255c5e833e38..36429730815d4b740511a2ec1b5= 0f823a730262b 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -31,7 +31,8 @@ sleep_clk: sleep-clk { }; =20 xo_board_clk: xo-board-clk { - compatible =3D "fixed-clock"; + compatible =3D "fixed-factor-clock"; + clocks =3D <&ref_96mhz_clk>; #clock-cells =3D <0>; }; =20 --=20 2.49.0