From nobody Fri Dec 19 18:56:24 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 733A913B284; Fri, 16 May 2025 14:12:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747404763; cv=none; b=f4Xm/0i/3bhlIpOGPyTiqvu++jUUDD3U7iIzXsum8TS6OoCIAb0EyLnvVlhE0rbl+z2pzs03j05Cp6OKvtzcTGjtaVmICHwIzyrb8bCbN0ghpojE0tRXYLzWPem1PnqOvxqJe+MxNbs9YDMktR3tsiHqEQU9HQHyf+aoDFhqetQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747404763; c=relaxed/simple; bh=tASrtAWlxRnbRRu8X1Omf+YcuIOtQV8Chp1OjDdP3Jw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FfqXlF2SlfIawy5jM8C+PrVD1tSk7xJJQo2m/WACb+UT8NvV835OjPztHyHqyfv4qBvDkImXY0Ab5Co1YlPc+MA2TwzY1Fk5OIO/VHcL2+wHIQ4OuwNuxl8zfMkztBuGJzGw4/6h18uRbFHOXfty60szbPgVqb36rraPNg7im+U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=YX+H/h0C; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="YX+H/h0C" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1747404754; bh=tASrtAWlxRnbRRu8X1Omf+YcuIOtQV8Chp1OjDdP3Jw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=YX+H/h0Cz/cb7Pt6kxO0uyXrguWbs+zzB//6WAmD4pu1M1IAYm0PoJxdFtVtpOH6x enXQrGiwzQr24VizDpfOWszxxw81D6H+meYmI+8OdSKW+F9Ay74//2tyq27ztR6enz EY+vPzTD6f4bWu7fU6fLD/9z0xofJu2iwx8htiww66BxyqfqYCzYQjLg0Fd5apqW+4 0JluDARpO3YWsR2sc+hPAZ5hY35dtg/ZaM2vHP8m/RFIABqbZjvi2espQCnb4OQhH8 myLuYeJzLwEaefb8ufJ2CJHgmsap9GcKdZnQHhpGjsQtANWzOMvtViKz9rFOQf0z8E 9YxdNn0WrvwLg== Received: from 2a01cb0892f2d600c8f85cf092d4af51.ipv6.abo.wanadoo.fr (2a01cb0892F2d600C8F85Cf092D4af51.ipv6.abo.wanadoo.fr [IPv6:2a01:cb08:92f2:d600:c8f8:5cf0:92d4:af51]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: jmassot) by bali.collaboradmins.com (Postfix) with ESMTPSA id BF38417E049F; Fri, 16 May 2025 16:12:33 +0200 (CEST) From: Julien Massot Date: Fri, 16 May 2025 16:12:13 +0200 Subject: [PATCH v2 1/2] dt-bindings: clock: mediatek: Add #reset-cells property for MT8188 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250516-dtb-check-mt8188-v2-1-fb60bef1b8e1@collabora.com> References: <20250516-dtb-check-mt8188-v2-0-fb60bef1b8e1@collabora.com> In-Reply-To: <20250516-dtb-check-mt8188-v2-0-fb60bef1b8e1@collabora.com> To: kernel@collabora.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Garmin Chang , Friday Yang Cc: Conor Dooley , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Julien Massot X-Mailer: b4 0.14.2 The '#reset-cells' property is permitted for some of the MT8188 clock controllers, but not listed as a valid property. Fixes: 9a5cd59640ac ("dt-bindings: clock: mediatek: Add SMI LARBs reset for= MT8188") Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Julien Massot Acked-by: Conor Dooley --- Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.= yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml index 2985c8c717d72888dd49f1f6249a9e2594d8a38d..5403242545ab12a7736ed4fbac2= 6008aa955c724 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml @@ -52,6 +52,9 @@ properties: '#clock-cells': const: 1 =20 + '#reset-cells': + const: 1 + required: - compatible - reg --=20 2.49.0 From nobody Fri Dec 19 18:56:24 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A261B145B3F; Fri, 16 May 2025 14:12:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747404764; cv=none; b=qM8uvMixkUVBKwDBDa7c2d+L+9oBhSJ+VrjI6rEyyYQUpHuv9gjqeahHHQVzclyHaWz2Td8XUmLiqGokPXLh3R1r2sq6H7zCfYuEEjFTU5+o5cX05kuTlWXZkuBG3ntvQriJGtqtMt6EdvLlQX5B9ffcor5mTgfMB+3czIj2xfU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747404764; c=relaxed/simple; bh=0CSU94FT+xS94/kzp81hGRLzb7zJ0Npr8p6nJ4MCPu8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hnRb7tZaYfBRrq5YPC+zqhLep4ZPF3XQRGBrY69VvZ/NMkheicc48vy/SjvTNbwoKIB95emgW+MhWL/P+zmAT5tG08DJVCUvND1pivdlAbXdU8vo/T018UoLa+zzuYmnsXfFWv9lZRKjyMd+H0IrXqK6DsnglYkQs4RG/XhBT/A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=m8bDrcPj; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="m8bDrcPj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1747404755; bh=0CSU94FT+xS94/kzp81hGRLzb7zJ0Npr8p6nJ4MCPu8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=m8bDrcPj92fPYm2aI5X3kkNHKlsbrWcFm9FlUwlVsEyOUa+uvEY5wdByupYCOJ6+T 5/R4m6YpYN084Xu+owhQ1faFtnTPR8F8a/hxOMCKekPeLRD5BTUJuRid4hZ5RUrwQ+ KoKcdydrXaNOf3iTowJqSp1/IYgDSEnu2jVgPkOOqzRoatm5jo2VUE4JJjMAEViMjz gzz7dYFdg9BL0DVjMsvsOHWmwWEiOJYZfDhCtTI9qEOeeEe0XUks6uC1G8U/FUwEsJ 5Ly0a32GoLQjzYMtLJ/D+mwQnvWSl0LazpoF4ci2rOYa4mlH+s2WlSTu/0hiIA9JIc GktEs1pgnUCig== Received: from 2a01cb0892f2d600c8f85cf092d4af51.ipv6.abo.wanadoo.fr (2a01cb0892F2d600C8F85Cf092D4af51.ipv6.abo.wanadoo.fr [IPv6:2a01:cb08:92f2:d600:c8f8:5cf0:92d4:af51]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: jmassot) by bali.collaboradmins.com (Postfix) with ESMTPSA id A9F8A17E05F0; Fri, 16 May 2025 16:12:34 +0200 (CEST) From: Julien Massot Date: Fri, 16 May 2025 16:12:14 +0200 Subject: [PATCH v2 2/2] arm64: dts: mediatek: mt8188: Add missing #reset-cells property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250516-dtb-check-mt8188-v2-2-fb60bef1b8e1@collabora.com> References: <20250516-dtb-check-mt8188-v2-0-fb60bef1b8e1@collabora.com> In-Reply-To: <20250516-dtb-check-mt8188-v2-0-fb60bef1b8e1@collabora.com> To: kernel@collabora.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Garmin Chang , Friday Yang Cc: Conor Dooley , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Julien Massot X-Mailer: b4 0.14.2 The binding now require the '#reset-cells' property but the devicetree has not been updated which trigger dtb-check errors. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Julien Massot --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index 296090fbaf4953db8075f72073509b731dc41e51..dec6ce3e94e92c8e1e2c3680cb3= 584394d9058bd 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -2647,36 +2647,42 @@ imgsys1_dip_top: clock-controller@15110000 { compatible =3D "mediatek,mt8188-imgsys1-dip-top"; reg =3D <0 0x15110000 0 0x1000>; #clock-cells =3D <1>; + #reset-cells =3D <1>; }; =20 imgsys1_dip_nr: clock-controller@15130000 { compatible =3D "mediatek,mt8188-imgsys1-dip-nr"; reg =3D <0 0x15130000 0 0x1000>; #clock-cells =3D <1>; + #reset-cells =3D <1>; }; =20 imgsys_wpe1: clock-controller@15220000 { compatible =3D "mediatek,mt8188-imgsys-wpe1"; reg =3D <0 0x15220000 0 0x1000>; #clock-cells =3D <1>; + #reset-cells =3D <1>; }; =20 ipesys: clock-controller@15330000 { compatible =3D "mediatek,mt8188-ipesys"; reg =3D <0 0x15330000 0 0x1000>; #clock-cells =3D <1>; + #reset-cells =3D <1>; }; =20 imgsys_wpe2: clock-controller@15520000 { compatible =3D "mediatek,mt8188-imgsys-wpe2"; reg =3D <0 0x15520000 0 0x1000>; #clock-cells =3D <1>; + #reset-cells =3D <1>; }; =20 imgsys_wpe3: clock-controller@15620000 { compatible =3D "mediatek,mt8188-imgsys-wpe3"; reg =3D <0 0x15620000 0 0x1000>; #clock-cells =3D <1>; + #reset-cells =3D <1>; }; =20 camsys: clock-controller@16000000 { @@ -2689,24 +2695,28 @@ camsys_rawa: clock-controller@1604f000 { compatible =3D "mediatek,mt8188-camsys-rawa"; reg =3D <0 0x1604f000 0 0x1000>; #clock-cells =3D <1>; + #reset-cells =3D <1>; }; =20 camsys_yuva: clock-controller@1606f000 { compatible =3D "mediatek,mt8188-camsys-yuva"; reg =3D <0 0x1606f000 0 0x1000>; #clock-cells =3D <1>; + #reset-cells =3D <1>; }; =20 camsys_rawb: clock-controller@1608f000 { compatible =3D "mediatek,mt8188-camsys-rawb"; reg =3D <0 0x1608f000 0 0x1000>; #clock-cells =3D <1>; + #reset-cells =3D <1>; }; =20 camsys_yuvb: clock-controller@160af000 { compatible =3D "mediatek,mt8188-camsys-yuvb"; reg =3D <0 0x160af000 0 0x1000>; #clock-cells =3D <1>; + #reset-cells =3D <1>; }; =20 ccusys: clock-controller@17200000 { --=20 2.49.0