From nobody Wed Dec 17 04:18:10 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B92F29B23D for ; Thu, 15 May 2025 20:21:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747340512; cv=none; b=d/G/O8TifIfv3md7VFgxspvKklJOCbJ6Zc5NTFNkBGG6z7XgZzyUTcAq9x47++1zCzvgF8/fz8V3haOT232ZvJ0ak0Uq39GCVKQzEf+8QYgIbIGP/QWf9UiU+ir6z3c3lYjOPEJXCCcvKfPhagJh1M5WvmZV+cbaj67Q+IxYbU4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747340512; c=relaxed/simple; bh=wUjjHir9umYBfWcexces7fjBYJ2cljh8IHV5teLVlBE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rqnwx4yQ1ljx1NG7oeQogpWsfxH2lPGU/WaiGKa3Aa+WRlpkB1XkoMlJ+GXzs9AFdMCxgrU7BN2dHwEWASfs9GpmL1nQ/QUSBU4wCB49ytfz2ZKrTJWE4B+DlBYxdUaEGtcsW1OEnQ1M5ZHXV02whgkYHdoDg1MD5AHYwBBwzGc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=vXMntWkX; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=DKDqw928; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="vXMntWkX"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="DKDqw928" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1747340508; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gI+qgdHH/JNK7szxkvKUfIqBaaHnasCVQthfpsDd22E=; b=vXMntWkXHSNkqIpjSGV4h70t5Zm6J+BkhOg8iLA6BNZea8akHp51yH55rb5AuM+Jy6usKA DYKc7GfpzE3XHJzA29G29zX43K15R01HcDIsqGIlPXnzVAvl4NKpOW56Z0+wf+sH12UlUO iW3mkMy4DlNCyi5xaZw1OuSoFmUEVJtlK0m/dC+4chxTdqpZio4JXYydRl0ohO94gRDnyu ajtT0B54hDGIkdW0eN0ld+iWsIkoKzJIcBL+XZy005kFI3nKz2MMjRlJ3MgPiPu1w5YOK5 zCtzYzyvtiinXdAW8pi+SydTOY7AuNduK6Du1uQXEoAv86GpqTKNVU24AY1EhA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1747340508; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gI+qgdHH/JNK7szxkvKUfIqBaaHnasCVQthfpsDd22E=; b=DKDqw928cHNjETjJU23HtPCCUqLi0oqZd1hA78Tb+jO0/fHHUgf1r2Cr6of2zEOSO5ABP5 2BefXbQ4ycugUlDw== To: Ingo Molnar , Borislav Petkov , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 1/2] x86/cpuid: Fix CPUID(0x2) iterator kernel-doc Date: Thu, 15 May 2025 22:21:41 +0200 Message-ID: <20250515202143.34448-2-darwi@linutronix.de> In-Reply-To: <20250515202143.34448-1-darwi@linutronix.de> References: <20250515202143.34448-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The CPUID(0x2) cache/TLB descriptors iterator has been recently changed from: for_each_leaf_0x2_entry(regs, __ptr, entry) to: for_each_cpuid_0x2_desc(_regs, _ptr, _desc) but the attached kernel-doc was not fully adapted. Fix it. Fixes: c4c9ea879c3b ("x86/cpuid: Rename cpuid_get_leaf_0x2_regs() to cpuid_= leaf_0x2()") Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/api.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index bf97f9770789..ccf20c62b89f 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -252,15 +252,15 @@ static inline void cpuid_leaf_0x2(union leaf_0x2_regs= *regs) =20 /** * for_each_cpuid_0x2_desc() - Iterator for parsed CPUID(0x2) descriptors - * @regs: CPUID(0x2) register output, as returned by cpuid_leaf_0x2() - * @__ptr: u8 pointer, for macro internal use only - * @desc: Pointer to parsed CPUID(0x2) descriptor at each iteration + * @_regs: CPUID(0x2) register output, as returned by cpuid_leaf_0x2() + * @_ptr: u8 pointer, for macro internal use only + * @_desc: Pointer to the parsed CPUID(0x2) descriptor at each iteration * * Loop over the 1-byte descriptors in the passed CPUID(0x2) output regist= ers - * @regs. Provide the parsed information for each descriptor through @des= c. + * @_regs. Provide the parsed information for each descriptor through @_d= esc. * - * To handle cache-specific descriptors, switch on @entry->c_type. For TLB - * descriptors, switch on @entry->t_type. + * To handle cache-specific descriptors, switch on @_desc->c_type. For TLB + * descriptors, switch on @_desc->t_type. * * Example usage for cache descriptors:: * --=20 2.49.0 From nobody Wed Dec 17 04:18:10 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4324729B786 for ; Thu, 15 May 2025 20:21:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747340515; cv=none; b=T7RmhUH+IvXscxWSNuyUyZfrPUnndp3so3Z6rrYxhftp3iUoMY0wFK2LHwbfWUKOYGlxSaEORwAeWbuHWGhg/RoPeh+4lcGusacpIuTC581OTaJrwFSGsjqnAnNgRxy8gVadi5Ua6BnEY8nU8KuH8BpYHIj0lYUlQSUrpOaVae0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747340515; c=relaxed/simple; bh=mJfCC/iRmdk2M7MvZLIWog78RJ8ElfIQyxW4zW2+VQ8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=a8SlIA8MV47sSBDyZKc4hZMj6ZJ/MpeBaT9aUJN46lvj1u6VKiLz3CrU0KTowd45v57qCq0S5IYe+Dy+um4ZevlzwLsFAOSzQ/PZrrNGCjsiqFO0Ks0Eb3VtwjOvwa4AqTWB32UgDB2n3n8C4AXdmYfthD/0w+6PUjOLmtxEosM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=N9omGqi/; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=eaNcOIgz; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="N9omGqi/"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="eaNcOIgz" From: "Ahmed S. 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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 2/2] x86/cpuid: Rename hypervisor_cpuid_base() to cpuid_hypervisor_base() Date: Thu, 15 May 2025 22:21:42 +0200 Message-ID: <20250515202143.34448-3-darwi@linutronix.de> In-Reply-To: <20250515202143.34448-1-darwi@linutronix.de> References: <20250515202143.34448-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In order to let all the APIs under have a shared "cpuid_" namespace, rename hypervisor_cpuid_base() to cpuid_base_hypervisor(). To align with the new style, also rename: for_each_possible_hypervisor_cpuid_base(function) to: for_each_possible_cpuid_base_hypervisor(function) Adjust call-sites accordingly. Suggested-by: Ingo Molnar Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/acrn.h | 2 +- arch/x86/include/asm/cpuid/api.h | 6 +++--- arch/x86/include/asm/xen/hypervisor.h | 2 +- arch/x86/kernel/jailhouse.c | 2 +- arch/x86/kernel/kvm.c | 2 +- arch/x86/kvm/cpuid.c | 2 +- 6 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/acrn.h b/arch/x86/include/asm/acrn.h index 1dd14381bcb6..fab11192c60a 100644 --- a/arch/x86/include/asm/acrn.h +++ b/arch/x86/include/asm/acrn.h @@ -25,7 +25,7 @@ void acrn_remove_intr_handler(void); static inline u32 acrn_cpuid_base(void) { if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) - return hypervisor_cpuid_base("ACRNACRNACRN", 0); + return cpuid_base_hypervisor("ACRNACRNACRN", 0); =20 return 0; } diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index ccf20c62b89f..44fa82e1267c 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -188,14 +188,14 @@ static __always_inline bool cpuid_function_is_indexed= (u32 function) return false; } =20 -#define for_each_possible_hypervisor_cpuid_base(function) \ +#define for_each_possible_cpuid_base_hypervisor(function) \ for (function =3D 0x40000000; function < 0x40010000; function +=3D 0x100) =20 -static inline u32 hypervisor_cpuid_base(const char *sig, u32 leaves) +static inline u32 cpuid_base_hypervisor(const char *sig, u32 leaves) { u32 base, eax, signature[3]; =20 - for_each_possible_hypervisor_cpuid_base(base) { + for_each_possible_cpuid_base_hypervisor(base) { cpuid(base, &eax, &signature[0], &signature[1], &signature[2]); =20 /* diff --git a/arch/x86/include/asm/xen/hypervisor.h b/arch/x86/include/asm/x= en/hypervisor.h index bd0fc69a10a7..c2fc7869b996 100644 --- a/arch/x86/include/asm/xen/hypervisor.h +++ b/arch/x86/include/asm/xen/hypervisor.h @@ -43,7 +43,7 @@ extern struct start_info *xen_start_info; =20 static inline uint32_t xen_cpuid_base(void) { - return hypervisor_cpuid_base(XEN_SIGNATURE, 2); + return cpuid_base_hypervisor(XEN_SIGNATURE, 2); } =20 struct pci_dev; diff --git a/arch/x86/kernel/jailhouse.c b/arch/x86/kernel/jailhouse.c index cd8ed1edbf9e..9e9a591a5fec 100644 --- a/arch/x86/kernel/jailhouse.c +++ b/arch/x86/kernel/jailhouse.c @@ -49,7 +49,7 @@ static uint32_t jailhouse_cpuid_base(void) !boot_cpu_has(X86_FEATURE_HYPERVISOR)) return 0; =20 - return hypervisor_cpuid_base("Jailhouse\0\0\0", 0); + return cpuid_base_hypervisor("Jailhouse\0\0\0", 0); } =20 static uint32_t __init jailhouse_detect(void) diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c index f3642226e0a5..921c1c783bc1 100644 --- a/arch/x86/kernel/kvm.c +++ b/arch/x86/kernel/kvm.c @@ -875,7 +875,7 @@ static noinline uint32_t __kvm_cpuid_base(void) return 0; /* So we don't blow up on old processors */ =20 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) - return hypervisor_cpuid_base(KVM_SIGNATURE, 0); + return cpuid_base_hypervisor(KVM_SIGNATURE, 0); =20 return 0; } diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 7f43d8d24fbe..ecd85f4801cc 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -236,7 +236,7 @@ static struct kvm_hypervisor_cpuid kvm_get_hypervisor_c= puid(struct kvm_vcpu *vcp struct kvm_cpuid_entry2 *entry; u32 base; =20 - for_each_possible_hypervisor_cpuid_base(base) { + for_each_possible_cpuid_base_hypervisor(base) { entry =3D kvm_find_cpuid_entry(vcpu, base); =20 if (entry) { --=20 2.49.0