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([91.197.138.148]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f395166fsm59310785e9.18.2025.05.15.01.23.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 01:23:53 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Samuel Holland , Andrew Jones , Deepak Gupta Subject: [PATCH v7 09/14] riscv: misaligned: move emulated access uniformity check in a function Date: Thu, 15 May 2025 10:22:10 +0200 Message-ID: <20250515082217.433227-10-cleger@rivosinc.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250515082217.433227-1-cleger@rivosinc.com> References: <20250515082217.433227-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Split the code that check for the uniformity of misaligned accesses performance on all cpus from check_unaligned_access_emulated_all_cpus() to its own function which will be used for delegation check. No functional changes intended. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Andrew Jones --- arch/riscv/kernel/traps_misaligned.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index e551ba17f557..287ec37021c8 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -647,6 +647,18 @@ bool __init check_vector_unaligned_access_emulated_all= _cpus(void) } #endif =20 +static bool all_cpus_unaligned_scalar_access_emulated(void) +{ + int cpu; + + for_each_online_cpu(cpu) + if (per_cpu(misaligned_access_speed, cpu) !=3D + RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED) + return false; + + return true; +} + #ifdef CONFIG_RISCV_SCALAR_MISALIGNED =20 static bool unaligned_ctl __read_mostly; @@ -685,8 +697,6 @@ static int cpu_online_check_unaligned_access_emulated(u= nsigned int cpu) =20 bool __init check_unaligned_access_emulated_all_cpus(void) { - int cpu; - /* * We can only support PR_UNALIGN controls if all CPUs have misaligned * accesses emulated since tasks requesting such control can run on any @@ -694,10 +704,8 @@ bool __init check_unaligned_access_emulated_all_cpus(v= oid) */ on_each_cpu(check_unaligned_access_emulated, NULL, 1); =20 - for_each_online_cpu(cpu) - if (per_cpu(misaligned_access_speed, cpu) - !=3D RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED) - return false; + if (!all_cpus_unaligned_scalar_access_emulated()) + return false; =20 unaligned_ctl =3D true; return true; --=20 2.49.0