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A shortcoming of the GIC architecture is that there's an absolute limit on the number of vPEs that can be tracked by the ITS. It is possible that an operator is running a mix of VMs on a system, only wanting to provide a specific class of VMs with hardware interrupt injection support. To support this, introduce a GIC attribute, KVM_DEV_ARM_VGIC_CONFIG_GICV4, for the userspace to enable or disable vGICv4 for a given VM. Make the interface backward compatible by leaving vGICv4 enabled by default. Suggested-by: Oliver Upton Signed-off-by: Raghavendra Rao Ananta --- arch/arm64/include/uapi/asm/kvm.h | 7 +++++ arch/arm64/kvm/vgic/vgic-init.c | 3 +++ arch/arm64/kvm/vgic/vgic-its.c | 2 +- arch/arm64/kvm/vgic/vgic-kvm-device.c | 39 +++++++++++++++++++++++++++ arch/arm64/kvm/vgic/vgic-mmio-v3.c | 12 ++++----- arch/arm64/kvm/vgic/vgic-v3.c | 16 +++++++++-- arch/arm64/kvm/vgic/vgic-v4.c | 8 +++--- include/kvm/arm_vgic.h | 5 ++++ 8 files changed, 79 insertions(+), 13 deletions(-) diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/as= m/kvm.h index af9d9acaf997..6762683f7e0f 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -428,6 +428,13 @@ enum { #define KVM_DEV_ARM_ITS_RESTORE_TABLES 2 #define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3 #define KVM_DEV_ARM_ITS_CTRL_RESET 4 +#define KVM_DEV_ARM_VGIC_CONFIG_GICV4 5 + +enum { + KVM_DEV_ARM_VGIC_CONFIG_GICV4_UNAVAILABLE =3D 0, + KVM_DEV_ARM_VGIC_CONFIG_GICV4_DISABLE, + KVM_DEV_ARM_VGIC_CONFIG_GICV4_ENABLE, +}; =20 /* Device Control API on vcpu fd */ #define KVM_ARM_VCPU_PMU_V3_CTRL 0 diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-ini= t.c index 1f33e71c2a73..cd345df2271f 100644 --- a/arch/arm64/kvm/vgic/vgic-init.c +++ b/arch/arm64/kvm/vgic/vgic-init.c @@ -132,6 +132,9 @@ int kvm_vgic_create(struct kvm *kvm, u32 type) =20 kvm->arch.vgic.in_kernel =3D true; kvm->arch.vgic.vgic_model =3D type; + kvm->arch.vgic.gicv4_config =3D kvm_vgic_global_state.has_gicv4 ? + KVM_DEV_ARM_VGIC_CONFIG_GICV4_ENABLE : + KVM_DEV_ARM_VGIC_CONFIG_GICV4_UNAVAILABLE; =20 kvm->arch.vgic.vgic_dist_base =3D VGIC_ADDR_UNDEF; =20 diff --git a/arch/arm64/kvm/vgic/vgic-its.c b/arch/arm64/kvm/vgic/vgic-its.c index fb96802799c6..bba635e4e851 100644 --- a/arch/arm64/kvm/vgic/vgic-its.c +++ b/arch/arm64/kvm/vgic/vgic-its.c @@ -2242,7 +2242,7 @@ static int vgic_its_save_itt(struct vgic_its *its, st= ruct its_device *device) * have direct access to that state without GICv4.1. * Let's simply fail the save operation... */ - if (ite->irq->hw && !kvm_vgic_global_state.has_gicv4_1) + if (ite->irq->hw && !kvm_vm_has_gicv4_1(its->dev->kvm)) return -EACCES; =20 ret =3D vgic_its_save_ite(its, device, ite, gpa); diff --git a/arch/arm64/kvm/vgic/vgic-kvm-device.c b/arch/arm64/kvm/vgic/vg= ic-kvm-device.c index 359094f68c23..f03b80fc816e 100644 --- a/arch/arm64/kvm/vgic/vgic-kvm-device.c +++ b/arch/arm64/kvm/vgic/vgic-kvm-device.c @@ -279,6 +279,33 @@ static int vgic_set_common_attr(struct kvm_device *dev, unlock_all_vcpus(dev->kvm); mutex_unlock(&dev->kvm->lock); return r; + case KVM_DEV_ARM_VGIC_CONFIG_GICV4: { + u8 __user *uaddr =3D (u8 __user *)(long)attr->addr; + u8 val; + + if (!kvm_vgic_global_state.has_gicv4) + return -ENXIO; + + if (get_user(val, uaddr)) + return -EFAULT; + + if (vgic_initialized(dev->kvm) && + val !=3D dev->kvm->arch.vgic.gicv4_config) + return -EBUSY; + + switch (val) { + case KVM_DEV_ARM_VGIC_CONFIG_GICV4_ENABLE: + case KVM_DEV_ARM_VGIC_CONFIG_GICV4_DISABLE: + mutex_lock(&dev->kvm->arch.config_lock); + dev->kvm->arch.vgic.gicv4_config =3D val; + mutex_unlock(&dev->kvm->arch.config_lock); + break; + default: + return -EINVAL; + } + + return 0; + } } break; } @@ -309,6 +336,16 @@ static int vgic_get_common_attr(struct kvm_device *dev, r =3D put_user(dev->kvm->arch.vgic.mi_intid, uaddr); break; } + case KVM_DEV_ARM_VGIC_GRP_CTRL: { + switch (attr->attr) { + case KVM_DEV_ARM_VGIC_CONFIG_GICV4: { + u8 __user *uaddr =3D (u8 __user *)(long)attr->addr; + + r =3D put_user(dev->kvm->arch.vgic.gicv4_config, uaddr); + break; + } + } + } } =20 return r; @@ -684,6 +721,8 @@ static int vgic_v3_has_attr(struct kvm_device *dev, return 0; case KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES: return 0; + case KVM_DEV_ARM_VGIC_CONFIG_GICV4: + return 0; } } return -ENXIO; diff --git a/arch/arm64/kvm/vgic/vgic-mmio-v3.c b/arch/arm64/kvm/vgic/vgic-= mmio-v3.c index ae4c0593d114..66b365f59c51 100644 --- a/arch/arm64/kvm/vgic/vgic-mmio-v3.c +++ b/arch/arm64/kvm/vgic/vgic-mmio-v3.c @@ -50,8 +50,8 @@ bool vgic_has_its(struct kvm *kvm) =20 bool vgic_supports_direct_msis(struct kvm *kvm) { - return (kvm_vgic_global_state.has_gicv4_1 || - (kvm_vgic_global_state.has_gicv4 && vgic_has_its(kvm))); + return kvm_vm_has_gicv4(kvm) && + (kvm_vgic_global_state.has_gicv4_1 || vgic_has_its(kvm)); } =20 /* @@ -86,7 +86,7 @@ static unsigned long vgic_mmio_read_v3_misc(struct kvm_vc= pu *vcpu, } break; case GICD_TYPER2: - if (kvm_vgic_global_state.has_gicv4_1 && gic_cpuif_has_vsgi()) + if (kvm_vm_has_gicv4_1(vcpu->kvm) && gic_cpuif_has_vsgi()) value =3D GICD_TYPER2_nASSGIcap; break; case GICD_IIDR: @@ -119,7 +119,7 @@ static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vc= pu, dist->enabled =3D val & GICD_CTLR_ENABLE_SS_G1; =20 /* Not a GICv4.1? No HW SGIs */ - if (!kvm_vgic_global_state.has_gicv4_1 || !gic_cpuif_has_vsgi()) + if (!kvm_vm_has_gicv4_1(vcpu->kvm) || !gic_cpuif_has_vsgi()) val &=3D ~GICD_CTLR_nASSGIreq; =20 /* Dist stays enabled? nASSGIreq is RO */ @@ -133,7 +133,7 @@ static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vc= pu, if (is_hwsgi !=3D dist->nassgireq) vgic_v4_configure_vsgis(vcpu->kvm); =20 - if (kvm_vgic_global_state.has_gicv4_1 && + if (kvm_vm_has_gicv4_1(vcpu->kvm) && was_enabled !=3D dist->enabled) kvm_make_all_cpus_request(vcpu->kvm, KVM_REQ_RELOAD_GICv4); else if (!was_enabled && dist->enabled) @@ -178,7 +178,7 @@ static int vgic_mmio_uaccess_write_v3_misc(struct kvm_v= cpu *vcpu, } case GICD_CTLR: /* Not a GICv4.1? No HW SGIs */ - if (!kvm_vgic_global_state.has_gicv4_1) + if (!kvm_vm_has_gicv4_1(vcpu->kvm)) val &=3D ~GICD_CTLR_nASSGIreq; =20 dist->enabled =3D val & GICD_CTLR_ENABLE_SS_G1; diff --git a/arch/arm64/kvm/vgic/vgic-v3.c b/arch/arm64/kvm/vgic/vgic-v3.c index b9ad7c42c5b0..bc8cb9184be9 100644 --- a/arch/arm64/kvm/vgic/vgic-v3.c +++ b/arch/arm64/kvm/vgic/vgic-v3.c @@ -20,6 +20,18 @@ static bool common_trap; static bool dir_trap; static bool gicv4_enable; =20 +int kvm_vm_has_gicv4(struct kvm *kvm) +{ + return kvm->arch.vgic.gicv4_config =3D=3D + KVM_DEV_ARM_VGIC_CONFIG_GICV4_ENABLE; +} + +int kvm_vm_has_gicv4_1(struct kvm *kvm) +{ + return (kvm_vm_has_gicv4(kvm) && + kvm_vgic_global_state.has_gicv4_1); +} + void vgic_v3_set_underflow(struct kvm_vcpu *vcpu) { struct vgic_v3_cpu_if *cpuif =3D &vcpu->arch.vgic_cpu.vgic_v3; @@ -404,7 +416,7 @@ int vgic_v3_save_pending_tables(struct kvm *kvm) * The above vgic initialized check also ensures that the allocation * and enabling of the doorbells have already been done. */ - if (kvm_vgic_global_state.has_gicv4_1) { + if (kvm_vm_has_gicv4_1(kvm)) { unmap_all_vpes(kvm); vlpi_avail =3D true; } @@ -581,7 +593,7 @@ int vgic_v3_map_resources(struct kvm *kvm) return -EBUSY; } =20 - if (kvm_vgic_global_state.has_gicv4_1) + if (kvm_vm_has_gicv4_1(kvm)) vgic_v4_configure_vsgis(kvm); =20 return 0; diff --git a/arch/arm64/kvm/vgic/vgic-v4.c b/arch/arm64/kvm/vgic/vgic-v4.c index c7de6154627c..814d54f4ce13 100644 --- a/arch/arm64/kvm/vgic/vgic-v4.c +++ b/arch/arm64/kvm/vgic/vgic-v4.c @@ -86,7 +86,7 @@ static irqreturn_t vgic_v4_doorbell_handler(int irq, void= *info) struct kvm_vcpu *vcpu =3D info; =20 /* We got the message, no need to fire again */ - if (!kvm_vgic_global_state.has_gicv4_1 && + if (!kvm_vm_has_gicv4_1(vcpu->kvm) && !irqd_irq_disabled(&irq_to_desc(irq)->irq_data)) disable_irq_nosync(irq); =20 @@ -245,7 +245,7 @@ int vgic_v4_init(struct kvm *kvm) =20 lockdep_assert_held(&kvm->arch.config_lock); =20 - if (!kvm_vgic_global_state.has_gicv4) + if (!kvm_vm_has_gicv4(kvm)) return 0; /* Nothing to see here... move along. */ =20 if (dist->its_vm.vpes) @@ -286,7 +286,7 @@ int vgic_v4_init(struct kvm *kvm) * On GICv4.1, the doorbell is managed in HW and must * be left enabled. */ - if (kvm_vgic_global_state.has_gicv4_1) + if (kvm_vm_has_gicv4_1(kvm)) irq_flags &=3D ~IRQ_NOAUTOEN; irq_set_status_flags(irq, irq_flags); =20 @@ -392,7 +392,7 @@ int vgic_v4_load(struct kvm_vcpu *vcpu) * doorbell interrupt that would still be pending. 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Wed, 14 May 2025 12:22:07 -0700 (PDT) Date: Wed, 14 May 2025 19:21:58 +0000 In-Reply-To: <20250514192159.1751538-1-rananta@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250514192159.1751538-1-rananta@google.com> X-Mailer: git-send-email 2.49.0.1101.gccaa498523-goog Message-ID: <20250514192159.1751538-3-rananta@google.com> Subject: [PATCH 2/3] docs: kvm: devices/arm-vgic-v3: Document KVM_DEV_ARM_VGIC_CONFIG_GICV4 attr From: Raghavendra Rao Ananta To: Oliver Upton , Marc Zyngier Cc: Raghavendra Rao Anata , Mingwei Zhang , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the KVM_DEV_ARM_VGIC_CONFIG_GICV4 attr under KVM_DEV_ARM_VGIC_GRP_CTRL, that includes the values supported to set/get and the expected error returns. Signed-off-by: Raghavendra Rao Ananta --- .../virt/kvm/devices/arm-vgic-v3.rst | 24 +++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/Documentation/virt/kvm/devices/arm-vgic-v3.rst b/Documentation= /virt/kvm/devices/arm-vgic-v3.rst index e860498b1e35..2eed2ac13542 100644 --- a/Documentation/virt/kvm/devices/arm-vgic-v3.rst +++ b/Documentation/virt/kvm/devices/arm-vgic-v3.rst @@ -240,17 +240,33 @@ Groups: save all LPI pending bits into guest RAM pending tables. =20 The first kB of the pending table is not altered by this operation. + KVM_DEV_ARM_VGIC_CONFIG_GICV4 + attribute to enable/disable vGICv4 for a VM. It supports three value= s: + KVM_DEV_ARM_VGIC_CONFIG_GICV4_UNAVAILABLE: Kernel is not booted with + 'kvm-arm.vgic_v4_enable=3D1' cmdline, and hence vGICv4 is unavailabl= e to + the VM. The value can only be read by the userspace, but cannot be s= et. + KVM_DEV_ARM_VGIC_CONFIG_GICV4_ENABLE: Kernel is booted with + 'kvm-arm.vgic_v4_enable=3D1' cmdline, and vGICv4 is available and en= abled + for the VM (default config). Userspace can get and set this value. + KVM_DEV_ARM_VGIC_CONFIG_GICV4_DISABLE: Kernel is booted with + 'kvm-arm.vgic_v4_enable=3D1' cmdline, and vGICv4 is available and di= sabled + for the VM. Userspace can get and set this value. + =20 Errors: =20 - =3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + =3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D -ENXIO VGIC not properly configured as required prior to calling - this attribute + this attribute or trying to enable/disable vGICv4 for the VM + on a vGICv3 configuration in the case of + KVM_DEV_ARM_VGIC_CONFIG_GICV4 + -EINVAL Invalid configuration supplied by userspace -ENODEV no online VCPU -ENOMEM memory shortage when allocating vgic internal data -EFAULT Invalid guest ram access - -EBUSY One or more VCPUS are running - =3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + -EBUSY One or more VCPUS are running or vGIC has already been initia= lized + in the case of KVM_DEV_ARM_VGIC_CONFIG_GICV4 + =3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D =20 =20 KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO --=20 2.49.0.1101.gccaa498523-goog From nobody Sat Feb 7 18:20:48 2026 Received: from mail-io1-f73.google.com (mail-io1-f73.google.com [209.85.166.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A13F9293756 for ; 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Wed, 14 May 2025 12:22:08 -0700 (PDT) Date: Wed, 14 May 2025 19:21:59 +0000 In-Reply-To: <20250514192159.1751538-1-rananta@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250514192159.1751538-1-rananta@google.com> X-Mailer: git-send-email 2.49.0.1101.gccaa498523-goog Message-ID: <20250514192159.1751538-4-rananta@google.com> Subject: [PATCH 3/3] KVM: selftests: Extend vgic_init to test GICv4 config attr From: Raghavendra Rao Ananta To: Oliver Upton , Marc Zyngier Cc: Raghavendra Rao Anata , Mingwei Zhang , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extend the arm64 vgic_init test to check KVM_DEV_ARM_VGIC_CONFIG_GICV4 attribute. This includes testing the interface with various configurations when KVM has vGICv4 enabled (kvm-arm.vgic_v4_enable=3D1 cmdline) and disabled. Signed-off-by: Raghavendra Rao Ananta --- tools/testing/selftests/kvm/arm64/vgic_init.c | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/tools/testing/selftests/kvm/arm64/vgic_init.c b/tools/testing/= selftests/kvm/arm64/vgic_init.c index b3b5fb0ff0a9..adcfaf461b2b 100644 --- a/tools/testing/selftests/kvm/arm64/vgic_init.c +++ b/tools/testing/selftests/kvm/arm64/vgic_init.c @@ -675,6 +675,63 @@ static void test_v3_its_region(void) vm_gic_destroy(&v); } =20 +static void test_v3_vgicv4_config(void) +{ + struct kvm_vcpu *vcpus[NR_VCPUS]; + uint8_t gicv4_config; + struct vm_gic v; + int ret; + + v =3D vm_gic_create_with_vcpus(KVM_DEV_TYPE_ARM_VGIC_V3, NR_VCPUS, vcpus); + if (__kvm_has_device_attr(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, + KVM_DEV_ARM_VGIC_CONFIG_GICV4)) + return; + + kvm_device_attr_get(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, + KVM_DEV_ARM_VGIC_CONFIG_GICV4, &gicv4_config); + + if (gicv4_config =3D=3D KVM_DEV_ARM_VGIC_CONFIG_GICV4_UNAVAILABLE) { + gicv4_config =3D KVM_DEV_ARM_VGIC_CONFIG_GICV4_DISABLE; + ret =3D __kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, + KVM_DEV_ARM_VGIC_CONFIG_GICV4, &gicv4_config); + TEST_ASSERT(ret && errno =3D=3D ENXIO, + "vGICv4 allowed to be disabled even though it's unavailable"); + + gicv4_config =3D KVM_DEV_ARM_VGIC_CONFIG_GICV4_ENABLE; + ret =3D __kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, + KVM_DEV_ARM_VGIC_CONFIG_GICV4, &gicv4_config); + TEST_ASSERT(ret && errno =3D=3D ENXIO, + "vGICv4 allowed to be enabled even though it's unavailable"); + } else { /* kvm-arm.vgic_v4_enable=3D1 */ + TEST_ASSERT(gicv4_config =3D=3D KVM_DEV_ARM_VGIC_CONFIG_GICV4_ENABLE, + "Expected vGICv4 to be enabled by default"); + + gicv4_config =3D KVM_DEV_ARM_VGIC_CONFIG_GICV4_DISABLE; + kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, + KVM_DEV_ARM_VGIC_CONFIG_GICV4, &gicv4_config); + + gicv4_config =3D KVM_DEV_ARM_VGIC_CONFIG_GICV4_ENABLE; + kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, + KVM_DEV_ARM_VGIC_CONFIG_GICV4, &gicv4_config); + + gicv4_config =3D KVM_DEV_ARM_VGIC_CONFIG_GICV4_ENABLE + 1; + ret =3D __kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, + KVM_DEV_ARM_VGIC_CONFIG_GICV4, &gicv4_config); + TEST_ASSERT(ret && errno =3D=3D EINVAL, + "vGICv4 allowed to be configured with unknown value"); + + kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, + KVM_DEV_ARM_VGIC_CTRL_INIT, NULL); + gicv4_config =3D KVM_DEV_ARM_VGIC_CONFIG_GICV4_DISABLE; + ret =3D __kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, + KVM_DEV_ARM_VGIC_CONFIG_GICV4, &gicv4_config); + TEST_ASSERT(ret && errno =3D=3D EBUSY, + "Changing vGICv4 config allowed after vGIC initialization"); + } + + vm_gic_destroy(&v); +} + /* * Returns 0 if it's possible to create GIC device of a given type (V2 or = V3). */ @@ -730,6 +787,7 @@ void run_tests(uint32_t gic_dev_type) test_v3_last_bit_single_rdist(); test_v3_redist_ipa_range_check_at_vcpu_run(); test_v3_its_region(); + test_v3_vgicv4_config(); } } =20 --=20 2.49.0.1101.gccaa498523-goog