From nobody Tue Dec 16 14:04:54 2025 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C9231E5213; Wed, 14 May 2025 15:08:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747235292; cv=none; b=ikiJgzUPGMZ8ilfLC7KvL8Mbwh0ZBYiYsY686DcZZknpfcfzSzMcfq8Dlsi2YW2517sydezMR2Ny1KDVi60sWYCfRovSyBwfm5LPtJZsjdDP4ufixJmMppwP00aUkiXPUpfzocJbNOqRWVZ3aUj6FWhMK7TaFWWfVHJctZRIFxo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747235292; c=relaxed/simple; bh=Z2k+Z3ej+xBBSlI+v5A/FT6JPN3k1dR1YS9RIx2vmrM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VRHg2bKjYTgxHegY7tbqRjDNLSB4orxBpu6cUI+PWhn8an3UdMaFeW9FjBoQy+tbMz5fIax39mnmtXSxtAF5WW/FD8RCy3b+MCii1pI/IfLYU2BdhfJ7BkwahewK+dcA7fi9CGCpNwNZY41It+0Xav0G/+HcuPJQMdkEYfRsheg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=cbreNX6i; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="cbreNX6i" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID; bh=Drf+NVrVuz8HdLieCwaETCrvT5VW/a6sghwm+qTJzWg=; b=cbreNX6iIiLWQZ+zDS8RTJYuS7 krv7lSwz5rhhB2FAUxleRZgwGQGBnn/K++9g4EF3fE/GK4EFGIZuHsnzUE/QGK0p0dOyUHF50O4KW BN7ZNIl8ny/iclMCRllL0Fn/6bSUG1cAa6MutXCAuovX1OB7TcXJ2t+EwP7IOd/22zq/2lRudboKj BX/0bMG3uoCiWCrKnVOl0sfkQJ5lU3mcyYjMzMki1tlU8EktyDCtPAm9B8JGxS0/93ayEP1dvpMdQ nXkRhKSYHFwTcZ/0G+zEr4GZnoAhTgtKCTLCkuRuwaOOH3Y3YaKURDzKPlnge95vnvv4yvR/hd8ml kTluc3Ig==; Received: from i53875a50.versanet.de ([83.135.90.80] helo=localhost.localdomain) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1uFDiA-0006vE-CB; Wed, 14 May 2025 17:07:58 +0200 From: Heiko Stuebner To: heiko@sntech.de Cc: quentin.schulz@cherry.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Heiko Stuebner Subject: [PATCH v4 6/6] arm64: dts: rockchip: add px30-pp1516 base dtsi and board variants Date: Wed, 14 May 2025 17:07:45 +0200 Message-ID: <20250514150745.2437804-7-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250514150745.2437804-1-heiko@sntech.de> References: <20250514150745.2437804-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heiko Stuebner PP1516 are Touchscreen devices built around the PX30 SoC and companion devices to PX30-Cobra, again with multiple display options. The devices feature an EMMC, OTG port and a 720x1280 display with a touchscreen and camera Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz --- arch/arm64/boot/dts/rockchip/Makefile | 2 + .../rockchip/px30-pp1516-ltk050h3146w-a2.dts | 39 ++ .../dts/rockchip/px30-pp1516-ltk050h3148w.dts | 39 ++ arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi | 602 ++++++++++++++++++ 4 files changed, 682 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3146w-a= 2.dts create mode 100644 arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3148w.d= ts create mode 100644 arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 8151e8bb1cd3..899113f88a29 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -8,6 +8,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-engicam-px30-core-cto= uch2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-engicam-px30-core-ctouch2-of10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-engicam-px30-core-edimm2.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-firefly-jd4-core-mb.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-pp1516-ltk050h3146w-a2.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-pp1516-ltk050h3148w.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-ringneck-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-ringneck-haikou-lvds-9904379.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-ringneck-haikou-video-demo.dtbo diff --git a/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3146w-a2.dts b= /arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3146w-a2.dts new file mode 100644 index 000000000000..b71929bcb33e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3146w-a2.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + */ + +/dts-v1/; +#include "px30-pp1516.dtsi" + +/ { + model =3D "Theobroma Systems PP-1516 with LTK050H3146W-A2 Display"; + compatible =3D "tsd,px30-pp1516-ltk050h3146w-a2", "tsd,px30-pp1516", "roc= kchip,px30"; +}; + +&dsi { + status =3D "okay"; + + panel@0 { + compatible =3D "leadtek,ltk050h3146w-a2"; + reg =3D <0>; + backlight =3D <&backlight>; + iovcc-supply =3D <&vcc_1v8>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&dsp_rst>; + reset-gpios =3D <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + vci-supply =3D <&vcc_2v8>; + + port { + mipi_in_panel: endpoint { + remote-endpoint =3D <&mipi_out_panel>; + }; + }; + }; +}; + +&dsi_out { + mipi_out_panel: endpoint { + remote-endpoint =3D <&mipi_in_panel>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3148w.dts b/ar= ch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3148w.dts new file mode 100644 index 000000000000..a9bd5936c701 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3148w.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + */ + +/dts-v1/; +#include "px30-pp1516.dtsi" + +/ { + model =3D "Theobroma Systems PP-1516 with LTK050H3148W Display"; + compatible =3D "tsd,px30-pp1516-ltk050h3148w", "tsd,px30-pp1516", "rockch= ip,px30"; +}; + +&dsi { + status =3D "okay"; + + panel@0 { + compatible =3D "leadtek,ltk050h3148w"; + reg =3D <0>; + backlight =3D <&backlight>; + iovcc-supply =3D <&vcc_1v8>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&dsp_rst>; + reset-gpios =3D <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + vci-supply =3D <&vcc_2v8>; + + port { + mipi_in_panel: endpoint { + remote-endpoint =3D <&mipi_out_panel>; + }; + }; + }; +}; + +&dsi_out { + mipi_out_panel: endpoint { + remote-endpoint =3D <&mipi_in_panel>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi b/arch/arm64/boo= t/dts/rockchip/px30-pp1516.dtsi new file mode 100644 index 000000000000..3f9a133d7373 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi @@ -0,0 +1,602 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + */ + +/dts-v1/; +#include +#include +#include +#include "px30.dtsi" + +/ { + aliases { + mmc0 =3D &emmc; + }; + + chosen { + stdout-path =3D "serial5:115200n8"; + }; + + backlight: backlight { + compatible =3D "pwm-backlight"; + power-supply =3D <&vcc5v0_sys>; + pwms =3D <&pwm0 0 25000 0>; + }; + + beeper { + compatible =3D "pwm-beeper"; + pwms =3D <&pwm1 0 1000 0>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible =3D "mmc-pwrseq-emmc"; + pinctrl-0 =3D <&emmc_reset>; + pinctrl-names =3D "default"; + reset-gpios =3D <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + }; + + gpio-leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&debug_led_pin>, <&heartbeat_led_pin>; + + /* + * LED2 on the PCB, left of the USB-C connector. + * Typically NOT populated. + */ + debug: led-0 { + label =3D "debug"; + gpios =3D <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "none"; + }; + + /* + * LED14 on the PCB, left of the PX30 SoC. + * Typically NOT populated. + */ + heartbeat: led-1 { + label =3D "heartbeat"; + gpios =3D <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + }; + }; + + vcc5v0_sys: regulator-vccsys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; + + vcc_cam_avdd: regulator-vcc-cam-avdd { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_cam_avdd"; + gpio =3D <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cam_avdd_en>; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + vin-supply =3D <&vcc_2v8>; + }; + + vcc_cam_dovdd: regulator-vcc-cam-dovdd { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_cam_dovdd"; + gpio =3D <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cam_dovdd_en>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&vcc_1v8>; + }; + + vcc_cam_dvdd: regulator-vcc-cam-dvdd { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_cam_dvdd"; + gpio =3D <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cam_dvdd_en>; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + vin-supply =3D <&vcc_3v3>; + }; + + vcc_lens_afvdd: regulator-vcc-lens-afvdd { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_lens_afvdd"; + gpio =3D <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cam_afvdd_en>; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + vin-supply =3D <&vcc_2v8>; + }; +}; + +&cpu0 { + cpu-supply =3D <&vdd_arm>; +}; + +&cpu1 { + cpu-supply =3D <&vdd_arm>; +}; + +&cpu2 { + cpu-supply =3D <&vdd_arm>; +}; + +&cpu3 { + cpu-supply =3D <&vdd_arm>; +}; + +&csi_dphy { + status =3D "okay"; +}; + +&display_subsystem { + status =3D "okay"; +}; + +&dsi_dphy { + status =3D "okay"; +}; + +&emmc { + bus-width =3D <8>; + cap-mmc-highspeed; + /* + * For hs200 support, U-Boot would have to set the RK809 DCDC4 + * rail to 1.8V from the default of 3.0V. It doesn't do that on + * devices out in the field, so disable hs200. + * mmc-hs200-1_8v; + */ + mmc-pwrseq =3D <&emmc_pwrseq>; + non-removable; + vmmc-supply =3D <&vcc_3v3>; + vqmmc-supply =3D <&vcc_emmc>; + status =3D "okay"; +}; + +&gpu { + mali-supply =3D <&vdd_log>; + status =3D "okay"; +}; + +/* I2C0 =3D PMIC, Touchscreen */ +&i2c0 { + status =3D "okay"; + + touchscreen@14 { + compatible =3D "goodix,gt911"; + reg =3D <0x14>; + AVDD28-supply =3D <&vcc_2v8>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + irq-gpios =3D <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&tch_int &tch_rst>; + reset-gpios =3D <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + VDDIO-supply =3D <&vcc_3v3>; + }; + + rk809: pmic@20 { + compatible =3D "rockchip,rk809"; + reg =3D <0x20>; + #clock-cells =3D <0>; + clock-output-names =3D "xin32k"; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_int>; + system-power-controller; + wakeup-source; + + vcc1-supply =3D <&vcc5v0_sys>; + vcc2-supply =3D <&vcc5v0_sys>; + vcc3-supply =3D <&vcc5v0_sys>; + vcc4-supply =3D <&vcc5v0_sys>; + vcc5-supply =3D <&vcc_3v3>; + vcc6-supply =3D <&vcc_3v3>; + vcc7-supply =3D <&vcc_3v3>; + vcc9-supply =3D <&vcc5v0_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name =3D "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <950000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name =3D "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <950000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name =3D "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0_1v8: vcc_emmc: DCDC_REG4 { + regulator-name =3D "vcc_3v0_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3000000>; + }; + }; + + vcc_3v3: DCDC_REG5 { + regulator-name =3D "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-name =3D "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcc_1v0: LDO_REG3 { + regulator-name =3D "vcc_1v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1000000>; + }; + }; + + vcc_2v8: LDO_REG4 { + regulator-name =3D "vcc_2v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <2800000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name =3D "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3000000>; + }; + }; + + vcc_sdio: LDO_REG6 { + regulator-name =3D "vcc_sdio"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcc_lcd: LDO_REG7 { + regulator-name =3D "vcc_lcd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1000000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <1000000>; + }; + }; + + vcc_1v8_lcd: LDO_REG8 { + regulator-name =3D "vcc_1v8_lcd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcca_1v8: LDO_REG9 { + regulator-name =3D "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + }; + }; +}; + +&i2c1 { + clock-frequency =3D <100000>; + status =3D "okay"; +}; + +/* I2C2 =3D Accelerometer + Camera */ +&i2c2 { + /* MEMSIC MXC4005 accelerometer is rated for I2C Fast Mode (<=3D400KHz) */ + /* OmniVision OV5675 camera is rated for I2C Fast Mode (<=3D400KHz) */ + clock-frequency =3D <400000>; + status =3D "okay"; + + focus: focus@c { + compatible =3D "dongwoon,dw9714"; + reg =3D <0xc>; + vcc-supply =3D <&vcc_lens_afvdd>; + }; + + accel@15 { + compatible =3D "memsic,mxc4005"; + reg =3D <0x15>; + interrupt-parent =3D <&gpio2>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&accel_int>; + }; + + camera@36 { + compatible =3D "ovti,ov5675"; + reg =3D <0x36>; + clocks =3D <&cru SCLK_CIF_OUT>; + assigned-clocks =3D <&cru SCLK_CIF_OUT>; + assigned-clock-rates =3D <19200000>; + avdd-supply =3D <&vcc_cam_avdd>; + dvdd-supply =3D <&vcc_cam_dvdd>; + dovdd-supply =3D <&vcc_cam_dovdd>; + lens-focus =3D <&focus>; + orientation =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cif_clkout_m0 &cam_pwdn>; + reset-gpios =3D <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>; + rotation =3D <0>; + + port { + ucam_out: endpoint { + remote-endpoint =3D <&mipi_in_ucam>; + data-lanes =3D <1 2>; + link-frequencies =3D /bits/ 64 <450000000>; + }; + }; + }; +}; + +&io_domains { + vccio1-supply =3D <&vcc_sdio>; + vccio2-supply =3D <&vccio_sd>; + vccio3-supply =3D <&vcc_1v8>; + vccio4-supply =3D <&vcc_3v3>; + vccio5-supply =3D <&vcc_3v3>; + vccio6-supply =3D <&vcc_emmc>; + status =3D "okay"; +}; + +&isp { + status =3D "okay"; + + ports { + port@0 { + mipi_in_ucam: endpoint@0 { + reg =3D <0>; + data-lanes =3D <1 2>; + remote-endpoint =3D <&ucam_out>; + }; + }; + }; +}; + +&isp_mmu { + status =3D "okay"; +}; + +&pinctrl { + accel { + accel_int: accel-int { + rockchip,pins =3D + <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + camera { + cam_afvdd_en: cam-afvdd-en { + rockchip,pins =3D + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cam_avdd_en: cam-avdd-en { + rockchip,pins =3D + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cam_dovdd_en: cam-dovdd-en { + rockchip,pins =3D + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cam_dvdd_en: cam-dvdd-en { + rockchip,pins =3D + <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cam_pwdn: cam-pwdn { + rockchip,pins =3D + <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + emmc { + emmc_reset: emmc-reset { + rockchip,pins =3D + <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + debug_led_pin: debug-led-pin { + rockchip,pins =3D + <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + heartbeat_led_pin: heartbeat-led-pin { + rockchip,pins =3D + <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + panel { + dsp_rst: dsp-rst { + rockchip,pins =3D + <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + tch_int: tch-int { + rockchip,pins =3D + <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + tch_rst: tch-rst { + rockchip,pins =3D + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins =3D + <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply =3D <&vcc_3v3>; + pmuio2-supply =3D <&vcc_3v3>; + status =3D "okay"; +}; + +&pwm0 { + status =3D "okay"; +}; + +&pwm1 { + status =3D "okay"; +}; + +&saradc { + vref-supply =3D <&vcc_1v8>; + status =3D "okay"; +}; + +&tsadc { + status =3D "okay"; +}; + +&u2phy { + status =3D "okay"; +}; + +&u2phy_host { + status =3D "okay"; +}; + +&u2phy_otg { + status =3D "okay"; +}; + +&uart5 { + pinctrl-0 =3D <&uart5_xfer>; + status =3D "okay"; +}; + +&usb20_otg { + dr_mode =3D "peripheral"; + status =3D "okay"; +}; + +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; + +&vopb { + status =3D "okay"; +}; + +&vopb_mmu { + status =3D "okay"; +}; + +&wdt { + status =3D "okay"; +}; --=20 2.47.2