From nobody Tue Dec 16 14:06:30 2025 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62C101C84BD; Wed, 14 May 2025 15:08:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747235289; cv=none; b=relaGNjT+tU3u1cCTYr82zOXNhkxpypBD/ShkacaiHqteEC5UKMnPSHD1dSWFr4sTjQi091M8CA9a+yvhK0QKM2xHIiWB93HuCPjHHy8Fq7prygCV04iYSSiJ7lz4lXUayivr9aJr0dHUVCLkALDm+wpVGAqISis3dcDMjHRIr0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747235289; c=relaxed/simple; bh=m5vCvjfOgtsdOdZeYm5gSkKK2NkNNaRASLMycHBQAyo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Fu2XIy6y8UvpwxYWNkrM6EBaP20fzn8IzeEtR7NABHCMgEt0SZ9QZFviLI71eZHctqkgD0CX+c+ReEtKSF61HtKmXA9PD9ceu/Hy46T5Ndzc2ULMhnmfIBq4If95f4I0vzqRNObL/E4zkBXEGtHHStdj0SPlXgtcTJHbGKUuSEY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=00xdPBV5; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="00xdPBV5" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID; bh=bup6NhA6evSSr2vJWZ/rxyhkcFN8+wVdFF6iyZzNxv0=; b=00xdPBV5LYUhsKRl0GPLmUYjwN MlKlXssVXXHpKTVBWLO7vYS3B5E0puV5YwwmnYbPxrTzmePbxtPjsvUPxmIhUPmMrWLHhWY1dLBnd 65kynvoqfcnLVH3zda3mHp3NsF18gDQ7djvUJjPTCrC+qMYQkITkU6V6a+JGo+69RO5o9roByzLgZ Dx7/nwxLu61OuoNqRo6bLIEoYgUzowC4eCvt2ap5+/3Thsm10owOHuxz+R000k3TbDTWaTW44qzde ibQIxMYX05W+4z/UnXUdaDn6MkXnEr2DQ++1zcwaahwDH7yM/RwbRJRnH9bhqpf85t/TnVB8DrR74 39JLSKPw==; Received: from i53875a50.versanet.de ([83.135.90.80] helo=localhost.localdomain) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1uFDi8-0006vE-JA; Wed, 14 May 2025 17:07:56 +0200 From: Heiko Stuebner To: heiko@sntech.de Cc: quentin.schulz@cherry.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Heiko Stuebner Subject: [PATCH v4 2/6] arm64: dts: rockchip: move reset to dedicated eth-phy node on ringneck Date: Wed, 14 May 2025 17:07:41 +0200 Message-ID: <20250514150745.2437804-3-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250514150745.2437804-1-heiko@sntech.de> References: <20250514150745.2437804-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heiko Stuebner Using snps,reset-* properties to handle the ethernet-phy resets is deprecated and instead a real phy node should be used. Move the Ringneck phy-reset properties to such a node Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Tested-by: Quentin Schulz --- .../boot/dts/rockchip/px30-ringneck.dtsi | 22 ++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi b/arch/arm64/b= oot/dts/rockchip/px30-ringneck.dtsi index 142244d52706..ab232e5c7ad6 100644 --- a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi @@ -83,9 +83,7 @@ &emmc { =20 /* On-module TI DP83825I PHY but no connector, enable in carrierboard */ &gmac { - snps,reset-gpio =3D <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us =3D <0 50000 50000>; + phy-handle =3D <&dp83825>; phy-supply =3D <&vcc_3v3>; clock_in_out =3D "output"; }; @@ -344,6 +342,18 @@ &io_domains { status =3D "okay"; }; =20 +&mdio { + dp83825: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&phy_rst>; + reset-assert-us =3D <50000>; + reset-deassert-us =3D <50000>; + reset-gpios =3D <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + }; +}; + &pinctrl { emmc { emmc_reset: emmc-reset { @@ -351,6 +361,12 @@ emmc_reset: emmc-reset { }; }; =20 + ethernet { + phy_rst: phy-rst { + rockchip,pins =3D <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + leds { module_led_pin: module-led-pin { rockchip,pins =3D <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; --=20 2.47.2