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[73.76.29.249]) by smtp.googlemail.com with ESMTPSA id 586e51a60fabf-2dba060be9esm2654535fac.10.2025.05.14.03.58.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 May 2025 03:58:52 -0700 (PDT) From: Andrew Ballance To: dakr@kernel.org, a.hindborg@kernel.org, airlied@gmail.com, akpm@linux-foundation.org, alex.gaynor@gmail.com, aliceryhl@google.com, andrewjballance@gmail.com, andriy.shevchenko@linux.intel.com, arnd@arndb.de, benno.lossin@proton.me, bhelgaas@google.com, bjorn3_gh@protonmail.com, boqun.feng@gmail.com, daniel.almeida@collabora.com, fujita.tomonori@gmail.com, gary@garyguo.net, gregkh@linuxfoundation.org, kwilczynski@kernel.org, me@kloenk.dev, ojeda@kernel.org, raag.jadav@intel.com, rafael@kernel.org, simona@ffwll.ch, tmgross@umich.edu Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, nouveau@lists.freedesktop.org, rust-for-linux@vger.kernel.org Subject: [PATCH v2 6/6] rust: pci: make Bar generic over Io Date: Wed, 14 May 2025 05:57:34 -0500 Message-ID: <20250514105734.3898411-7-andrewjballance@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250514105734.3898411-1-andrewjballance@gmail.com> References: <20250514105734.3898411-1-andrewjballance@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" renames `Bar` to `RawBar` and makes it generic over `IoAccess`. a user can give a compile time suggestion when mapping a bar so that the type of io can be known. updates nova-core and rust_driver_pci to use new bar api. Suggested-by: Danilo Krummrich Signed-off-by: Andrew Ballance --- drivers/gpu/nova-core/driver.rs | 4 +- rust/kernel/pci.rs | 101 +++++++++++++++++++++++++------- samples/rust/rust_driver_pci.rs | 2 +- 3 files changed, 83 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/nova-core/driver.rs b/drivers/gpu/nova-core/driver= .rs index a08fb6599267..c03283d1e60e 100644 --- a/drivers/gpu/nova-core/driver.rs +++ b/drivers/gpu/nova-core/driver.rs @@ -11,7 +11,7 @@ pub(crate) struct NovaCore { } =20 const BAR0_SIZE: usize =3D 8; -pub(crate) type Bar0 =3D pci::Bar; +pub(crate) type Bar0 =3D pci::MMIoBar; =20 kernel::pci_device_table!( PCI_TABLE, @@ -33,7 +33,7 @@ fn probe(pdev: &pci::Device, _info: &Self::IdInfo) = -> Result(0, c_str!("nova-c= ore/bar0"))?; + let bar =3D pdev.iomap_region_sized_mmio::(0, c_str!("n= ova-core/bar0"))?; =20 let this =3D KBox::pin_init( try_pin_init!(Self { diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs index 9f5ca22d327a..42fbe597b06e 100644 --- a/rust/kernel/pci.rs +++ b/rust/kernel/pci.rs @@ -11,8 +11,7 @@ devres::Devres, driver, error::{to_result, Result}, - io::Io, - io::IoRaw, + io::{Io, IoAccess, IoRaw, MMIo}, str::CStr, types::{ARef, ForeignOwnable, Opaque}, ThisModule, @@ -259,15 +258,21 @@ pub struct Device( /// /// # Invariants /// -/// `Bar` always holds an `IoRaw` inststance that holds a valid pointer to= the start of the I/O +/// `Bar` always holds an `I` inststance that holds a valid pointer to the= start of the I/O /// memory mapped PCI bar and its size. -pub struct Bar { +pub struct RawBar =3D Io>= { pdev: ARef, - io: IoRaw, + io: I, num: i32, } =20 -impl Bar { +/// a pci bar that can be either PortIo or MMIo +pub type IoBar =3D RawBar>; + +/// a pci bar that maps a [`MMIo`]. +pub type MMIoBar =3D RawBar>; + +impl> RawBar { fn new(pdev: &Device, num: u32, name: &CStr) -> Result { let len =3D pdev.resource_len(num)?; if len =3D=3D 0 { @@ -299,7 +304,7 @@ fn new(pdev: &Device, num: u32, name: &CStr) -> Result<= Self> { return Err(ENOMEM); } =20 - let io =3D match IoRaw::new(ioptr, len as usize) { + let raw =3D match IoRaw::new(ioptr, len as usize) { Ok(io) =3D> io, Err(err) =3D> { // SAFETY: @@ -311,7 +316,22 @@ fn new(pdev: &Device, num: u32, name: &CStr) -> Result= { } }; =20 - Ok(Bar { + // SAFETY: + // - `raw` is from `pci_iomap` + // - addresses from `pci_iomap` should be accesed through ioread/i= owrite + let io =3D match unsafe { I::from_raw_cookie(raw) } { + Ok(io) =3D> io, + Err(err) =3D> { + // SAFETY: + // `pdev` is valid by the invariants of `Device`. + // `ioptr` is guaranteed to be the start of a valid I/O ma= pped memory region. + // `num` is checked for validity by a previous call to `De= vice::resource_len`. + unsafe { Self::do_release(pdev, ioptr, num) }; + return Err(err); + } + }; + + Ok(RawBar { pdev: pdev.into(), io, num, @@ -338,25 +358,24 @@ fn release(&self) { } } =20 -impl Bar { +impl RawBar { fn index_is_valid(index: u32) -> bool { // A `struct pci_dev` owns an array of resources with at most `PCI= _NUM_RESOURCES` entries. index < bindings::PCI_NUM_RESOURCES } } =20 -impl Drop for Bar { +impl> Drop for RawBar { fn drop(&mut self) { self.release(); } } =20 -impl Deref for Bar { - type Target =3D Io; +impl> Deref for RawBar { + type Target =3D I; =20 fn deref(&self) -> &Self::Target { - // SAFETY: By the type invariant of `Self`, the MMIO range in `sel= f.io` is properly mapped. - unsafe { Io::from_raw_ref(&self.io) } + &self.io } } =20 @@ -379,7 +398,7 @@ pub fn device_id(&self) -> u16 { =20 /// Returns the size of the given PCI bar resource. pub fn resource_len(&self, bar: u32) -> Result { - if !Bar::index_is_valid(bar) { + if !RawBar::index_is_valid(bar) { return Err(EINVAL); } =20 @@ -389,22 +408,62 @@ pub fn resource_len(&self, bar: u32) -> Result { Ok(unsafe { bindings::pci_resource_len(self.as_raw(), bar.try_into= ()?) }) } =20 - /// Mapps an entire PCI-BAR after performing a region-request on it. I= /O operation bound checks + /// Maps an entire PCI-BAR after performing a region-request on it. I/= O operation bound checks /// can be performed on compile time for offsets (plus the requested t= ype size) < SIZE. pub fn iomap_region_sized( &self, bar: u32, name: &CStr, - ) -> Result>> { - let bar =3D Bar::::new(self, bar, name)?; + ) -> Result>> { + self.iomap_region_sized_hint::>(bar, name) + } + + /// Maps an entire PCI-BAR after performing a region-request on it. + pub fn iomap_region(&self, bar: u32, name: &CStr) -> Result> { + self.iomap_region_sized::<0>(bar, name) + } + + /// Maps an entire PCI-BAR after performing a region-request on it. I/= O operation bound checks + /// can be performed on compile time for offsets (plus the requested t= ype size) < SIZE. + /// where it is known that the bar is [`MMIo`] + pub fn iomap_region_sized_mmio( + &self, + bar: u32, + name: &CStr, + ) -> Result>> { + self.iomap_region_sized_hint::>(bar, name) + } + + /// Maps an entire PCI-BAR after performing a region-request on it. + /// where it is known that the bar is [`MMIo`] + pub fn iomap_region_mmio(&self, bar: u32, name: &CStr) -> Result> { + self.iomap_region_sized_hint::<0, MMIo<0>>(bar, name) + } + + /// Maps an entire PCI-BAR after performing a region-request where the + /// type of Io backend is known at compile time. + pub fn iomap_region_hint( + &self, + bar: u32, + name: &CStr, + ) -> Result>> { + let bar =3D RawBar::<0, I>::new(self, bar, name)?; let devres =3D Devres::new(self.as_ref(), bar, GFP_KERNEL)?; =20 Ok(devres) } + /// Maps an entire PCI-BAR after performing a region-request where the + /// type of Io backend is known at compile time. I/O operation bound c= hecks + /// can be performed on compile time for offsets (plus the requested t= ype size) < SIZE. + pub fn iomap_region_sized_hint>( + &self, + bar: u32, + name: &CStr, + ) -> Result>> { + let bar =3D RawBar::::new(self, bar, name)?; + let devres =3D Devres::new(self.as_ref(), bar, GFP_KERNEL)?; =20 - /// Mapps an entire PCI-BAR after performing a region-request on it. - pub fn iomap_region(&self, bar: u32, name: &CStr) -> Result> { - self.iomap_region_sized::<0>(bar, name) + Ok(devres) } } =20 diff --git a/samples/rust/rust_driver_pci.rs b/samples/rust/rust_driver_pci= .rs index a8d292f4c1b3..b645155142db 100644 --- a/samples/rust/rust_driver_pci.rs +++ b/samples/rust/rust_driver_pci.rs @@ -18,7 +18,7 @@ impl Regs { const END: usize =3D 0x10; } =20 -type Bar0 =3D pci::Bar<{ Regs::END }>; +type Bar0 =3D pci::IoBar<{ Regs::END }>; =20 #[derive(Debug)] struct TestIndex(u8); --=20 2.49.0