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Wed, 14 May 2025 09:52:39 +0000 (GMT) X-AuditID: b6c32a29-55afd7000000223e-67-682467e773de Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 7E.8B.08766.7E764286; Wed, 14 May 2025 18:52:39 +0900 (KST) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250514095236epsmtip2db692ab276e71302b8d52d182d5c59f7~-XAT3BQRN1817318173epsmtip2L; Wed, 14 May 2025 09:52:36 +0000 (GMT) From: Raghav Sharma To: krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, conor+dt@kernel.org, richardcochran@gmail.com, sunyeal.hong@samsung.com, shin.son@samsung.com Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, dev.tailor@samsung.com, chandan.vn@samsung.com, karthik.sun@samsung.com, Raghav Sharma Subject: [PATCH v2 2/3] clk: samsung: exynosautov920: add block hsi2 clock support Date: Wed, 14 May 2025 15:32:13 +0530 Message-Id: <20250514100214.2479552-3-raghav.s@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250514100214.2479552-1-raghav.s@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupjkeLIzCtJLcpLzFFi42LZdlhJXvd5ukqGwbNPOhYP5m1js5jwJcJi zd5zTBbXvzxntbi3Yxm7xfwj51gtGme8YbI4f34Du8Wmx9dYLT723GO1uLxrDpvFjPP7mCwu nnK1OLZAzOL7yjuMFkfOvGC2+L9nB7vF4TftrBb/rm1ksZh8fC2rRdOy9UwOoh7vb7Sye+yc dZfdY9OqTjaPzUvqPfq2rGL0+LxJLoAtissmJTUnsyy1SN8ugSvj+qLzbAXzlSsmfm1haWA8 ItvFyMkhIWAi8XnBRxYQW0hgN6PEnXfZEHEJiX3/fzNC2MISK/89Z+9i5AKqecsosbH5HBtI gk1AS+LK9ndsIAkRgS4miXP/XoFNYhbYySSxcr0EiC0sECSxYsFpsAYWAVWJLbums4LYvALW EjvmfWSG2CAvsf/gWTCbU8BG4uuLy8wQF1lLtLyawwRRLyhxcuYTqPnyEs1bZzNPYBSYhSQ1 C0lqASPTKkbJ1ILi3PTcYsMCw7zUcr3ixNzi0rx0veT83E2M4CjT0tzBuH3VB71DjEwcjIcY JTiYlUR4r2cpZwjxpiRWVqUW5ccXleakFh9ilOZgURLnFX/RmyIkkJ5YkpqdmlqQWgSTZeLg lGpgChf03SDzNWxb7CXBTcc/aDWd7Rd5pZc3JyLgdURikKCUd6f5xWvNSbGXvu6xzfq1fENr XOb9r1mS1cczn3lPuHih0vj0oflLMiYr8te8O5/Aqc77/MYm500mU+7sTFsl+5Upd9uDOy8f Wara37s348KkPZ/7rshYKQXxKvo1PzhhLvja++BUIU5lf42nc+f47crpDfFX7suQnSO0f9rC b5+uzhLapbK3eO7tlrmf/zA3S7LprpL/UW577GShwd+TBZdj57SnfW/49P9w2MROPzWRg1ZH r7w+7XPz3dWLh89Iyxf2GB9K3T9N9KVxH3vp78aX1jtP+Nx+y2U8k/HJdK5w+bIEJWeDx5/Y Hz74/kOJpTgj0VCLuag4EQDcJh+1IQMAAA== X-CMS-MailID: 20250514095239epcas5p4a08eea7daa18a0fbda8873f64122a774 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-543,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250514095239epcas5p4a08eea7daa18a0fbda8873f64122a774 References: <20250514100214.2479552-1-raghav.s@samsung.com> Register compatible and cmu_info data to support clocks. CMU_HSI2, this provides clocks for HSI2 block Signed-off-by: Raghav Sharma --- drivers/clk/samsung/clk-exynosautov920.c | 72 ++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/drivers/clk/samsung/clk-exynosautov920.c b/drivers/clk/samsung= /clk-exynosautov920.c index da4afe8ac2ab..572b6ace14ac 100644 --- a/drivers/clk/samsung/clk-exynosautov920.c +++ b/drivers/clk/samsung/clk-exynosautov920.c @@ -26,6 +26,7 @@ #define CLKS_NR_MISC (CLK_DOUT_MISC_OSC_DIV2 + 1) #define CLKS_NR_HSI0 (CLK_DOUT_HSI0_PCIE_APB + 1) #define CLKS_NR_HSI1 (CLK_MOUT_HSI1_USBDRD + 1) +#define CLKS_NR_HSI2 (CLK_DOUT_HSI2_ETHERNET_PTP + 1) =20 /* ---- CMU_TOP ----------------------------------------------------------= -- */ =20 @@ -1752,6 +1753,74 @@ static const struct samsung_cmu_info hsi1_cmu_info _= _initconst =3D { .clk_name =3D "noc", }; =20 +/* ---- CMU_HSI2 ---------------------------------------------------------= */ + +/* Register Offset definitions for CMU_HSI2 (0x16b00000) */ +#define PLL_LOCKTIME_PLL_ETH 0x0 +#define PLL_CON3_PLL_ETH 0x10c +#define PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_USER 0x600 +#define PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USER 0x610 +#define PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x630 +#define CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET 0x1000 +#define CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET 0x1800 +#define CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP 0x1804 + +static const unsigned long hsi2_clk_regs[] __initconst =3D { + PLL_LOCKTIME_PLL_ETH, + PLL_CON3_PLL_ETH, + PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_USER, + PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USER, + PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER, + CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET, + CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET, + CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP, +}; + +static const struct samsung_pll_clock hsi2_pll_clks[] __initconst =3D { + /* CMU_HSI2_PLL */ + PLL(pll_531x, FOUT_PLL_ETH, "fout_pll_eth", "oscclk", + PLL_LOCKTIME_PLL_ETH, PLL_CON3_PLL_ETH, NULL), +}; + +/* List of parent clocks for Muxes in CMU_HSI2 */ +PNAME(mout_clkcmu_hsi2_noc_ufs_user_p) =3D { "oscclk", "dout_clkcmu_hsi2_n= oc_ufs" }; +PNAME(mout_clkcmu_hsi2_ufs_embd_user_p) =3D { "oscclk", "dout_clkcmu_hsi2_= ufs_embd" }; +PNAME(mout_hsi2_ethernet_p) =3D { "fout_pll_eth", "mout_clkcmu_hsi2_ethern= et_user" }; +PNAME(mout_clkcmu_hsi2_ethernet_user_p) =3D { "oscclk", "dout_clkcmu_hsi2_= ethernet" }; + +static const struct samsung_mux_clock hsi2_mux_clks[] __initconst =3D { + MUX(CLK_MOUT_HSI2_NOC_UFS_USER, "mout_clkcmu_hsi2_noc_ufs_user", + mout_clkcmu_hsi2_noc_ufs_user_p, PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USE= R, 4, 1), + MUX(CLK_MOUT_HSI2_UFS_EMBD_USER, "mout_clkcmu_hsi2_ufs_embd_user", + mout_clkcmu_hsi2_ufs_embd_user_p, PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_U= SER, 4, 1), + MUX(CLK_MOUT_HSI2_ETHERNET, "mout_hsi2_ethernet", + mout_hsi2_ethernet_p, CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET, 0, 1), + MUX(CLK_MOUT_HSI2_ETHERNET_USER, "mout_clkcmu_hsi2_ethernet_user", + mout_clkcmu_hsi2_ethernet_user_p, PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_U= SER, 4, 1), +}; + +static const struct samsung_div_clock hsi2_div_clks[] __initconst =3D { + DIV(CLK_DOUT_HSI2_ETHERNET, "dout_hsi2_ethernet", + "mout_hsi2_ethernet", CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET, + 0, 4), + DIV(CLK_DOUT_HSI2_ETHERNET_PTP, "dout_hsi2_ethernet_ptp", + "mout_hsi2_ethernet", CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP, + 0, 4), +}; + +static const struct samsung_cmu_info hsi2_cmu_info __initconst =3D { + .pll_clks =3D hsi2_pll_clks, + .nr_pll_clks =3D ARRAY_SIZE(hsi2_pll_clks), + .mux_clks =3D hsi2_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(hsi2_mux_clks), + .div_clks =3D hsi2_div_clks, + .nr_div_clks =3D ARRAY_SIZE(hsi2_div_clks), + .nr_clk_ids =3D CLKS_NR_HSI2, + .clk_regs =3D hsi2_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(hsi2_clk_regs), + .clk_name =3D "noc", +}; + static int __init exynosautov920_cmu_probe(struct platform_device *pdev) { const struct samsung_cmu_info *info; @@ -1779,6 +1848,9 @@ static const struct of_device_id exynosautov920_cmu_o= f_match[] =3D { }, { .compatible =3D "samsung,exynosautov920-cmu-hsi1", .data =3D &hsi1_cmu_info, + }, { + .compatible =3D "samsung,exynosautov920-cmu-hsi2", + .data =3D &hsi2_cmu_info, }, { } }; --=20 2.34.1