From nobody Mon Feb 9 03:45:55 2026 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3E7A25F798 for ; Wed, 14 May 2025 09:54:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747216450; cv=none; b=jYgfeEn7sqQ0JTzMcjvYwem0FzzMx1lwp8JpqGY+0eds9Xed0oElzm24Ej4kXGPWGMEoo1PAb96X/8RHq4nfr7OTv8056Q0CY5+Vxrf3ZVzCoF+AZ6QvMCXg0u5KsTilZKCc7MC87/pE422peBUGswbYXTThnJwKjLLpQrrzIHw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747216450; c=relaxed/simple; bh=VbnAmLxBB+9ni3Y9B/gXoAlfLtNObeur1VJCWbvyhdM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=L9IZ7CEpXHfqXvQ3XCf+WU4iAyF/MNRiG0rUAo9FhIgXAoZkyN02SZi8I2AbzCrzt+z8YSQFnQSkWA7ltxRtgmkk+f457D/Rl3VTlYpp4Wy6cqwHP/SzsU03vNvDqC/l5hyRKm515l+C7w5cN8hgagbcAAb+ig0+r19o2qX/ZRQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 54E9rrw0092296 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 14 May 2025 17:53:53 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Wed, 14 May 2025 17:53:53 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , , , Ben Zong-You Xie Subject: [PATCH v4 1/9] riscv: add Andes SoC family Kconfig support Date: Wed, 14 May 2025 17:53:42 +0800 Message-ID: <20250514095350.3765716-2-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250514095350.3765716-1-ben717@andestech.com> References: <20250514095350.3765716-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 54E9rrw0092296 Content-Type: text/plain; charset="utf-8" The first SoC in the Andes series is QiLai. It includes a high-performance quad-core RISC-V AX45MP cluster and one NX27V vector processor. For further information, refer to [1]. [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qil= ai-chip/ Signed-off-by: Ben Zong-You Xie --- arch/riscv/Kconfig.errata | 2 +- arch/riscv/Kconfig.socs | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index e318119d570d..be76883704a6 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -12,7 +12,7 @@ config ERRATA_ANDES =20 config ERRATA_ANDES_CMO bool "Apply Andes cache management errata" - depends on ERRATA_ANDES && ARCH_R9A07G043 + depends on ERRATA_ANDES && (ARCH_R9A07G043 || ARCH_ANDES) select RISCV_DMA_NONCOHERENT default y help diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index a9c3d2f6debc..1bf5637f2601 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -1,5 +1,14 @@ menu "SoC selection" =20 +config ARCH_ANDES + bool "Andes SoCs" + depends on MMU && !XIP_KERNEL + select ERRATA_ANDES + select ERRATA_ANDES_CMO + select AX45MP_L2_CACHE + help + This enables support for Andes SoC platform hardware. + config ARCH_MICROCHIP_POLARFIRE def_bool ARCH_MICROCHIP =20 --=20 2.34.1