From nobody Mon Feb 9 13:57:30 2026 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC6AA265630 for ; Wed, 14 May 2025 09:54:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747216484; cv=none; b=PBGyq6USBql0alwkOa8463NAqNcy2QynPHeyiXK4ivEgd5rDZjEj5Qz7WeURzEnQ+VCRRHZzfrn9TohGcrsS38LM6NeQ00Fgo0TFPKw+dMDehb7zXs2IOjhEFzUABWkQOU30CsR6lru3j8gBYNJPlxdAH4nTCPMUStVUZL3HvI8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747216484; c=relaxed/simple; bh=MUNzFZca4jP1Wzj7p7OSBhZbTeKUQVOelMr5pj0uSLM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WCrsKGgQ0MPPEKVd97Lz2154x1rS/ZSSKaharHQRHvQnvZTRLl1cJQThkF6w2k7+mOM1ifykWYS0AJGG1jqAL5e/XRaz1onq6H59kw9L4yUZjT+VyCXU9txO3Q55JAQTxS5DqHkWR7kAgtBx5eaP0MoRpS5ToB5ALK21HoTGa54= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 54E9s5qg092534 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 14 May 2025 17:54:05 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Wed, 14 May 2025 17:54:05 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , , , Ben Zong-You Xie , Conor Dooley Subject: [PATCH v4 9/9] riscv: defconfig: enable Andes SoC Date: Wed, 14 May 2025 17:53:50 +0800 Message-ID: <20250514095350.3765716-10-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250514095350.3765716-1-ben717@andestech.com> References: <20250514095350.3765716-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 54E9s5qg092534 Content-Type: text/plain; charset="utf-8" Enable Andes SoC config in defconfig to allow the default upstream kernel to boot on Voyager board. Acked-by: Conor Dooley Signed-off-by: Ben Zong-You Xie --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index eea825ee58e1..29a97cbf4ee6 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -25,6 +25,7 @@ CONFIG_BLK_DEV_INITRD=3Dy CONFIG_EXPERT=3Dy # CONFIG_SYSFS_SYSCALL is not set CONFIG_PROFILING=3Dy +CONFIG_ARCH_ANDES=3Dy CONFIG_ARCH_MICROCHIP=3Dy CONFIG_ARCH_SIFIVE=3Dy CONFIG_ARCH_SOPHGO=3Dy -- 2.34.1