From nobody Tue Feb 10 01:15:08 2026 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37CDD22618F; Wed, 14 May 2025 09:19:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747214399; cv=none; b=iJT74AQ3z2TjhjYd4/XSNR5fkc2hxaNO5W+uoBchMBSTeCckE2NP1rGi+t/+YTHIA/oqB7vo1di2aAL0k5KAS8252SkCR/Z8vDJ7aoYaAX1VeHeFxcUS7/dLg3lwMjpTU366dFoXpgUmUScFAivpeuhQVyu+cBnr5FFHBF17Am0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747214399; c=relaxed/simple; bh=J8zSjG1YWRpP2BiZ7FfzE1KFXnUG0V8xG6UkQqapBhg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=oFsuHnDcrmfQjlVjQAFcQy++z7sIDdFMuABeR8marxEbriqU42KFjfD04G68EZL7GWym0//CE+qpWO00l9OkOF2OuD404VU5eX9PwJkFMn3dlPYgAY6iUKm6rKSQd6YbLMAEFGkBbRn32h4Md7rmae0s8PouuG4eAVVf7hWouwA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=QVHv6zzF; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="QVHv6zzF" Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54E7vxYR030623; Wed, 14 May 2025 11:19:22 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= NrWZEBaWAkproY8CI+qS1Q6z3QO/fCAcsTOlY185XKo=; b=QVHv6zzF+gfdjGht bZbHLPuxAZfqtAAHQrdS0P2N3IAvm2QtddL33JaK8NLTWOnG4Sgsvf5pAgedFhSe K9M1OhDRMWdb2vmUA76wPNBzEaE/yXQ4ExBLkZYdTtBNCkkkBKx4NoSUGQ7qKKlB aoBGT/6m8Pg0J7/ITcDj9jupaFE2oofkwonZBNBU74jgx3tU5vjfSPMeuhTvOTDr rAvSJrsVsZakyFdJmvt16AFTMqwWm4ay1CE8+BQ6PO0yl3IVP5Vd+KOSoWlqnok9 GlDMz/Xe/Sayj4YIWqSqhVcNMZo+/uLVWZre9Csb2SeIRhI/J9XeENT4FcftAHVJ GODkrA== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 46mbdytukp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 14 May 2025 11:19:22 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 6448240055; Wed, 14 May 2025 11:17:48 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id AC259B4874A; Wed, 14 May 2025 11:16:36 +0200 (CEST) Received: from localhost (10.130.77.120) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 14 May 2025 11:16:36 +0200 From: Christian Bruel To: , , , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v9 3/9] dt-bindings: PCI: Add STM32MP25 PCIe Endpoint bindings Date: Wed, 14 May 2025 11:15:24 +0200 Message-ID: <20250514091530.3249364-4-christian.bruel@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250514091530.3249364-1-christian.bruel@foss.st.com> References: <20250514091530.3249364-1-christian.bruel@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-14_03,2025-05-14_02,2025-02-21_01 Content-Type: text/plain; charset="utf-8" STM32MP25 PCIe Controller is based on the DesignWare core configured as end point mode from the SYSCFG register. Signed-off-by: Christian Bruel Reviewed-by: Rob Herring (Arm) Acked-by: Manivannan Sadhasivam --- .../bindings/pci/st,stm32-pcie-ep.yaml | 67 +++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.= yaml diff --git a/Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml b/= Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml new file mode 100644 index 000000000000..fc1bbe19e616 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/st,stm32-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32MP25 PCIe Endpoint + +maintainers: + - Christian Bruel + +description: + PCIe endpoint controller based on the Synopsys DesignWare PCIe core. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# + - $ref: /schemas/pci/st,stm32-pcie-common.yaml# + +properties: + compatible: + const: st,stm32mp25-pcie-ep + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: PCIe configuration registers. + + reg-names: + items: + - const: dbi + - const: addr_space + + reset-gpios: + description: GPIO controlled connection to PERST# signal + maxItems: 1 + + phys: + maxItems: 1 + +required: + - phys + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + pcie-ep@48400000 { + compatible =3D "st,stm32mp25-pcie-ep"; + reg =3D <0x48400000 0x400000>, + <0x10000000 0x8000000>; + reg-names =3D "dbi", "addr_space"; + clocks =3D <&rcc CK_BUS_PCIE>; + phys =3D <&combophy PHY_TYPE_PCIE>; + resets =3D <&rcc PCIE_R>; + pinctrl-names =3D "default", "init"; + pinctrl-0 =3D <&pcie_pins_a>; + pinctrl-1 =3D <&pcie_init_pins_a>; + reset-gpios =3D <&gpioj 8 GPIO_ACTIVE_LOW>; + access-controllers =3D <&rifsc 68>; + power-domains =3D <&CLUSTER_PD>; + }; --=20 2.34.1