From nobody Tue Feb 10 02:43:34 2026 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 107BE22576A; Wed, 14 May 2025 09:21:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747214496; cv=none; b=Vgpq/zxMZYcCUH+7Yd8N8WoXx2MjH7Vghv1v6PsDESVYMB8hpx51FwC11joIQYuftHPJuItwGH4vcDtgnntCNHVlww0SBiWYKdh2czUegjREMsEvIqX3KLeLGWFKl/qPwVgHFCqaZUiDXR5qh5sVZXANMvq3RbBjxrf9AgkcyZ0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747214496; c=relaxed/simple; bh=i9LSW+S4PAZOlz8NvEMuLQl0XMu60kzZIjrm0p4e00A=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HrTje0d2Z6CSHWTKP2+F7eyaHOwtokGdJwWUxf68c9g6AQq4D3Je70OmL6poMb9cNamY4LWZnjxeJ9S2bo647UR+QsWKOv7eYQA4cwsWBrJfnfGS5P0IclCyGApKHeu77ehemT8kidnosSCV1J2d7c06BcrKSSMYcdrGaAYCHic= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=BlZjdebh; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="BlZjdebh" Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54E7w8pW023322; Wed, 14 May 2025 11:21:09 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= 99SNtvnMFqK7qNsbPspBqDAiBIpPQhzr7yAu4VDBnp8=; b=BlZjdebhX5jqrVHb VNH2gIrtZp6/CWej+WSDKFR8rDQ/+uw/hmRiSrnBfECN+47hpxo4YaaS5t/TnK7O 0dWSgI+8FYvFnupDGloJSq9XFifgbfTc1R3iId7GlPX08pjIs9Au7DOr0DVKrttF xsV0jYCm+GQ9sHA+2pabxuu7h4hMnNhtA8zjyEnwBF9bSilF8nX++g1lxbb1wx57 gyDf2C5wUy5T1CCaL4A3VV+0tuOtgRhCcAh+9btinErWgKzZtI6HFlYSM56AEf7B /GtE4k2R+qki+BrZZa74TluH+KWSxSXo3eigYMx/9jujnpDHOUQXM3l9LjLhg2Pn Rz99MA== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 46mbds2s3n-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 14 May 2025 11:21:09 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 7B8AE40047; Wed, 14 May 2025 11:19:37 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 0F5A0B48E9E; Wed, 14 May 2025 11:18:20 +0200 (CEST) Received: from localhost (10.130.77.120) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 14 May 2025 11:18:19 +0200 From: Christian Bruel To: , , , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v9 9/9] arm64: dts: st: Enable PCIe on the stm32mp257f-ev1 board Date: Wed, 14 May 2025 11:15:30 +0200 Message-ID: <20250514091530.3249364-10-christian.bruel@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250514091530.3249364-1-christian.bruel@foss.st.com> References: <20250514091530.3249364-1-christian.bruel@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-14_03,2025-05-14_02,2025-02-21_01 Content-Type: text/plain; charset="utf-8" Add PCIe RC and EP support on stm32mp257f-ev1 board. Default to RC mode. Signed-off-by: Christian Bruel --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/d= ts/st/stm32mp257f-ev1.dts index 9d1a1155e36c..85f99a1ca154 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -257,6 +257,27 @@ scmi_vdd_sdcard: regulator@23 { }; }; =20 +&pcie_ep { + pinctrl-names =3D "default", "init"; + pinctrl-0 =3D <&pcie_pins_a>; + pinctrl-1 =3D <&pcie_init_pins_a>; + reset-gpios =3D <&gpioj 8 GPIO_ACTIVE_LOW>; + status =3D "disabled"; +}; + +&pcie_rc { + pinctrl-names =3D "default", "init", "sleep"; + pinctrl-0 =3D <&pcie_pins_a>; + pinctrl-1 =3D <&pcie_init_pins_a>; + pinctrl-2 =3D <&pcie_sleep_pins_a>; + status =3D "okay"; + + pcie@0,0 { + reset-gpios =3D <&gpioj 8 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&gpioh 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; +}; + &sdmmc1 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc1_b4_pins_a>; --=20 2.34.1