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([82.78.167.58]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f57ddfbesm19286561f8f.10.2025.05.14.02.04.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 May 2025 02:04:32 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com Cc: claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH v2 6/8] clk: renesas: rzg2l-cpg: Drop MSTOP based power domain support Date: Wed, 14 May 2025 12:04:13 +0300 Message-ID: <20250514090415.4098534-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250514090415.4098534-1-claudiu.beznea.uj@bp.renesas.com> References: <20250514090415.4098534-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Since the configuration order between the individual MSTOP and CLKON bits cannot be preserved with the power domain abstraction, drop the power domain core code. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v2: - collected tags drivers/clk/renesas/rzg2l-cpg.c | 208 +++----------------------------- drivers/clk/renesas/rzg2l-cpg.h | 51 -------- 2 files changed, 17 insertions(+), 242 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cp= g.c index 844a89b37026..be42eeee1814 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -148,6 +148,7 @@ struct rzg2l_pll5_mux_dsi_div_param { * @num_resets: Number of Module Resets in info->resets[] * @last_dt_core_clk: ID of the last Core Clock exported to DT * @info: Pointer to platform data + * @genpd: PM domain * @mux_dsi_div_params: pll5 mux and dsi div parameters */ struct rzg2l_cpg_priv { @@ -164,6 +165,8 @@ struct rzg2l_cpg_priv { =20 const struct rzg2l_cpg_info *info; =20 + struct generic_pm_domain genpd; + struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params; }; =20 @@ -1769,39 +1772,14 @@ static int rzg2l_cpg_reset_controller_register(stru= ct rzg2l_cpg_priv *priv) return devm_reset_controller_register(priv->dev, &priv->rcdev); } =20 -/** - * struct rzg2l_cpg_pm_domains - RZ/G2L PM domains data structure - * @onecell_data: cell data - * @domains: generic PM domains - */ -struct rzg2l_cpg_pm_domains { - struct genpd_onecell_data onecell_data; - struct generic_pm_domain *domains[]; -}; - -/** - * struct rzg2l_cpg_pd - RZ/G2L power domain data structure - * @genpd: generic PM domain - * @priv: pointer to CPG private data structure - * @conf: CPG PM domain configuration info - * @id: RZ/G2L power domain ID - */ -struct rzg2l_cpg_pd { - struct generic_pm_domain genpd; - struct rzg2l_cpg_priv *priv; - struct rzg2l_cpg_pm_domain_conf conf; - u16 id; -}; - -static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_pd *pd, +static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_priv *priv, const struct of_phandle_args *clkspec) { - if (clkspec->np !=3D pd->genpd.dev.of_node || clkspec->args_count !=3D 2) + if (clkspec->np !=3D priv->genpd.dev.of_node || clkspec->args_count !=3D = 2) return false; =20 switch (clkspec->args[0]) { case CPG_MOD: { - struct rzg2l_cpg_priv *priv =3D pd->priv; const struct rzg2l_cpg_info *info =3D priv->info; unsigned int id =3D clkspec->args[1]; =20 @@ -1826,7 +1804,7 @@ static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_pd *= pd, =20 static int rzg2l_cpg_attach_dev(struct generic_pm_domain *domain, struct d= evice *dev) { - struct rzg2l_cpg_pd *pd =3D container_of(domain, struct rzg2l_cpg_pd, gen= pd); + struct rzg2l_cpg_priv *priv =3D container_of(domain, struct rzg2l_cpg_pri= v, genpd); struct device_node *np =3D dev->of_node; struct of_phandle_args clkspec; bool once =3D true; @@ -1835,7 +1813,7 @@ static int rzg2l_cpg_attach_dev(struct generic_pm_dom= ain *domain, struct device int error; =20 for (i =3D 0; !of_parse_phandle_with_args(np, "clocks", "#clock-cells", i= , &clkspec); i++) { - if (!rzg2l_cpg_is_pm_clk(pd, &clkspec)) { + if (!rzg2l_cpg_is_pm_clk(priv, &clkspec)) { of_node_put(clkspec.np); continue; } @@ -1880,183 +1858,31 @@ static void rzg2l_cpg_detach_dev(struct generic_pm= _domain *unused, struct device } =20 static void rzg2l_cpg_genpd_remove(void *data) -{ - struct genpd_onecell_data *celldata =3D data; - - for (unsigned int i =3D 0; i < celldata->num_domains; i++) - pm_genpd_remove(celldata->domains[i]); -} - -static void rzg2l_cpg_genpd_remove_simple(void *data) { pm_genpd_remove(data); } =20 -static int rzg2l_cpg_power_on(struct generic_pm_domain *domain) -{ - struct rzg2l_cpg_pd *pd =3D container_of(domain, struct rzg2l_cpg_pd, gen= pd); - struct rzg2l_cpg_reg_conf mstop =3D pd->conf.mstop; - struct rzg2l_cpg_priv *priv =3D pd->priv; - - /* Set MSTOP. */ - if (mstop.mask) - writel(mstop.mask << 16, priv->base + mstop.off); - - return 0; -} - -static int rzg2l_cpg_power_off(struct generic_pm_domain *domain) -{ - struct rzg2l_cpg_pd *pd =3D container_of(domain, struct rzg2l_cpg_pd, gen= pd); - struct rzg2l_cpg_reg_conf mstop =3D pd->conf.mstop; - struct rzg2l_cpg_priv *priv =3D pd->priv; - - /* Set MSTOP. */ - if (mstop.mask) - writel(mstop.mask | (mstop.mask << 16), priv->base + mstop.off); - - return 0; -} - -static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd) -{ - bool always_on =3D !!(pd->genpd.flags & GENPD_FLAG_ALWAYS_ON); - struct dev_power_governor *governor; - int ret; - - if (always_on) - governor =3D &pm_domain_always_on_gov; - else - governor =3D &simple_qos_governor; - - pd->genpd.flags |=3D GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP; - pd->genpd.attach_dev =3D rzg2l_cpg_attach_dev; - pd->genpd.detach_dev =3D rzg2l_cpg_detach_dev; - pd->genpd.power_on =3D rzg2l_cpg_power_on; - pd->genpd.power_off =3D rzg2l_cpg_power_off; - - ret =3D pm_genpd_init(&pd->genpd, governor, !always_on); - if (ret) - return ret; - - if (always_on) - ret =3D rzg2l_cpg_power_on(&pd->genpd); - - return ret; -} - static int __init rzg2l_cpg_add_clk_domain(struct rzg2l_cpg_priv *priv) { struct device *dev =3D priv->dev; struct device_node *np =3D dev->of_node; - struct rzg2l_cpg_pd *pd; - int ret; - - pd =3D devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); - if (!pd) - return -ENOMEM; - - pd->genpd.name =3D np->name; - pd->genpd.flags =3D GENPD_FLAG_ALWAYS_ON; - pd->priv =3D priv; - ret =3D rzg2l_cpg_pd_setup(pd); - if (ret) - return ret; - - ret =3D devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove_simple, &pd-= >genpd); - if (ret) - return ret; - - return of_genpd_add_provider_simple(np, &pd->genpd); -} - -static struct generic_pm_domain * -rzg2l_cpg_pm_domain_xlate(const struct of_phandle_args *spec, void *data) -{ - struct generic_pm_domain *domain =3D ERR_PTR(-ENOENT); - struct genpd_onecell_data *genpd =3D data; - - if (spec->args_count !=3D 1) - return ERR_PTR(-EINVAL); - - for (unsigned int i =3D 0; i < genpd->num_domains; i++) { - struct rzg2l_cpg_pd *pd =3D container_of(genpd->domains[i], struct rzg2l= _cpg_pd, - genpd); - - if (pd->id =3D=3D spec->args[0]) { - domain =3D &pd->genpd; - break; - } - } - - return domain; -} - -static int __init rzg2l_cpg_add_pm_domains(struct rzg2l_cpg_priv *priv) -{ - const struct rzg2l_cpg_info *info =3D priv->info; - struct device *dev =3D priv->dev; - struct device_node *np =3D dev->of_node; - struct rzg2l_cpg_pm_domains *domains; - struct generic_pm_domain *parent; - u32 ncells; + struct generic_pm_domain *genpd =3D &priv->genpd; int ret; =20 - ret =3D of_property_read_u32(np, "#power-domain-cells", &ncells); + genpd->name =3D np->name; + genpd->flags =3D GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON | + GENPD_FLAG_ACTIVE_WAKEUP; + genpd->attach_dev =3D rzg2l_cpg_attach_dev; + genpd->detach_dev =3D rzg2l_cpg_detach_dev; + ret =3D pm_genpd_init(genpd, &pm_domain_always_on_gov, false); if (ret) return ret; =20 - /* For backward compatibility. */ - if (!ncells) - return rzg2l_cpg_add_clk_domain(priv); - - domains =3D devm_kzalloc(dev, struct_size(domains, domains, info->num_pm_= domains), - GFP_KERNEL); - if (!domains) - return -ENOMEM; - - domains->onecell_data.domains =3D domains->domains; - domains->onecell_data.num_domains =3D info->num_pm_domains; - domains->onecell_data.xlate =3D rzg2l_cpg_pm_domain_xlate; - - ret =3D devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, &domains->o= necell_data); + ret =3D devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, genpd); if (ret) return ret; =20 - for (unsigned int i =3D 0; i < info->num_pm_domains; i++) { - struct rzg2l_cpg_pd *pd; - - pd =3D devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); - if (!pd) - return -ENOMEM; - - pd->genpd.name =3D info->pm_domains[i].name; - pd->genpd.flags =3D info->pm_domains[i].genpd_flags; - pd->conf =3D info->pm_domains[i].conf; - pd->id =3D info->pm_domains[i].id; - pd->priv =3D priv; - - ret =3D rzg2l_cpg_pd_setup(pd); - if (ret) - return ret; - - domains->domains[i] =3D &pd->genpd; - /* Parent should be on the very first entry of info->pm_domains[]. */ - if (!i) { - parent =3D &pd->genpd; - continue; - } - - ret =3D pm_genpd_add_subdomain(parent, &pd->genpd); - if (ret) - return ret; - } - - ret =3D of_genpd_add_provider_onecell(np, &domains->onecell_data); - if (ret) - return ret; - - return 0; + return of_genpd_add_provider_simple(np, genpd); } =20 static int __init rzg2l_cpg_probe(struct platform_device *pdev) @@ -2119,7 +1945,7 @@ static int __init rzg2l_cpg_probe(struct platform_dev= ice *pdev) if (error) return error; =20 - error =3D rzg2l_cpg_add_pm_domains(priv); + error =3D rzg2l_cpg_add_clk_domain(priv); if (error) return error; =20 diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cp= g.h index 50a5a23f2e6a..0a71c5ec24b6 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -257,51 +257,6 @@ struct rzg2l_reset { #define DEF_RST(_id, _off, _bit) \ DEF_RST_MON(_id, _off, _bit, -1) =20 -/** - * struct rzg2l_cpg_reg_conf - RZ/G2L register configuration data structure - * @off: register offset - * @mask: register mask - */ -struct rzg2l_cpg_reg_conf { - u16 off; - u16 mask; -}; - -#define DEF_REG_CONF(_off, _mask) ((struct rzg2l_cpg_reg_conf) { .off =3D = (_off), .mask =3D (_mask) }) - -/** - * struct rzg2l_cpg_pm_domain_conf - PM domain configuration data structure - * @mstop: MSTOP register configuration - */ -struct rzg2l_cpg_pm_domain_conf { - struct rzg2l_cpg_reg_conf mstop; -}; - -/** - * struct rzg2l_cpg_pm_domain_init_data - PM domain init data - * @name: PM domain name - * @conf: PM domain configuration - * @genpd_flags: genpd flags (see GENPD_FLAG_*) - * @id: PM domain ID (similar to the ones defined in - * include/dt-bindings/clock/-cpg.h) - */ -struct rzg2l_cpg_pm_domain_init_data { - const char * const name; - struct rzg2l_cpg_pm_domain_conf conf; - u32 genpd_flags; - u16 id; -}; - -#define DEF_PD(_name, _id, _mstop_conf, _flags) \ - { \ - .name =3D (_name), \ - .id =3D (_id), \ - .conf =3D { \ - .mstop =3D (_mstop_conf), \ - }, \ - .genpd_flags =3D (_flags), \ - } - /** * struct rzg2l_cpg_info - SoC-specific CPG Description * @@ -320,8 +275,6 @@ struct rzg2l_cpg_pm_domain_init_data { * @crit_mod_clks: Array with Module Clock IDs of critical clocks that * should not be disabled without a knowledgeable driver * @num_crit_mod_clks: Number of entries in crit_mod_clks[] - * @pm_domains: PM domains init data array - * @num_pm_domains: Number of PM domains * @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers */ struct rzg2l_cpg_info { @@ -348,10 +301,6 @@ struct rzg2l_cpg_info { const unsigned int *crit_mod_clks; unsigned int num_crit_mod_clks; =20 - /* Power domain. */ - const struct rzg2l_cpg_pm_domain_init_data *pm_domains; - unsigned int num_pm_domains; - bool has_clk_mon_regs; }; =20 --=20 2.43.0