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([82.78.167.58]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f57ddfbesm19286561f8f.10.2025.05.14.02.04.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 May 2025 02:04:26 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com Cc: claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH v2 3/8] clk: renesas: rzg2l-cpg: Add macro to loop through module clocks Date: Wed, 14 May 2025 12:04:10 +0300 Message-ID: <20250514090415.4098534-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250514090415.4098534-1-claudiu.beznea.uj@bp.renesas.com> References: <20250514090415.4098534-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add a macro to iterate over the module clocks array. This will be useful in the upcoming commits that move MSTOP support into the clock enable/disable APIs. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v2: - none; this patch is new drivers/clk/renesas/rzg2l-cpg.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cp= g.c index 767da288b0f7..c619b2da92b0 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1202,6 +1202,13 @@ struct mstp_clock { =20 #define to_mod_clock(_hw) container_of(_hw, struct mstp_clock, hw) =20 +#define for_each_mstp_clk(mstp_clk, hw, priv) \ + for (unsigned int i =3D 0; (priv) && i < (priv)->num_mod_clks; i++) \ + if ((priv)->clks[(priv)->num_core_clks + i] =3D=3D ERR_PTR(-ENOENT)) \ + continue; \ + else if (((hw) =3D __clk_get_hw((priv)->clks[(priv)->num_core_clks + i])= ) && \ + ((mstp_clk) =3D to_mod_clock(hw))) + static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) { struct mstp_clock *clock =3D to_mod_clock(hw); @@ -1314,17 +1321,10 @@ static struct mstp_clock *rzg2l_mod_clock_get_sibling(struct mstp_clock *clock, struct rzg2l_cpg_priv *priv) { + struct mstp_clock *clk; struct clk_hw *hw; - unsigned int i; - - for (i =3D 0; i < priv->num_mod_clks; i++) { - struct mstp_clock *clk; - - if (priv->clks[priv->num_core_clks + i] =3D=3D ERR_PTR(-ENOENT)) - continue; =20 - hw =3D __clk_get_hw(priv->clks[priv->num_core_clks + i]); - clk =3D to_mod_clock(hw); + for_each_mstp_clk(clk, hw, priv) { if (clock->off =3D=3D clk->off && clock->bit =3D=3D clk->bit) return clk; } --=20 2.43.0