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([82.78.167.58]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f57ddfbesm19286561f8f.10.2025.05.14.02.04.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 May 2025 02:04:24 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com Cc: claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH v2 2/8] clk: renesas: rzg2l-cpg: Move pointers after hw member Date: Wed, 14 May 2025 12:04:09 +0300 Message-ID: <20250514090415.4098534-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250514090415.4098534-1-claudiu.beznea.uj@bp.renesas.com> References: <20250514090415.4098534-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Reorder the pointer members in struct mstp_clock so they appear immediately after the hw member. This helps avoid potential padding and eliminates the need for any calculations in the to_mod_clock() macro. As struct clk_hw currently contains only pointers, placing it first also avoids padding. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v2: - moved pointers after hw member - updated the patch title and description to reflect the new approach - collected tags drivers/clk/renesas/rzg2l-cpg.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cp= g.c index c87ad5a972b7..767da288b0f7 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1185,19 +1185,19 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_c= lk *core, * struct mstp_clock - MSTP gating clock * * @hw: handle between common and hardware-specific interfaces + * @priv: CPG/MSTP private data + * @sibling: pointer to the other coupled clock * @off: register offset * @bit: ON/MON bit * @enabled: soft state of the clock, if it is coupled with another clock - * @priv: CPG/MSTP private data - * @sibling: pointer to the other coupled clock */ struct mstp_clock { struct clk_hw hw; + struct rzg2l_cpg_priv *priv; + struct mstp_clock *sibling; u16 off; u8 bit; bool enabled; - struct rzg2l_cpg_priv *priv; - struct mstp_clock *sibling; }; =20 #define to_mod_clock(_hw) container_of(_hw, struct mstp_clock, hw) --=20 2.43.0