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(unknown [10.28.34.254]) by maili.marvell.com (Postfix) with ESMTP id CDB075B6934; Tue, 13 May 2025 22:11:21 -0700 (PDT) From: Bharat Bhushan To: , , , , , , , , , CC: , Bharat Bhushan Subject: [PATCH 3/4 RESEND] crypto: octeontx2: Fix address alignment on CN10K A0/A1 and OcteonTX2 Date: Wed, 14 May 2025 10:40:42 +0530 Message-ID: <20250514051043.3178659-4-bbhushan2@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250514051043.3178659-1-bbhushan2@marvell.com> References: <20250514051043.3178659-1-bbhushan2@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: fyktusxU6I6pW2F6-ibaHTYh6ZtzvdJC X-Authority-Analysis: v=2.4 cv=fbyty1QF c=1 sm=1 tr=0 ts=682425fe cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=dt9VzEwgFbYA:10 a=M5GUcnROAAAA:8 a=x_2_y-6S6mRvB2HLd-wA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: fyktusxU6I6pW2F6-ibaHTYh6ZtzvdJC X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE0MDA0MyBTYWx0ZWRfX4ySys8jiiAza KRDsoGvsS+LIaqbw3HE71VBMF8A80fVpiwDO7p9EKCF5IcsVEqXn3Rjp/sSBGud+xnqEU4qkqZE gnMs4ak41gC0vmuScz/xlXnfcueXpe7/OJnXktThDfmc99u41WggsDxcDxzHT+6D36dpFGz1lcc bRyzr/xnQGlgNhu8o1rfnYxRvyS2SCopfzeAmo5WYfPOyJTFfDbRgrK3Hld2wixkU1GfcJIYKq5 CzVV0+8IE5JVnaRVVi9u6qY/Vuk5yWepsSa3g6dYS2CcL5jm3DaSQC6o7e6sFZ+5ZIFuxg1pKE7 oVb8zMkd09yDsuENNu1ZijWUXnJPDHzzvsqNiYjTVwuxcNRDo9vBGHH3y5iatZfdxUL7sIWCpXd riQvifoXXDgC8QxMhVD/hH6v5SmzfDCJkzK8/SVJFojsvFq7ugnEqNJ/IpDs0ySI527OfGoZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-14_01,2025-05-09_01,2025-02-21_01 Content-Type: text/plain; charset="utf-8" octeontx2 crypto driver allocates memory using kmalloc/kzalloc, and uses this memory for dma (does dma_map_single()). It assumes that kmalloc/kzalloc will return 128-byte aligned address. But kmalloc/kzalloc returns 8-byte aligned address after below changes: "9382bc44b5f5 arm64: allow kmalloc() caches aligned to the smaller cache_line_size() Memory allocated are used for following purpose: - Input data or scatter list address - 8-Byte alignment - Output data or gather list address - 8-Byte alignment - Completion address - 32-Byte alignment. This patch ensures all addresses are aligned as mentioned above. Signed-off-by: Bharat Bhushan --- .../marvell/octeontx2/otx2_cpt_reqmgr.h | 62 ++++++++++++++----- 1 file changed, 47 insertions(+), 15 deletions(-) diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h b/drivers/c= rypto/marvell/octeontx2/otx2_cpt_reqmgr.h index e27e849b01df..f0f1ff45c383 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h +++ b/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h @@ -34,6 +34,9 @@ #define SG_COMP_2 2 #define SG_COMP_1 1 =20 +#define OTX2_CPT_DPTR_RPTR_ALIGN 8 +#define OTX2_CPT_RES_ADDR_ALIGN 32 + union otx2_cpt_opcode { u16 flags; struct { @@ -417,10 +420,9 @@ static inline struct otx2_cpt_inst_info * otx2_sg_info_create(struct pci_dev *pdev, struct otx2_cpt_req_info *req, gfp_t gfp) { - int align =3D OTX2_CPT_DMA_MINALIGN; struct otx2_cpt_inst_info *info; - u32 dlen, align_dlen, info_len; - u16 g_sz_bytes, s_sz_bytes; + u32 dlen, info_len; + u16 g_len, s_len; u32 total_mem_len; =20 if (unlikely(req->in_cnt > OTX2_CPT_MAX_SG_IN_CNT || @@ -429,22 +431,50 @@ otx2_sg_info_create(struct pci_dev *pdev, struct otx2= _cpt_req_info *req, return NULL; } =20 - g_sz_bytes =3D ((req->in_cnt + 3) / 4) * - sizeof(struct otx2_cpt_sglist_component); - s_sz_bytes =3D ((req->out_cnt + 3) / 4) * - sizeof(struct otx2_cpt_sglist_component); + /* Allocate memory to meet below alignment requirement: + * ---------------------------------- + * | struct otx2_cpt_inst_info | + * | (No alignment required) | + * | -----------------------------| + * | | padding for 8B alignment | + * |----------------------------------| + * | SG List Gather/Input memory | + * | Length =3D multiple of 32Bytes | + * | Alignment =3D 8Byte | + * |----------------------------------| + * | SG List Scatter/Output memory | + * | Length =3D multiple of 32Bytes | + * | Alignment =3D 8Byte | + * | (padding for below alignment) | + * | -----------------------------| + * | | padding for 32B alignment | + * |----------------------------------| + * | Result response memory | + * ---------------------------------- + */ =20 - dlen =3D g_sz_bytes + s_sz_bytes + SG_LIST_HDR_SIZE; - align_dlen =3D ALIGN(dlen, align); - info_len =3D ALIGN(sizeof(*info), align); - total_mem_len =3D align_dlen + info_len + sizeof(union otx2_cpt_res_s); + info_len =3D sizeof(*info); + + g_len =3D ((req->in_cnt + 3) / 4) * + sizeof(struct otx2_cpt_sglist_component); + s_len =3D ((req->out_cnt + 3) / 4) * + sizeof(struct otx2_cpt_sglist_component); + + dlen =3D g_len + s_len + SG_LIST_HDR_SIZE; + + /* Allocate extra memory for SG and response address alignment */ + total_mem_len =3D ALIGN(info_len, OTX2_CPT_DPTR_RPTR_ALIGN) + dlen; + total_mem_len =3D ALIGN(total_mem_len, OTX2_CPT_RES_ADDR_ALIGN) + + sizeof(union otx2_cpt_res_s); =20 info =3D kzalloc(total_mem_len, gfp); if (unlikely(!info)) return NULL; =20 info->dlen =3D dlen; - info->in_buffer =3D (u8 *)info + info_len; + info->in_buffer =3D PTR_ALIGN((u8 *)info + info_len, + OTX2_CPT_DPTR_RPTR_ALIGN); + info->out_buffer =3D info->in_buffer + 8 + g_len; =20 ((u16 *)info->in_buffer)[0] =3D req->out_cnt; ((u16 *)info->in_buffer)[1] =3D req->in_cnt; @@ -460,7 +490,7 @@ otx2_sg_info_create(struct pci_dev *pdev, struct otx2_c= pt_req_info *req, } =20 if (setup_sgio_components(pdev, req->out, req->out_cnt, - &info->in_buffer[8 + g_sz_bytes])) { + info->out_buffer)) { dev_err(&pdev->dev, "Failed to setup scatter list\n"); goto destroy_info; } @@ -476,8 +506,10 @@ otx2_sg_info_create(struct pci_dev *pdev, struct otx2_= cpt_req_info *req, * Get buffer for union otx2_cpt_res_s response * structure and its physical address */ - info->completion_addr =3D info->in_buffer + align_dlen; - info->comp_baddr =3D info->dptr_baddr + align_dlen; + info->completion_addr =3D PTR_ALIGN((info->in_buffer + dlen), + OTX2_CPT_RES_ADDR_ALIGN); + info->comp_baddr =3D ALIGN((info->dptr_baddr + dlen), + OTX2_CPT_RES_ADDR_ALIGN); =20 return info; =20 --=20 2.34.1