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(unknown [10.28.34.254]) by maili.marvell.com (Postfix) with ESMTP id BD1105C68E3; Tue, 13 May 2025 22:11:12 -0700 (PDT) From: Bharat Bhushan To: , , , , , , , , , CC: , Bharat Bhushan Subject: [PATCH 1/4 RESEND] crypto: octeontx2: add timeout for load_fvc completion poll Date: Wed, 14 May 2025 10:40:40 +0530 Message-ID: <20250514051043.3178659-2-bbhushan2@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250514051043.3178659-1-bbhushan2@marvell.com> References: <20250514051043.3178659-1-bbhushan2@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: iKrlbvHaAo-xKbh8FPnpSBx4Ge7Vcu5k X-Authority-Analysis: v=2.4 cv=VITdn8PX c=1 sm=1 tr=0 ts=682425f5 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=dt9VzEwgFbYA:10 a=M5GUcnROAAAA:8 a=dP9LQboaRqI6G61vZ2MA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: iKrlbvHaAo-xKbh8FPnpSBx4Ge7Vcu5k X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE0MDA0MyBTYWx0ZWRfX+eRNgYH8MIwt qJlO9mDYNc/SOuSGFY5t4aTTNBXERCZKGMGfOb+ecjVeHp+GKImniH+WQsA8DsHJUR/QuHi5S7D KK/XDbjXOqJqetO7P4AWy1o9QAkEeCwrLY41VWnHeGK17CfEhJAexORP3PiYYwXSGq1u6P4wJa/ mw8dE7BWCVKUna3+NqXmla1JhqH+jEYg957cF13fEEWV2H3aWRBvJI+7KGnBuyM8yBdrnTufF31 8FwcRNHdO/E05YvS0oU4e2LMdP8RcUDqGv8Svq3G6ExRcLxUI9nzg5OvG357HmU4B3wtMA9y0KR 03OAj9RHGdtLcqxXrgivSo7yjc0ECcRlz3N5Yptk6FKeden1ub9lfuZiDEknecp0uUqZJyREzyS LJHIvDVuRDGKWYQhtsTIa/oJQv+ByUsux3ruZqNfYkj/2PWu8bEfA2zDtBN1LEHtSBfe3Ggc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-14_01,2025-05-09_01,2025-02-21_01 Content-Type: text/plain; charset="utf-8" Adds timeout to exit from possible infinite loop, which polls on CPT instruction(load_fvc) completion. Signed-off-by: Srujana Challa Signed-off-by: Bharat Bhushan --- .../crypto/marvell/octeontx2/otx2_cptpf_ucode.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c b/drivers/= crypto/marvell/octeontx2/otx2_cptpf_ucode.c index 42c5484ce66a..3a818ac89295 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c +++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c @@ -1494,6 +1494,7 @@ int otx2_cpt_discover_eng_capabilities(struct otx2_cp= tpf_dev *cptpf) dma_addr_t rptr_baddr; struct pci_dev *pdev; u32 len, compl_rlen; + int timeout =3D 10000; int ret, etype; void *rptr; =20 @@ -1556,16 +1557,27 @@ int otx2_cpt_discover_eng_capabilities(struct otx2_= cptpf_dev *cptpf) etype); otx2_cpt_fill_inst(&inst, &iq_cmd, rptr_baddr); lfs->ops->send_cmd(&inst, 1, &cptpf->lfs.lf[0]); + timeout =3D 10000; =20 while (lfs->ops->cpt_get_compcode(result) =3D=3D - OTX2_CPT_COMPLETION_CODE_INIT) + OTX2_CPT_COMPLETION_CODE_INIT) { cpu_relax(); + udelay(1); + timeout--; + if (!timeout) { + ret =3D -ENODEV; + cptpf->is_eng_caps_discovered =3D false; + dev_warn(&pdev->dev, "Timeout on CPT load_fvc completion poll\n"); + goto error_no_response; + } + } =20 cptpf->eng_caps[etype].u =3D be64_to_cpup(rptr); } - dma_unmap_single(&pdev->dev, rptr_baddr, len, DMA_BIDIRECTIONAL); cptpf->is_eng_caps_discovered =3D true; =20 +error_no_response: + dma_unmap_single(&pdev->dev, rptr_baddr, len, DMA_BIDIRECTIONAL); free_result: kfree(result); lf_cleanup: --=20 2.34.1 From nobody Sun Feb 8 13:39:40 2026 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 595F8101EE; Wed, 14 May 2025 05:11:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.148.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747199498; cv=none; b=GvV3sk5vaK3lA0elrgpZADmCcH6moFgS806L26IhBbP8X5DTaZgCqg3S1z73vxBnwsWq4SFl61tFXcKTKD5Oph6pEdRK4oBS2ga/Oh5QqibGN12TrtKerFvRgVDFkYjzwhEWSmNaEKbl3ZKtaudZtP/A/rkk9d5IeNjtExHuGGY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747199498; c=relaxed/simple; bh=nftJTquf7IRaq8HHdnbjeXO05NPydCSiIigaPKYx7mU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=OD9/U+9xkoYNd8mVIxcap6HLxijEFqVtS/wJbBfRwqVH3My0llha9zyxUEC36fazx+WSILnkRU5VnYnWJdCB+oDsu8q6I9QJ2+AeHE1g2km8IX0zOBTIyXpeKbnduD8xA2jPCNubqCO0Ym55ZpWjfri8cYm9gOG5WrMKC4m0cYM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=j9LbfbrB; arc=none smtp.client-ip=67.231.148.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="j9LbfbrB" Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 54DNSt3r028349; Tue, 13 May 2025 22:11:22 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=u Walq60J9nmTGN587g4K2toCWBPNF4Fg/bQygVQX8eM=; b=j9LbfbrBJXY6fUcSX 2g+57D9Z3DIgnjZf5gn1JtPlgcJx9AsXBKi8b24EuwKC/bPwc+qLH4kljkKh08jd MW5WxEQsuiceaCtsu/LnzCbT1PZQHYmN3BC7q2bDcVQs8bFPrGo1G4dzkVLwNT99 e72moPbyuGQz9iAuGnDoeaVKKzQ3x1WrjP9r5iBxvZimSlOZPEjQpDWA+s+J3YPX YbKWVAJYx3t+MnJAcYtpr6LjOVTb7V/kn4Si11whFsb7J6QoqgH39CIp3dNlBjuy 4Hje/DIkBmcFZsqqlYb8hL9c0aIpTAdLdH/ZLUjHPY6k31sEv9KA70AuGi+3NFaq aPwwA== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 46mfssrgtk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 13 May 2025 22:11:22 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 13 May 2025 22:11:21 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 13 May 2025 22:11:21 -0700 Received: from bharat-OptiPlex-Tower-Plus-7020.. (unknown [10.28.34.254]) by maili.marvell.com (Postfix) with ESMTP id 547F85B693B; Tue, 13 May 2025 22:11:17 -0700 (PDT) From: Bharat Bhushan To: , , , , , , , , , CC: , Bharat Bhushan Subject: [PATCH 2/4 RESEND] crypto: octeontx2: Fix address alignment issue on ucode loading Date: Wed, 14 May 2025 10:40:41 +0530 Message-ID: <20250514051043.3178659-3-bbhushan2@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250514051043.3178659-1-bbhushan2@marvell.com> References: <20250514051043.3178659-1-bbhushan2@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=OvpPyz/t c=1 sm=1 tr=0 ts=682425fa cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=dt9VzEwgFbYA:10 a=M5GUcnROAAAA:8 a=ub5NSpVJfYrinLkKqRIA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-ORIG-GUID: xZPNwD6JWLyKI20MPR_s5kz7M7YRzA9- X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE0MDA0MyBTYWx0ZWRfX3Ndg4D4v0Eae 25p35NHNCAODSFEk9c6lZuoJUuSsT5BrnPkRTjJQ4u0AvwJU7nKBcI/k4iMWC0dK+kh8xJGtgsD gQBNRq36XdV7z8HAPjwg+2ogJ3kRS8w2kGfVdAl/BfItFGC694tBGugjN1iu3grHFL1YnVk8Iom Z+EC8nIW7GSVLxL49YHvxTsBC0+JU2MjSC9LIfaKytgYqk05CrSS1wXNkSpRQVMHRkMoEhMVcs8 8MVPDf4ISYsa0dLfaGaU9H4fw2jxxm62V31/Devye55xhMsjkECLbBWJjZZKNJVUrChG7GAAtSw DywmgvCfPXUwZLzsm5E10BVhg82/qYJ9mVniEb0KuUFcaBEHw2TOTDGYK3EwWc1Ieih0NC0fq+W Kd0iit2ByxCQ2LtjLE5LQXKFjKrTNbN7guEq5DBk0KkLzP9UJ+kiFQXTr5CqiiwrMSA6eWn/ X-Proofpoint-GUID: xZPNwD6JWLyKI20MPR_s5kz7M7YRzA9- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-14_01,2025-05-09_01,2025-02-21_01 Content-Type: text/plain; charset="utf-8" octeontx2 crypto driver allocates memory using kmalloc/kzalloc, and uses this memory for dma (does dma_map_single()). It assumes that kmalloc/kzalloc will return 128-byte aligned address. But kmalloc/kzalloc returns 8-byte aligned address after below changes: "9382bc44b5f5 arm64: allow kmalloc() caches aligned to the smaller cache_line_size()" Completion address should be 32-Byte alignment when loading microcode. Signed-off-by: Bharat Bhushan --- .../marvell/octeontx2/otx2_cptpf_ucode.c | 30 +++++++++++-------- 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c b/drivers/= crypto/marvell/octeontx2/otx2_cptpf_ucode.c index 3a818ac89295..1c2aa9626088 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c +++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c @@ -1491,12 +1491,13 @@ int otx2_cpt_discover_eng_capabilities(struct otx2_= cptpf_dev *cptpf) union otx2_cpt_opcode opcode; union otx2_cpt_res_s *result; union otx2_cpt_inst_s inst; + dma_addr_t result_baddr; dma_addr_t rptr_baddr; struct pci_dev *pdev; - u32 len, compl_rlen; int timeout =3D 10000; int ret, etype; void *rptr; + u32 len; =20 /* * We don't get capabilities if it was already done @@ -1521,22 +1522,27 @@ int otx2_cpt_discover_eng_capabilities(struct otx2_= cptpf_dev *cptpf) if (ret) goto delete_grps; =20 - compl_rlen =3D ALIGN(sizeof(union otx2_cpt_res_s), OTX2_CPT_DMA_MINALIGN); - len =3D compl_rlen + LOADFVC_RLEN; + len =3D LOADFVC_RLEN + sizeof(union otx2_cpt_res_s) + + OTX2_CPT_RES_ADDR_ALIGN; =20 - result =3D kzalloc(len, GFP_KERNEL); - if (!result) { + rptr =3D kzalloc(len, GFP_KERNEL); + if (!rptr) { ret =3D -ENOMEM; goto lf_cleanup; } - rptr_baddr =3D dma_map_single(&pdev->dev, (void *)result, len, + + rptr_baddr =3D dma_map_single(&pdev->dev, rptr, len, DMA_BIDIRECTIONAL); if (dma_mapping_error(&pdev->dev, rptr_baddr)) { dev_err(&pdev->dev, "DMA mapping failed\n"); ret =3D -EFAULT; - goto free_result; + goto free_rptr; } - rptr =3D (u8 *)result + compl_rlen; + + result =3D (union otx2_cpt_res_s *)PTR_ALIGN(rptr + LOADFVC_RLEN, + OTX2_CPT_RES_ADDR_ALIGN); + result_baddr =3D ALIGN(rptr_baddr + LOADFVC_RLEN, + OTX2_CPT_RES_ADDR_ALIGN); =20 /* Fill in the command */ opcode.s.major =3D LOADFVC_MAJOR_OP; @@ -1548,14 +1554,14 @@ int otx2_cpt_discover_eng_capabilities(struct otx2_= cptpf_dev *cptpf) /* 64-bit swap for microcode data reads, not needed for addresses */ cpu_to_be64s(&iq_cmd.cmd.u); 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(unknown [10.28.34.254]) by maili.marvell.com (Postfix) with ESMTP id CDB075B6934; Tue, 13 May 2025 22:11:21 -0700 (PDT) From: Bharat Bhushan To: , , , , , , , , , CC: , Bharat Bhushan Subject: [PATCH 3/4 RESEND] crypto: octeontx2: Fix address alignment on CN10K A0/A1 and OcteonTX2 Date: Wed, 14 May 2025 10:40:42 +0530 Message-ID: <20250514051043.3178659-4-bbhushan2@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250514051043.3178659-1-bbhushan2@marvell.com> References: <20250514051043.3178659-1-bbhushan2@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: fyktusxU6I6pW2F6-ibaHTYh6ZtzvdJC X-Authority-Analysis: v=2.4 cv=fbyty1QF c=1 sm=1 tr=0 ts=682425fe cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=dt9VzEwgFbYA:10 a=M5GUcnROAAAA:8 a=x_2_y-6S6mRvB2HLd-wA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: fyktusxU6I6pW2F6-ibaHTYh6ZtzvdJC X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE0MDA0MyBTYWx0ZWRfX4ySys8jiiAza KRDsoGvsS+LIaqbw3HE71VBMF8A80fVpiwDO7p9EKCF5IcsVEqXn3Rjp/sSBGud+xnqEU4qkqZE gnMs4ak41gC0vmuScz/xlXnfcueXpe7/OJnXktThDfmc99u41WggsDxcDxzHT+6D36dpFGz1lcc bRyzr/xnQGlgNhu8o1rfnYxRvyS2SCopfzeAmo5WYfPOyJTFfDbRgrK3Hld2wixkU1GfcJIYKq5 CzVV0+8IE5JVnaRVVi9u6qY/Vuk5yWepsSa3g6dYS2CcL5jm3DaSQC6o7e6sFZ+5ZIFuxg1pKE7 oVb8zMkd09yDsuENNu1ZijWUXnJPDHzzvsqNiYjTVwuxcNRDo9vBGHH3y5iatZfdxUL7sIWCpXd riQvifoXXDgC8QxMhVD/hH6v5SmzfDCJkzK8/SVJFojsvFq7ugnEqNJ/IpDs0ySI527OfGoZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-14_01,2025-05-09_01,2025-02-21_01 Content-Type: text/plain; charset="utf-8" octeontx2 crypto driver allocates memory using kmalloc/kzalloc, and uses this memory for dma (does dma_map_single()). It assumes that kmalloc/kzalloc will return 128-byte aligned address. But kmalloc/kzalloc returns 8-byte aligned address after below changes: "9382bc44b5f5 arm64: allow kmalloc() caches aligned to the smaller cache_line_size() Memory allocated are used for following purpose: - Input data or scatter list address - 8-Byte alignment - Output data or gather list address - 8-Byte alignment - Completion address - 32-Byte alignment. This patch ensures all addresses are aligned as mentioned above. Signed-off-by: Bharat Bhushan --- .../marvell/octeontx2/otx2_cpt_reqmgr.h | 62 ++++++++++++++----- 1 file changed, 47 insertions(+), 15 deletions(-) diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h b/drivers/c= rypto/marvell/octeontx2/otx2_cpt_reqmgr.h index e27e849b01df..f0f1ff45c383 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h +++ b/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h @@ -34,6 +34,9 @@ #define SG_COMP_2 2 #define SG_COMP_1 1 =20 +#define OTX2_CPT_DPTR_RPTR_ALIGN 8 +#define OTX2_CPT_RES_ADDR_ALIGN 32 + union otx2_cpt_opcode { u16 flags; struct { @@ -417,10 +420,9 @@ static inline struct otx2_cpt_inst_info * otx2_sg_info_create(struct pci_dev *pdev, struct otx2_cpt_req_info *req, gfp_t gfp) { - int align =3D OTX2_CPT_DMA_MINALIGN; struct otx2_cpt_inst_info *info; - u32 dlen, align_dlen, info_len; - u16 g_sz_bytes, s_sz_bytes; + u32 dlen, info_len; + u16 g_len, s_len; u32 total_mem_len; =20 if (unlikely(req->in_cnt > OTX2_CPT_MAX_SG_IN_CNT || @@ -429,22 +431,50 @@ otx2_sg_info_create(struct pci_dev *pdev, struct otx2= _cpt_req_info *req, return NULL; } =20 - g_sz_bytes =3D ((req->in_cnt + 3) / 4) * - sizeof(struct otx2_cpt_sglist_component); - s_sz_bytes =3D ((req->out_cnt + 3) / 4) * - sizeof(struct otx2_cpt_sglist_component); + /* Allocate memory to meet below alignment requirement: + * ---------------------------------- + * | struct otx2_cpt_inst_info | + * | (No alignment required) | + * | -----------------------------| + * | | padding for 8B alignment | + * |----------------------------------| + * | SG List Gather/Input memory | + * | Length =3D multiple of 32Bytes | + * | Alignment =3D 8Byte | + * |----------------------------------| + * | SG List Scatter/Output memory | + * | Length =3D multiple of 32Bytes | + * | Alignment =3D 8Byte | + * | (padding for below alignment) | + * | -----------------------------| + * | | padding for 32B alignment | + * |----------------------------------| + * | Result response memory | + * ---------------------------------- + */ =20 - dlen =3D g_sz_bytes + s_sz_bytes + SG_LIST_HDR_SIZE; - align_dlen =3D ALIGN(dlen, align); - info_len =3D ALIGN(sizeof(*info), align); - total_mem_len =3D align_dlen + info_len + sizeof(union otx2_cpt_res_s); + info_len =3D sizeof(*info); + + g_len =3D ((req->in_cnt + 3) / 4) * + sizeof(struct otx2_cpt_sglist_component); + s_len =3D ((req->out_cnt + 3) / 4) * + sizeof(struct otx2_cpt_sglist_component); + + dlen =3D g_len + s_len + SG_LIST_HDR_SIZE; + + /* Allocate extra memory for SG and response address alignment */ + total_mem_len =3D ALIGN(info_len, OTX2_CPT_DPTR_RPTR_ALIGN) + dlen; + total_mem_len =3D ALIGN(total_mem_len, OTX2_CPT_RES_ADDR_ALIGN) + + sizeof(union otx2_cpt_res_s); =20 info =3D kzalloc(total_mem_len, gfp); if (unlikely(!info)) return NULL; =20 info->dlen =3D dlen; - info->in_buffer =3D (u8 *)info + info_len; + info->in_buffer =3D PTR_ALIGN((u8 *)info + info_len, + OTX2_CPT_DPTR_RPTR_ALIGN); + info->out_buffer =3D info->in_buffer + 8 + g_len; =20 ((u16 *)info->in_buffer)[0] =3D req->out_cnt; ((u16 *)info->in_buffer)[1] =3D req->in_cnt; @@ -460,7 +490,7 @@ otx2_sg_info_create(struct pci_dev *pdev, struct otx2_c= pt_req_info *req, } =20 if (setup_sgio_components(pdev, req->out, req->out_cnt, - &info->in_buffer[8 + g_sz_bytes])) { + info->out_buffer)) { dev_err(&pdev->dev, "Failed to setup scatter list\n"); goto destroy_info; } @@ -476,8 +506,10 @@ otx2_sg_info_create(struct pci_dev *pdev, struct otx2_= cpt_req_info *req, * Get buffer for union otx2_cpt_res_s response * structure and its physical address */ - info->completion_addr =3D info->in_buffer + align_dlen; - info->comp_baddr =3D info->dptr_baddr + align_dlen; + info->completion_addr =3D PTR_ALIGN((info->in_buffer + dlen), + OTX2_CPT_RES_ADDR_ALIGN); + info->comp_baddr =3D ALIGN((info->dptr_baddr + dlen), + OTX2_CPT_RES_ADDR_ALIGN); =20 return info; =20 --=20 2.34.1 From nobody Sun Feb 8 13:39:40 2026 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B9FB1F869E; Wed, 14 May 2025 05:11:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.156.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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(unknown [10.28.34.254]) by maili.marvell.com (Postfix) with ESMTP id 4F79A5B693A; Tue, 13 May 2025 22:11:26 -0700 (PDT) From: Bharat Bhushan To: , , , , , , , , , CC: , Bharat Bhushan Subject: [PATCH 4/4 RESEND] crypto: octeontx2: Fix address alignment on CN10KB and CN10KA-B0 Date: Wed, 14 May 2025 10:40:43 +0530 Message-ID: <20250514051043.3178659-5-bbhushan2@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250514051043.3178659-1-bbhushan2@marvell.com> References: <20250514051043.3178659-1-bbhushan2@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: 8XBC0Qi1HInnHcRMF01cq8uLWf0bHDAo X-Authority-Analysis: v=2.4 cv=fbyty1QF c=1 sm=1 tr=0 ts=68242603 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=dt9VzEwgFbYA:10 a=M5GUcnROAAAA:8 a=BhrP5AWxFkdJNdVQK0QA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: 8XBC0Qi1HInnHcRMF01cq8uLWf0bHDAo X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE0MDA0MyBTYWx0ZWRfX7zN8vu+hBjlS cRi1zHqncRLxpjls5wfL6bEvpEZbCaejTEwhxAT8IhdQoAjYZ8gdX0ew+RkDjVnYSWXpP7J44K5 Xxw4oorj3zDnRYwmhXlRQeBq3tJ6W22/y5cjwgLevK291LGM2C3qZ1cQxtaqvMrSqH/qqRIaSac r+w/6mbOru/46Pi+LXUyznQ+5d3L/7bO3Jwhx3YShGtPd84EHUYrqbS3lZE8o9MWtQZERHyqJUM mDPA+m7oRCiiWOFa/9fKl59TdgHGsKt+3r6zURjoM+Ep47XMfawug/ScfKq577mC/7CcPzY2Jbr 5CMUvtE7k5e4rOLvZQLRyeotmiADMVq3MyW4F/OOnvNO4gxdCBO1ZIzalLQ4ySSxspnPfMRWm9c k9+EIqeFwPw3jOAkwK6qRQ/o5STGa9W7M4eONWY0x2y2ngGjfK3Jd75c1JexD8mr//n43w4W X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-14_01,2025-05-09_01,2025-02-21_01 Content-Type: text/plain; charset="utf-8" octeontx2 crypto driver allocates memory using kmalloc/kzalloc, and uses this memory for dma (does dma_map_single()). It assumes that kmalloc/kzalloc will return 128-byte aligned address. But kmalloc/kzalloc returns 8-byte aligned address after below changes: "9382bc44b5f5 arm64: allow kmalloc() caches aligned to the smaller cache_line_size() Memory allocated are used for following purpose: - Input data or scatter list address - 8-Byte alignment - Output data or gather list address - 8-Byte alignment - Completion address - 32-Byte alignment. This patch ensures all addresses are aligned as mentioned above. Signed-off-by: Bharat Bhushan --- .../marvell/octeontx2/otx2_cpt_reqmgr.h | 57 ++++++++++++++----- 1 file changed, 42 insertions(+), 15 deletions(-) diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h b/drivers/c= rypto/marvell/octeontx2/otx2_cpt_reqmgr.h index f0f1ff45c383..b49dafc596c7 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h +++ b/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h @@ -350,22 +350,45 @@ static inline struct otx2_cpt_inst_info * cn10k_sgv2_info_create(struct pci_dev *pdev, struct otx2_cpt_req_info *req, gfp_t gfp) { - u32 dlen =3D 0, g_len, sg_len, info_len; - int align =3D OTX2_CPT_DMA_MINALIGN; + u32 dlen =3D 0, g_len, s_len, sg_len, info_len; struct otx2_cpt_inst_info *info; - u16 g_sz_bytes, s_sz_bytes; u32 total_mem_len; int i; =20 - g_sz_bytes =3D ((req->in_cnt + 2) / 3) * - sizeof(struct cn10kb_cpt_sglist_component); - s_sz_bytes =3D ((req->out_cnt + 2) / 3) * - sizeof(struct cn10kb_cpt_sglist_component); + /* Allocate memory to meet below alignment requirement: + * ---------------------------------- + * | struct otx2_cpt_inst_info | + * | (No alignment required) | + * | -----------------------------| + * | | padding for 8B alignment | + * |----------------------------------| + * | SG List Gather/Input memory | + * | Length =3D multiple of 32Bytes | + * | Alignment =3D 8Byte | + * |----------------------------------| + * | SG List Scatter/Output memory | + * | Length =3D multiple of 32Bytes | + * | Alignment =3D 8Byte | + * | (padding for below alignment) | + * | -----------------------------| + * | | padding for 32B alignment | + * |----------------------------------| + * | Result response memory | + * ---------------------------------- + */ + + info_len =3D sizeof(*info); =20 - g_len =3D ALIGN(g_sz_bytes, align); - sg_len =3D ALIGN(g_len + s_sz_bytes, align); - info_len =3D ALIGN(sizeof(*info), align); - total_mem_len =3D sg_len + info_len + sizeof(union otx2_cpt_res_s); + g_len =3D ((req->in_cnt + 2) / 3) * + sizeof(struct cn10kb_cpt_sglist_component); + s_len =3D ((req->out_cnt + 2) / 3) * + sizeof(struct cn10kb_cpt_sglist_component); + sg_len =3D g_len + s_len; + + /* Allocate extra memory for SG and response address alignment */ + total_mem_len =3D ALIGN(info_len, OTX2_CPT_DPTR_RPTR_ALIGN) + sg_len; + total_mem_len =3D ALIGN(total_mem_len, OTX2_CPT_RES_ADDR_ALIGN) + + sizeof(union otx2_cpt_res_s); =20 info =3D kzalloc(total_mem_len, gfp); if (unlikely(!info)) @@ -375,7 +398,9 @@ cn10k_sgv2_info_create(struct pci_dev *pdev, struct otx= 2_cpt_req_info *req, dlen +=3D req->in[i].size; =20 info->dlen =3D dlen; - info->in_buffer =3D (u8 *)info + info_len; + info->in_buffer =3D PTR_ALIGN((u8 *)info + info_len, + OTX2_CPT_DPTR_RPTR_ALIGN); + info->out_buffer =3D info->in_buffer + g_len; info->gthr_sz =3D req->in_cnt; info->sctr_sz =3D req->out_cnt; =20 @@ -387,7 +412,7 @@ cn10k_sgv2_info_create(struct pci_dev *pdev, struct otx= 2_cpt_req_info *req, } =20 if (sgv2io_components_setup(pdev, req->out, req->out_cnt, - &info->in_buffer[g_len])) { + info->out_buffer)) { dev_err(&pdev->dev, "Failed to setup scatter list\n"); goto destroy_info; } @@ -404,8 +429,10 @@ cn10k_sgv2_info_create(struct pci_dev *pdev, struct ot= x2_cpt_req_info *req, * Get buffer for union otx2_cpt_res_s response * structure and its physical address */ - info->completion_addr =3D info->in_buffer + sg_len; - info->comp_baddr =3D info->dptr_baddr + sg_len; + info->completion_addr =3D PTR_ALIGN((info->in_buffer + sg_len), + OTX2_CPT_RES_ADDR_ALIGN); + info->comp_baddr =3D ALIGN((info->dptr_baddr + sg_len), + OTX2_CPT_RES_ADDR_ALIGN); =20 return info; =20 --=20 2.34.1