From nobody Mon Feb 9 05:52:17 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1F911F5423; Wed, 14 May 2025 04:31:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747197076; cv=none; b=Omu7jZFElVPA6JdWgRxev2/yoAD8nkAMkDyY4Pa8Eb2lEIWbCX7zVgaRcWYMjxfSGQ7RgWvKpgFTM3DPrbmX2F9GFEW1lnei4yrslQggcpJDzTu2WeI4I8CsKMLmzKpQWC3E0tx/62FKp/lEYs79la+2jQT9e3QXfzkW6dXv210= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747197076; c=relaxed/simple; bh=k89ugzuHOnkB/aDBW+4LJjImUgTAiWJPrYGGiSD3Gng=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=gEc3fIKC/IrRiSGvuX+abl4TZ9qdL80XKm9uvfbkjeFUB4Tx/FnuenLo83HeaeRVa5dwAkMLmwzalEKWJXlNby2Bys75G3c9+iZor6TLRH+NZN7PZgtCtiu+GxrsyhV518r5Fpn67JulMYrmWv1RdijI9lQs88P8T2fEfovGV30= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=mNT9+I0L; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="mNT9+I0L" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1747197074; x=1778733074; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=k89ugzuHOnkB/aDBW+4LJjImUgTAiWJPrYGGiSD3Gng=; b=mNT9+I0L1OtfSw2di6X8L23mCBIIrw9ga0jukYpvY6xx83nyBm8Eq27X R4qe9PTuxTJ9JhU+gp8XQ9GmFq/4frZuY4AausZfvWYr16B64ZI149bS2 178iKPd0h/Jc9IXOpV3KV+OIZnnsiNhmfIZO0m8fyYEGfkaQpeULUBGf6 ZdVEbDhwnccnInXeifA3Xwgfyam4HUguJzIrceS2l8yP5fXK6fNRnDA6E fbj9egnTr1RDOS8oZFTSQ5A7x/DTQDhrCYH5PCWc//6mfy+uqhQtLk+kY BjL5md2HVPGTGb8TQzt7Ks29j5lRykY7GZwJ2o8RvG0CW5TFT1glODa0S w==; X-CSE-ConnectionGUID: TMG3lNiqQRSLlPKHTB4aRw== X-CSE-MsgGUID: dYVwMY44SC+5LS97ZvdPxg== X-IronPort-AV: E=McAfee;i="6700,10204,11432"; a="36699108" X-IronPort-AV: E=Sophos;i="6.15,287,1739865600"; d="scan'208";a="36699108" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2025 21:31:14 -0700 X-CSE-ConnectionGUID: YLqlEdyTTAa3BRgQ97xyIg== X-CSE-MsgGUID: GJbgOeR+S0m5REJNPEf0BA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,287,1739865600"; d="scan'208";a="142861820" Received: from mohdfai2-ilbpg12-1.png.intel.com ([10.88.227.73]) by orviesa004.jf.intel.com with ESMTP; 13 May 2025 21:31:11 -0700 From: Faizal Rahim To: Tony Nguyen , Przemek Kitszel , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vladimir Oltean Cc: intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Faizal Rahim , Aleksandr Loktionov , Chwee-Lin Choong Subject: [PATCH iwl-next v2 3/8] igc: refactor TXDCTL macros to use FIELD_PREP and GEN_MASK Date: Wed, 14 May 2025 00:29:40 -0400 Message-Id: <20250514042945.2685273-4-faizal.abdul.rahim@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250514042945.2685273-1-faizal.abdul.rahim@linux.intel.com> References: <20250514042945.2685273-1-faizal.abdul.rahim@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Refactor TXDCTL macro handling to use FIELD_PREP and GENMASK macros. This prepares the code for adding a new TXDCTL priority field in an upcoming patch. Verified that the macro values remain unchanged before and after refactoring. Signed-off-by: Faizal Rahim Reviewed-by: Simon Horman --- drivers/net/ethernet/intel/igc/igc.h | 15 ++++++++++----- drivers/net/ethernet/intel/igc/igc_main.c | 6 ++---- 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/intel/igc/igc.h b/drivers/net/ethernet/in= tel/igc/igc.h index db1e2db1619e..daab06fc3f80 100644 --- a/drivers/net/ethernet/intel/igc/igc.h +++ b/drivers/net/ethernet/intel/igc/igc.h @@ -493,13 +493,18 @@ static inline u32 igc_rss_type(const union igc_adv_rx= _desc *rx_desc) /* Receive Software Flush */ #define IGC_RXDCTL_SWFLUSH 0x04000000 =20 -#define IGC_TXDCTL_PTHRESH 8 -#define IGC_TXDCTL_HTHRESH 1 -#define IGC_TXDCTL_WTHRESH 16 +#define IGC_TXDCTL_PTHRESH_MASK GENMASK(4, 0) +#define IGC_TXDCTL_HTHRESH_MASK GENMASK(12, 8) +#define IGC_TXDCTL_WTHRESH_MASK GENMASK(20, 16) +#define IGC_TXDCTL_QUEUE_ENABLE_MASK GENMASK(25, 25) +#define IGC_TXDCTL_SWFLUSH_MASK GENMASK(26, 26) +#define IGC_TXDCTL_PTHRESH(x) FIELD_PREP(IGC_TXDCTL_PTHRESH_MASK, (x)) +#define IGC_TXDCTL_HTHRESH(x) FIELD_PREP(IGC_TXDCTL_HTHRESH_MASK, (x)) +#define IGC_TXDCTL_WTHRESH(x) FIELD_PREP(IGC_TXDCTL_WTHRESH_MASK, (x)) /* Ena specific Tx Queue */ -#define IGC_TXDCTL_QUEUE_ENABLE 0x02000000 +#define IGC_TXDCTL_QUEUE_ENABLE FIELD_PREP(IGC_TXDCTL_QUEUE_ENABLE_MASK, = 1) /* Transmit Software Flush */ -#define IGC_TXDCTL_SWFLUSH 0x04000000 +#define IGC_TXDCTL_SWFLUSH FIELD_PREP(IGC_TXDCTL_SWFLUSH_MASK, 1) =20 #define IGC_RX_DMA_ATTR \ (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) diff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethern= et/intel/igc/igc_main.c index 4f1a8bc006c6..f3a312c9413b 100644 --- a/drivers/net/ethernet/intel/igc/igc_main.c +++ b/drivers/net/ethernet/intel/igc/igc_main.c @@ -749,11 +749,9 @@ static void igc_configure_tx_ring(struct igc_adapter *= adapter, wr32(IGC_TDH(reg_idx), 0); writel(0, ring->tail); =20 - txdctl |=3D IGC_TXDCTL_PTHRESH; - txdctl |=3D IGC_TXDCTL_HTHRESH << 8; - txdctl |=3D IGC_TXDCTL_WTHRESH << 16; + txdctl |=3D IGC_TXDCTL_PTHRESH(8) | IGC_TXDCTL_HTHRESH(1) | + IGC_TXDCTL_WTHRESH(16) | IGC_TXDCTL_QUEUE_ENABLE; =20 - txdctl |=3D IGC_TXDCTL_QUEUE_ENABLE; wr32(IGC_TXDCTL(reg_idx), txdctl); } =20 --=20 2.34.1