From nobody Tue Feb 10 05:43:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CEA8E28368D; Wed, 14 May 2025 15:12:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747235520; cv=none; b=RFkM6wpWyVLnG7Y20yZ18Ad2FXk7RXOip503/rD04N89TXoE6Iy+3YlEHTz3iGFRCVazKdYjJ0HG+bAR6TiXazj5IEvKlXjHt9hQhgOnC0RswjfHCNzK7Bt0X78iTiOrL/0Tv56ccDOlngsShCwPUjpa6qBdfwIdQSBS97unFQ8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747235520; c=relaxed/simple; bh=Hf3yeg1WG/z7INDo4b2QRGGuu17lQVYeFJrtiNhG/f4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=azyFBRYTuUqxlDo2mcNJZ2qH/KHRYviMe/xkYCztYYp1F7GZ6FPCEj3gJz/WC7ZEB+/TzU1cqwvr0RxpRkUDpp8kV3/WDgm3Xqll9IbquW0V3nyzXpLdG6GdoJtn2Kg3WVn5sgMasiWbQXsthEYv/im6REToHaWMXh2PnZC41ug= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Ne11gRYW; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Ne11gRYW" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7831CC4CEE3; Wed, 14 May 2025 15:11:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747235520; bh=Hf3yeg1WG/z7INDo4b2QRGGuu17lQVYeFJrtiNhG/f4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Ne11gRYWj3lgEpcZrYSohDydfOYZvORQ1fzMRn23X7XgnG5NBJu5ZptVagwkDDdWB 77mnYKrnKHaO/0a7UIUGmw12f13ew0CjDDoOgdvdLoi0Zsz/armAGlQL02TKvHS4bX qQtnX1PE5cJ8ahIAEPBwl0FF1I9J7EgZUMgMmxJ2Nvo6dVY0muBQYrdJXH/a8qzG4V fVSsnfpEkoDSacxo2OUEAlSGPgc43vNl1txhBeTvO4eBgnbyY85bx3awQi0W520EpZ K4ThhfSrDds0sCys1P8rOo/Ny3zyBJLVEx4iCX2mSiFnQ6QFwM2iLMppH5OSqNlrtn 4Q9syGAR98YxA== From: Konrad Dybcio Date: Wed, 14 May 2025 17:10:35 +0200 Subject: [PATCH RFC RFT v2 15/15] drm/msm/a6xx: Warn if the highest_bank_bit value is overwritten Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250514-topic-ubwc_central-v2-15-09ecbc0a05ce@oss.qualcomm.com> References: <20250514-topic-ubwc_central-v2-0-09ecbc0a05ce@oss.qualcomm.com> In-Reply-To: <20250514-topic-ubwc_central-v2-0-09ecbc0a05ce@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Akhil P Oommen , Sean Paul , David Airlie , Simona Vetter Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747235442; l=1451; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=NNwmHE/NXY7JNBB9ewjFIbDQ2ogaNlnpROm0GZClv6g=; b=c2HWY6JbvvY3r20QpOfuIVaoNxVaYPVeIJTkCQio4TyRUikHhSB6rqKK5+IfpP8nIUNZkkGbk 03TnjpR85eqAiGlt0YgcL7Dc/g0lQUQA6bnpCfJUs4vsAjvI2pUmGSK X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio In preparation to resolve the issue of hardcoding HBB, throw a warning if the value is being overwritten in the GPU driver. The HBB value is directly correlated with the memory configuration. On platforms where more than one is supported, the value must differ for proper functioning of the hardware, but it also must be consistent across all UBWC producers/consumers. On platforms supporting only a single DRAM setup, the value may still be wrong, or at least inconsistent. Print a warning to help catch such cases, until we declare full trust to the central database. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index eaf468b67f97ff153e92a73a45581228fcf75e46..ab812338739568d5908ca439e5c= 53e230a02de5d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -637,6 +637,10 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gp= u) if (adreno_is_a702(gpu)) cfg->highest_bank_bit =3D 14; =20 + if (cfg->highest_bank_bit !=3D common_cfg->highest_bank_bit) + DRM_WARN_ONCE("Inconclusive highest_bank_bit value: %u (GPU) vs %u (UBWC= _CFG)\n", + cfg->highest_bank_bit, common_cfg->highest_bank_bit); + gpu->ubwc_config =3D &gpu->_ubwc_config; =20 return 0; --=20 2.49.0