From nobody Sun Feb 8 01:51:58 2026 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 282062770B; Tue, 13 May 2025 21:59:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747173587; cv=none; b=higyN6/1TDYkDSE3SyRtMTCdFposuwTfsL84t1+8qa6lAH27K0Y44O6EapJX+YlU4+imELJGILpxHhsseUWlgvT0089e/zAyiei8nl/wK79MjWAjPw7ZzXOgQPnaKFKPvDLbvx5zN2T1PtKU54j5Kad776vh4HNdh1Vq8uCBxDM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747173587; c=relaxed/simple; bh=ntDm6nMYwj9nso877Gv0Ll0lYiGUYVC4kTqiZ2cOGrM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dhrYqJPLIDt+zCLV7PLrNmm4drkHQkQRFNvRdlZKH69ka3Gfl0vWF11gIandEnv5t9vFcLZoJldH2owBwuiMh9ouE5Lab0u9eYMZZum9q338oZOXDBxY+3Fa2u+DnkY/YZV6wmfL36rlJNvA+yQW/nUosT0w4EJR4DYgRYd5Z9I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=VYO8tJDf; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="VYO8tJDf" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTP id 54DLxa7l2425893; Tue, 13 May 2025 16:59:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1747173576; bh=qmQfcLpiSyLwy3Zc5zbrGssZMtkDmMAcUwLjz7QJh1g=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=VYO8tJDfkIroqj/Xvx4yPWEaQDxkcQSISNZS4QLwOtrV7lPkoxtGea5Lc8+WeNbov ZuZbj0hZA8xyXfAuSXGX+EytnYg9dnLaqXDVb3hwpRsuM+27CSb4IETYJDFITFs53t xYyW1bqhZGTvTxxFRX13wy1+wHJP5KtFsJCcO3kI= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 54DLxZ021005887 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Tue, 13 May 2025 16:59:35 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 13 May 2025 16:59:34 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 13 May 2025 16:59:34 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 54DLxYdC111031; Tue, 13 May 2025 16:59:34 -0500 From: Judith Mendez To: Judith Mendez , Greg Kroah-Hartman , Jiri Slaby CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Santosh Shilimkar , Vignesh Raghavendra , Tero Kristo , Bin Liu , Andy Shevchenko , Andrew Davis , , , , Subject: [PATCH 1/7] dt-bindings: serial: add binding documentation for TI PRUSS UART Date: Tue, 13 May 2025 16:59:28 -0500 Message-ID: <20250513215934.933807-2-jm@ti.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250513215934.933807-1-jm@ti.com> References: <20250513215934.933807-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Bin Liu This adds the YAML DT binding for PRUSS UART on TI SoCs. Signed-off-by: Bin Liu Signed-off-by: Judith Mendez --- .../bindings/serial/ti,pruss-uart.yaml | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/ti,pruss-uart.= yaml diff --git a/Documentation/devicetree/bindings/serial/ti,pruss-uart.yaml b/= Documentation/devicetree/bindings/serial/ti,pruss-uart.yaml new file mode 100644 index 000000000000..34a03d572333 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/ti,pruss-uart.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/ti,pruss-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI PRUSS serial UART + +maintainers: + - Bin Liu + +description: | + The PRU subsystem has a serial UART peripheral based on the industry + standard TL16C550, with 16-byte TX/RX FIFOs. + +allOf: + - $ref: /schemas/serial.yaml# + +properties: + compatible: + items: + - const: ti,pruss-uart + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + description: | + PRU UART interrupt mappings, containing an entry of 3 cell-values. + The first is the PRU System Event ID for PRU UART Interrupt Request. + The second is the PRU interrupt channel ID. + The third is the PRU host interrupt ID. + +required: + - compatible + - reg + - clocks + - interrupts + +additionalProperties: false + +examples: + - | + pruss_uart: serial@28000 { + compatible =3D "ti,pruss-uart"; + reg =3D <0x28000 0x40>; + clocks =3D <&k3_clks 81 13>; + interrupt-parent =3D <&pruss_intc>; + interrupts =3D <6 4 4>; + }; --=20 2.49.0 From nobody Sun Feb 8 01:51:58 2026 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 409621FAC30; Tue, 13 May 2025 21:59:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747173588; cv=none; b=NKYYLWOZ985zR6zgjDlyCF6qGjdH4kTnOZd9OhYrNlt9O1j2mqhFSOnQtfeZv1fcY9gRKwralwHaPF1aXvHU8uYeN6xXOXmrhaIAJvXDo+pAzQjKdihJSrviZk/n1MflC1bEea/XnFfb1HCFpNrMYDlQrTyl/HmYXKz6QOjyY00= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747173588; c=relaxed/simple; bh=KZEn/QtXsHYg73UlRGGnMR1jgTy07zQFPZnzyBRyfUg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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Tue, 13 May 2025 16:59:34 -0500 From: Judith Mendez To: Judith Mendez , Greg Kroah-Hartman , Jiri Slaby CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Santosh Shilimkar , Vignesh Raghavendra , Tero Kristo , Bin Liu , Andy Shevchenko , Andrew Davis , , , , Subject: [PATCH 2/7] dt-bindings: soc: ti: pruss: Add documentation for PRU UART support Date: Tue, 13 May 2025 16:59:29 -0500 Message-ID: <20250513215934.933807-3-jm@ti.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250513215934.933807-1-jm@ti.com> References: <20250513215934.933807-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Add documentation for PRU UART node which is for PRU serial UART based-off the industry standard TL16C550 asynchronous communications element. Signed-off-by: Judith Mendez --- Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml b/Docum= entation/devicetree/bindings/soc/ti/ti,pruss.yaml index 927b3200e29e..54397297cbf5 100644 --- a/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml +++ b/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml @@ -324,6 +324,13 @@ patternProperties: $ref: /schemas/net/ti,davinci-mdio.yaml# type: object =20 + serial@[a-f0-9]+$: + description: | + Serial UART sub-module. A PRUSS can have a serial UART sub-module ba= sed + on the industry standard TL16C550 asynchronous communications elemen= t. + $ref: /schemas/serial/ti,pruss-uart.yaml# + type: object + "^(pru|rtu|txpru)@[0-9a-f]+$": description: | PRU Node. Each PRUSS has dual PRU cores, each represented as a Remot= eProc --=20 2.49.0 From nobody Sun Feb 8 01:51:58 2026 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 90C15216386; Tue, 13 May 2025 21:59:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747173600; cv=none; b=Qs6PX3CZUuUxz3JkslhGV5/NY3sTMFTbW7vxYSh16Oxh6RJhxqX898JZWFtnmUEOzWhiWrNFytviF6rkafO1432c5xVdOgptcuEtiexdiMtafnPFlilMk7kMdew8XVdKUnMM8NYlvbqhP/3EA70tkIf6Y+rI5p29ucnwgkUSjoA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747173600; c=relaxed/simple; bh=7dM0csk/Le537zRg7Zsum00I82ANCkL4hbXK15kachY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hgJq5T/GpwdsmhEdRA39wN/LjjPn4calbf80TAPesj/jGTY7ODYMBYmGiORAV8T7kZsBncQuMSsH4iCjKFmFrp13Vz/dS6bmYA7h2u5hEFvHPFWJ9RAVd2pQmF7jE8m+Os8QtpAHYTTqVo+4LG6zVmCJ4zNRi/wYROQy9XBelNQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=Isxgsznd; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Isxgsznd" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 54DLxaFo2965935; Tue, 13 May 2025 16:59:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1747173576; bh=0pISafSJiVZnu+3T2nuCjyIRJYlg9QHOnQKp4Z5jklI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=IsxgsznddCdPywhjydnyipviNkC9XBG/eWHX1HwWW1Yxyx+q9VoiUjPrBJ4joR0sl R38j/DKlxxOWbdXmYxDaMvOmyZgCUXlpYORjuAV7NHZRpS2E5ITzsylQqvxUy2S2Ee g+3tGGKdfCm9AgljAz8kqyOxUyfrZWeDYw9POvHA= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 54DLxZD62966904 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Tue, 13 May 2025 16:59:35 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 13 May 2025 16:59:34 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 13 May 2025 16:59:34 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 54DLxYdE111031; Tue, 13 May 2025 16:59:34 -0500 From: Judith Mendez To: Judith Mendez , Greg Kroah-Hartman , Jiri Slaby CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Santosh Shilimkar , Vignesh Raghavendra , Tero Kristo , Bin Liu , Andy Shevchenko , Andrew Davis , , , , Subject: [PATCH 3/7] serial: 8250: Add PRUSS UART driver Date: Tue, 13 May 2025 16:59:30 -0500 Message-ID: <20250513215934.933807-4-jm@ti.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250513215934.933807-1-jm@ti.com> References: <20250513215934.933807-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Bin Liu This adds a new serial 8250 driver that supports the UART in PRUSS or PRU_ICSS*. The UART sub-module is based on the industry standard TL16C550 UART controller, which has 16-bytes FIFO and supports 16x and 13x over samplings. Signed-off-by: Bin Liu Signed-off-by: Judith Mendez --- drivers/tty/serial/8250/8250_pruss.c | 178 +++++++++++++++++++++++++++ drivers/tty/serial/8250/Kconfig | 11 ++ drivers/tty/serial/8250/Makefile | 1 + 3 files changed, 190 insertions(+) create mode 100644 drivers/tty/serial/8250/8250_pruss.c diff --git a/drivers/tty/serial/8250/8250_pruss.c b/drivers/tty/serial/8250= /8250_pruss.c new file mode 100644 index 000000000000..04a455580022 --- /dev/null +++ b/drivers/tty/serial/8250/8250_pruss.c @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Serial Port driver for PRUSS UART on TI platforms + * + * Copyright (C) 2025 by Texas Instruments Incorporated - http://www.ti.c= om/ + * Author: Bin Liu + */ +#include +#include +#include +#include +#include +#include + +#include "8250.h" + +/* PowerManagement and Emulation */ +#define PRUSS_UART_PEREMU_MGMT 12 +#define PRUSS_UART_TX_EN BIT(14) +#define PRUSS_UART_RX_EN BIT(13) +#define PRUSS_UART_FREE_RUN BIT(0) + +/* Oversampling Mode Select */ +#define PRUSS_UART_MDR 13 +#define PRUSS_UART_MDR_OSM_SEL_MASK BIT(0) +#define PRUSS_UART_MDR_16X_MODE 0 +#define PRUSS_UART_MDR_13X_MODE 1 + +struct pruss8250_data { + struct clk *clk; + int line; +}; + +static int pruss8250_startup(struct uart_port *port) +{ + int ret; + + port->serial_out(port, PRUSS_UART_PEREMU_MGMT, 0); + + ret =3D serial8250_do_startup(port); + if (!ret) + port->serial_out(port, PRUSS_UART_PEREMU_MGMT, PRUSS_UART_TX_EN | + PRUSS_UART_RX_EN | + PRUSS_UART_FREE_RUN); + + return ret; +} + +static unsigned int pruss8250_get_divisor(struct uart_port *port, + unsigned int baud, + unsigned int *frac) +{ + unsigned int uartclk =3D port->uartclk; + unsigned int div_13, div_16; + unsigned int abs_d13, abs_d16; + u16 quot; + + div_13 =3D DIV_ROUND_CLOSEST(uartclk, 13 * baud); + div_16 =3D DIV_ROUND_CLOSEST(uartclk, 16 * baud); + div_13 =3D div_13 ? : 1; + div_16 =3D div_16 ? : 1; + + abs_d13 =3D abs(baud - uartclk / 13 / div_13); + abs_d16 =3D abs(baud - uartclk / 16 / div_16); + + if (abs_d13 >=3D abs_d16) { + *frac =3D PRUSS_UART_MDR_16X_MODE; + quot =3D div_16; + } else { + *frac =3D PRUSS_UART_MDR_13X_MODE; + quot =3D div_13; + } + + return quot; +} + +static void pruss8250_set_divisor(struct uart_port *port, unsigned int bau= d, + unsigned int quot, unsigned int quot_frac) +{ + serial8250_do_set_divisor(port, baud, quot); + + /* + * quot_frac holds the MDR over-sampling mode + * which is set in pruss8250_get_divisor() + */ + quot_frac &=3D PRUSS_UART_MDR_OSM_SEL_MASK; + port->serial_out(port, PRUSS_UART_MDR, quot_frac); +} + +static int pruss8250_probe(struct platform_device *pdev) +{ + struct uart_8250_port port8250; + struct uart_port *port =3D &port8250.port; + struct device *dev =3D &pdev->dev; + struct pruss8250_data *data; + struct resource *res; + int ret; + + data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + memset(&port8250, 0, sizeof(port8250)); + + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "Failed to get resource"); + return -EINVAL; + } + + if (!port->uartclk) { + data->clk =3D devm_clk_get(dev, NULL); + if (IS_ERR(data->clk)) { + dev_err(dev, "Failed to get clock!\n"); + return -ENODEV; + } else { + port->uartclk =3D clk_get_rate(data->clk); + devm_clk_put(dev, data->clk); + } + } + + port->dev =3D dev; + port->mapbase =3D res->start; + port->mapsize =3D resource_size(res); + port->type =3D PORT_16550A; + port->flags =3D UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_FIXED_TYPE | + UPF_IOREMAP; + port->startup =3D pruss8250_startup; + port->rs485_config =3D serial8250_em485_config; + port->get_divisor =3D pruss8250_get_divisor; + port->set_divisor =3D pruss8250_set_divisor; + + ret =3D uart_read_port_properties(port); + if (ret) + return ret; + + port->iotype =3D UPIO_MEM32; + port->regshift =3D 2; + + spin_lock_init(&port8250.port.lock); + port8250.capabilities =3D UART_CAP_FIFO | UART_CAP_AFE; + + ret =3D serial8250_register_8250_port(&port8250); + if (ret < 0) + return dev_err_probe(dev, ret, "Unable to register 8250 port.\n"); + + data->line =3D ret; + platform_set_drvdata(pdev, data); + return 0; +} + +static void pruss8250_remove(struct platform_device *pdev) +{ + struct pruss8250_data *data =3D platform_get_drvdata(pdev); + + serial8250_unregister_port(data->line); +} + +static const struct of_device_id pruss8250_of_match[] =3D { + { .compatible =3D "ti,pruss-uart", .data =3D (void *)PORT_16550A }, + { /* Sentinel */ } +}; +MODULE_DEVICE_TABLE(of, pruss8250_of_match); + +static struct platform_driver pruss8250_driver =3D { + .driver =3D { + .name =3D "pruss8250", + .of_match_table =3D pruss8250_of_match, + }, + .probe =3D pruss8250_probe, + .remove =3D pruss8250_remove, +}; + +module_platform_driver(pruss8250_driver); + +MODULE_AUTHOR("Bin Liu To: Judith Mendez , Greg Kroah-Hartman , Jiri Slaby CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Santosh Shilimkar , Vignesh Raghavendra , Tero Kristo , Bin Liu , Andy Shevchenko , Andrew Davis , , , , Subject: [PATCH 4/7] DONOTMERGE: arm64: dts: ti: k3-am64-main: Add PRU UART nodes Date: Tue, 13 May 2025 16:59:31 -0500 Message-ID: <20250513215934.933807-5-jm@ti.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250513215934.933807-1-jm@ti.com> References: <20250513215934.933807-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" There is one PRU UART module in each PRU_ICSSG for am64 SoC. Add a PRU UART child node in each ICSSG node in am64 main voltage domain .dtsi file for am64x device. Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am64-main.dtsi index c7e5da37486a..5ba7b8a8dbcf 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -1280,6 +1280,15 @@ icssg0_iepclk_mux: iepclk-mux@30 { }; }; =20 + icssg0_uart: serial@28000 { + compatible =3D "ti,pruss-uart"; + reg =3D <0x28000 0x40>; + clocks =3D <&k3_clks 81 19>; + interrupt-parent =3D <&icssg0_intc>; + interrupts =3D <6 7 7>; + status =3D "disabled"; + }; + icssg0_iep0: iep@2e000 { compatible =3D "ti,am654-icss-iep"; reg =3D <0x2e000 0x1000>; @@ -1459,6 +1468,15 @@ icssg1_iepclk_mux: iepclk-mux@30 { }; }; =20 + icssg1_uart: serial@28000 { + compatible =3D "ti,pruss-uart"; + reg =3D <0x28000 0x40>; + clocks =3D <&k3_clks 82 19>; + interrupt-parent =3D <&icssg1_intc>; + interrupts =3D <6 7 7>; + status =3D "disabled"; + }; + icssg1_iep0: iep@2e000 { compatible =3D "ti,am654-icss-iep"; reg =3D <0x2e000 0x1000>; --=20 2.49.0 From nobody Sun Feb 8 01:51:58 2026 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61FC520C461; Tue, 13 May 2025 21:59:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747173600; cv=none; b=B0DFT2DsH5CxsRdLi1yarmvVZEBKjBNC7tD5VDJ7jsmPze1YcFBap7vHvhWCM8zaxfoPNlLa+rTjIMl5DCBIliRMQk1PfbpJrSWP6kgQZGFMLl2ZHntHr8SlRNLIVEuZ+fuShVk8x2pcNIriCLb1woL0ZhXl17aiRnwUj/oCc0A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747173600; c=relaxed/simple; bh=JwDW09i6Wb/dXp2iXbgQlj6eYiXj8mnV0MZVigxCgz8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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Tue, 13 May 2025 16:59:35 -0500 From: Judith Mendez To: Judith Mendez , Greg Kroah-Hartman , Jiri Slaby CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Santosh Shilimkar , Vignesh Raghavendra , Tero Kristo , Bin Liu , Andy Shevchenko , Andrew Davis , , , , Subject: [PATCH 5/7] DONOTMERGE: arm64: dts: ti: k3-am642-sk: Enable PRU UART Date: Tue, 13 May 2025 16:59:32 -0500 Message-ID: <20250513215934.933807-6-jm@ti.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250513215934.933807-1-jm@ti.com> References: <20250513215934.933807-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" There is one PRU UART module in each ICSSG for am64 SoC. UART RX/TX signals for PRU UART in ICSSG0 can be routed from/to the PRU Connector J10 (pins 45/44) on am64x SK, so enable icssg0_uart by default and add pinmux node. Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/t= i/k3-am642-sk.dts index 1deaa0be0085..9065fc8a7569 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -25,6 +25,7 @@ aliases { serial0 =3D &mcu_uart0; serial1 =3D &main_uart1; serial2 =3D &main_uart0; + serial3 =3D &icssg0_uart; i2c0 =3D &main_i2c0; i2c1 =3D &main_i2c1; mmc0 =3D &sdhci0; @@ -284,6 +285,15 @@ AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD = */ >; }; =20 + icssg0_uart_pins_default: icssg0-uart-default-pins { + pinctrl-single,pins =3D < + AM64X_IOPAD(0x0184, PIN_INPUT, 2) /* (W6) PRG0_PRU0_GPO9.PRG0_UART0_CTS= n */ + AM64X_IOPAD(0x0188, PIN_OUTPUT, 2) /* (AA5) PRG0_PRU0_GPO10.PRG0_UART0_= RTSn */ + AM64X_IOPAD(0x01d4, PIN_INPUT, 2) /* (Y5) PRG0_PRU1_GPO9.PRG0_UART0_RXD= */ + AM64X_IOPAD(0x01d8, PIN_OUTPUT, 2) /* (V6) PRG0_PRU1_GPO10.PRG0_UART0_T= XD */ + >; + }; + main_usb0_pins_default: main-usb0-default-pins { bootph-all; pinctrl-single,pins =3D < @@ -413,6 +423,12 @@ &main_uart1 { pinctrl-0 =3D <&main_uart1_pins_default>; }; =20 +&icssg0_uart { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&icssg0_uart_pins_default>; + status =3D "okay"; +}; + &main_i2c0 { bootph-all; status =3D "okay"; --=20 2.49.0 From nobody Sun Feb 8 01:51:58 2026 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 282661F4C90; Tue, 13 May 2025 21:59:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747173587; cv=none; b=tHd/reQs4wueelXi9RSrEd1dnwZp/QIgFwI4p3K2sCEGOnafVcWXIrJqBhjoA6GoUkkhJloU3YQwaM7JUb58A13jFpJQ6EZg2Xnn1An7pIz8G9OzqBn6waLIAZGnXtvt1FZh7yvjmPf9qQAAa0tiqzsgAzGTlRQqw3XSyyA7tjk= ARC-Message-Signature: i=1; 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Tue, 13 May 2025 16:59:35 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 54DLxYdH111031; Tue, 13 May 2025 16:59:35 -0500 From: Judith Mendez To: Judith Mendez , Greg Kroah-Hartman , Jiri Slaby CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Santosh Shilimkar , Vignesh Raghavendra , Tero Kristo , Bin Liu , Andy Shevchenko , Andrew Davis , , , , Subject: [PATCH 6/7] DONOTMERGE: arm64: dts: ti: k3-am62-main: Add PRU UART node Date: Tue, 13 May 2025 16:59:33 -0500 Message-ID: <20250513215934.933807-7-jm@ti.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250513215934.933807-1-jm@ti.com> References: <20250513215934.933807-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" There is one PRU UART module in the PRU subsystem for am62 SoC. Add a PRU UART child node in PRUSS node in am62 main voltage domain .dtsi file for am62x device. Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am62-main.dtsi index 9e0b6eee9ac7..c012f33f4609 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -1144,6 +1144,15 @@ pruss_intc: interrupt-controller@20000 { "host_intr6", "host_intr7"; }; =20 + pruss_uart: serial@28000 { + compatible =3D "ti,pruss-uart"; + reg =3D <0x28000 0x40>; + clocks =3D <&k3_clks 81 13>; /* pruss_uart_clk */ + interrupt-parent =3D <&pruss_intc>; + interrupts =3D <6 4 4>; + status =3D "disabled"; + }; + pru0: pru@34000 { compatible =3D "ti,am625-pru"; reg =3D <0x34000 0x3000>, --=20 2.49.0 From nobody Sun Feb 8 01:51:58 2026 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8FEB217659; Tue, 13 May 2025 22:00:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747173602; cv=none; b=tZiSIM1U9QLXMojF0XwX+vDSJ8E/lCY7bBk8JSPestBJPcHCNT0x+gVJNXPlcuMzWBzQsft9tZj4AcxOPpFpjELpHyiiJjUgTQme9bClVjkv87hHnu7n6PsDpuJ8hK5AWFRw53e7dEBNwTpK6eI6etwPNsj7HiBPfyB7HX28J8w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747173602; c=relaxed/simple; bh=5EjVsjxBlzfUERFXjaKmvuV82xLSUkfyC7+UBqTb/04=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pwGZL0mPn6JxSeD86bcdx+S86EIFHHXLqIKwPa6ccbd7a3O5ghT35Y6U6bXjMSk35qT3awDmaJkcTctQxpy4/zfEXJ0Xl5sl9FtYdGokeW8QPV16e0ZsBcFJb7s2nhB2YrAaDS25Wi0L/2vPslLtfLmYXefWSe3OvZAs1esB8vg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=xtoa2PHH; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="xtoa2PHH" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 54DLxaCl2431444; Tue, 13 May 2025 16:59:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1747173576; bh=PaXp3+Nc4om8rc2bk8qplk5oP4MocCsaSbkZb3DsCtw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xtoa2PHH8NNnlNIvxtJ0iTBfsGyJcMXfl8yIJK0einXWti5e0cubP7ZTzilM75ENp g2WwLiyouRLtfK6UkaueaGGSk1b3AZHHBwQM7Y+rMuzNGRq96l+5K/YBaqE/6HsIIO LVIxl45889/QWNR6mwFp38foUMwOC5bTRXUmKrHA= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 54DLxZON1005889 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Tue, 13 May 2025 16:59:35 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 13 May 2025 16:59:35 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 13 May 2025 16:59:35 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 54DLxYdI111031; Tue, 13 May 2025 16:59:35 -0500 From: Judith Mendez To: Judith Mendez , Greg Kroah-Hartman , Jiri Slaby CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Santosh Shilimkar , Vignesh Raghavendra , Tero Kristo , Bin Liu , Andy Shevchenko , Andrew Davis , , , , Subject: [PATCH 7/7] DONOTMERGE: arm64: dts: ti: k3-am62x-sk: Enable PRU UART Date: Tue, 13 May 2025 16:59:34 -0500 Message-ID: <20250513215934.933807-8-jm@ti.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250513215934.933807-1-jm@ti.com> References: <20250513215934.933807-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" There is one PRU UART module in the PRU subsystem for am62 SoC. UART RX/TX signals for PRU UART in PRU subsystem can be routed from/to the user expansion header J3 (pins 10/8) on am62x SK, so enable pruss_uart by default and add pinmux node. Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am62x-sk-common.dtsi index ee8337bfbbfd..c474e1d1a74d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -15,6 +15,7 @@ aliases { serial0 =3D &wkup_uart0; serial1 =3D &mcu_uart0; serial2 =3D &main_uart0; + serial3 =3D &pruss_uart; mmc0 =3D &sdhci0; mmc1 =3D &sdhci1; mmc2 =3D &sdhci2; @@ -181,6 +182,13 @@ AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20/D16) MCASP0_= ACLKR.UART1_TXD */ >; }; =20 + pruss_uart_pins: pruss-uart-pins { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x01d8, PIN_INPUT, 6) /* (C15) MCAN0_TX.PR0_UART0_RXD */ + AM62X_IOPAD(0x01dc, PIN_OUTPUT, 6) /* (E15) MCAN0_RX.PR0_UART0_TXD */ + >; + }; + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins =3D < AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16/E12) I2C0_SCL */ @@ -370,6 +378,12 @@ &main_uart1 { pinctrl-0 =3D <&main_uart1_pins_default>; }; =20 +&pruss_uart { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pruss_uart_pins>; + status =3D "okay"; +}; + &main_i2c0 { status =3D "okay"; pinctrl-names =3D "default"; --=20 2.49.0