From nobody Mon Feb 9 06:25:34 2026 Received: from mail-io1-f46.google.com (mail-io1-f46.google.com [209.85.166.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B45931FDA8B for ; Tue, 13 May 2025 21:53:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.166.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747173236; cv=none; b=J4LeVYLpylftq9OcO3f6YeF03xpYaBgdEmKi5IZERqKj5Ek/nlIrxSiHpI95/WS/bsiGWBS2uB+WEVo3D1s06qZXVln8TCYp9pu4m2/neVhB0NtGMlSJYutjBmQIPQfKzLDvMJXd9fDULW5GYooxEbX9ZDRPu9kdUnIVmVMPHvw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747173236; c=relaxed/simple; bh=Yykr4pXHm+eFZeLoxnQj4YQ7g7m8no0bRdRqTGC2FXA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nBzf8nD68Hr1b2XBiChGd8dXzO8Pee06wvX0/XUJqodqqgdLmc0IBnhw2zq2L8ZOKH9uBlGD9xE9xkO0aBs3iRMVLbedhR4c+tE++BAt/Hb7Y3DX+PVDAT0Tl/6+oPU803+wnSZgDMozpdFRqMSixvl66fQQ2SG0crKc6ht5Z/g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riscstar.com; spf=pass smtp.mailfrom=riscstar.com; dkim=pass (2048-bit key) header.d=riscstar-com.20230601.gappssmtp.com header.i=@riscstar-com.20230601.gappssmtp.com header.b=gXpny+Ur; arc=none smtp.client-ip=209.85.166.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riscstar.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=riscstar.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=riscstar-com.20230601.gappssmtp.com header.i=@riscstar-com.20230601.gappssmtp.com header.b="gXpny+Ur" Received: by mail-io1-f46.google.com with SMTP id ca18e2360f4ac-86135ae2a29so579832939f.2 for ; Tue, 13 May 2025 14:53:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=riscstar-com.20230601.gappssmtp.com; s=20230601; t=1747173234; x=1747778034; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CofZ6mxwdPQ5E5kE6D3I1SRbGpA+t1hpeEYsYL5jGT4=; b=gXpny+Ur7k15sHOEJAB2dlyV5YpsWLw24Zd+KUXyprQt59C4uVc9yRgjDmbZhKDzN3 QRjjmic1Az24priJhQisK68ZL+EHM7bwHZi58USfxlExxh4CqhAkOlXHDFPfyqcaoL+Z 8nuCuFJf5Tz7Fv7EssLrPfxu7XdNNy0q+VScW0rZku5xqpZW2K5RqyTJGUUGmD7UhMOm Xqfv6tVmRLp7ALSaudYDnY5I2F3mn73lTYqAgjV/Z9k0xFY9FLTQy15of97eg16I5G2h gzaM6LCaX6dly/KzsSzCXasdxmQR9ib2sGT9n3dms8kqZPZWOq1m7hwFIr93NOP25zlU ZEAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747173234; x=1747778034; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CofZ6mxwdPQ5E5kE6D3I1SRbGpA+t1hpeEYsYL5jGT4=; b=fdQ03QWGH2SSKav4kDy+C9shMVO3/qSnqHXbq6zUW23J3YgV2KXEXFY3m5fzEOgfyo 1t9GqbfcZThf0u+kOw8cMlrsAErKnhaB36oA27JAGjPziakfFWWee3GN64pf+tcCZLLa 9gnnEO+1CiwKy9fp7YYuJQ1or+sx+AanhZepg4OkjwNbh4L6hsM7DLeKwwE2LGR3sgrD PDuBHZKJYGGbsibogR1hsCWEGu7mThng2eGaVGakryqMypVZXk+nBfjzBP0xgG7u3ZaK EfiA3Yr9+1v6NcuMBVLtcp7YOhron6ewG00n6VWV/HVsqgjS4XJTdxCdWzCSU+d3FbS5 mTyg== X-Forwarded-Encrypted: i=1; AJvYcCXB9shG1aGYAYJKRy/q0X9JxEoN/ZZphPyCSyulog7c884cp25TVPHt0TIIH1PlHuhn75Q5alFrS//r/PI=@vger.kernel.org X-Gm-Message-State: AOJu0Yw3mVMkTbQ/kh6MjYUiAqMMlxAvFDqxASItUXHgWSYi0eIwRF2w sT0zUT0GeOaKgoqaB1Obsz16dPOaJBOAuQROurIDOQ29fiQPUDXknjoCm1dZjX0= X-Gm-Gg: ASbGnctV7qPR7oz+lAOpaCMCDjUQ3iFnywVaxS/W1WO2jRnqdy7GsXBushQkSPdgvcT m002+2cV6NEweJE5MJM08xDQ1Hl3kDdfJkKqy9u9jl2p679y5SezORPwCQmNj54/R9US4rAjzvz 9bOYkn9VgFZ9xfmdFHhJxwTeJlvciYRewQtUQTTS0XOWVA78loseJLDKqOtC28Lmf4XQ9OF2MX3 jUymSbuXXj5tsybmqb/oB80zznn4dEHXeWF1lPLDUoooVh5rdYsDvwRz8NmUxv445IAa3q6pQ6z FunlIdhpei3KqpAHPvTKR0pg8l2r6yaUIkFrbr/aNtfaHDxtnSZp5N/EAgViLY6Gw/JdrkX8N+e l5ef+Wk3PIhi/xXHBA5lr429w X-Google-Smtp-Source: AGHT+IE+tdGzdtN7678iU4Ivi8ODMsCF92xBzdacl7enWU++qN65n+N0dHtpayrDwOqxA6q/g4x1TA== X-Received: by 2002:a05:6602:3a01:b0:861:d8ca:3587 with SMTP id ca18e2360f4ac-86a08dcff41mr132336939f.4.1747173233800; Tue, 13 May 2025 14:53:53 -0700 (PDT) Received: from localhost.localdomain (c-73-228-159-35.hsd1.mn.comcast.net. [73.228.159.35]) by smtp.gmail.com with ESMTPSA id ca18e2360f4ac-867636e0dedsm239622539f.32.2025.05.13.14.53.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 May 2025 14:53:53 -0700 (PDT) From: Alex Elder To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, dlan@gentoo.org Cc: heylenay@4d2.org, inochiama@outlook.com, guodong@riscstar.com, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, spacemit@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 3/6] clk: spacemit: set up reset auxiliary devices Date: Tue, 13 May 2025 16:53:41 -0500 Message-ID: <20250513215345.3631593-4-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250513215345.3631593-1-elder@riscstar.com> References: <20250513215345.3631593-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a new reset_name field to the spacemit_ccu_data structure. If it is non-null, the CCU implements a reset controller, and the name will be used in the name for the auxiliary device that implements it. Define a new type to hold an auxiliary device as well as the regmap pointer that will be needed by CCU reset controllers. Set up code to initialize and add an auxiliary device for any CCU that implements reset functionality. Make it optional for a CCU to implement a clock controller. This doesn't apply to any of the existing CCUs but will for some new ones that will be added soon. Signed-off-by: Alex Elder Reviewed-by: Haylen Chu Reviewed-by: Yixun Lan --- drivers/clk/spacemit/Kconfig | 1 + drivers/clk/spacemit/ccu-k1.c | 104 ++++++++++++++++++++++++++++--- include/soc/spacemit/k1-syscon.h | 12 ++++ 3 files changed, 107 insertions(+), 10 deletions(-) diff --git a/drivers/clk/spacemit/Kconfig b/drivers/clk/spacemit/Kconfig index 4c4df845b3cb2..3854f6ae6d0ea 100644 --- a/drivers/clk/spacemit/Kconfig +++ b/drivers/clk/spacemit/Kconfig @@ -3,6 +3,7 @@ config SPACEMIT_CCU tristate "Clock support for SpacemiT SoCs" depends on ARCH_SPACEMIT || COMPILE_TEST + select AUXILIARY_BUS select MFD_SYSCON help Say Y to enable clock controller unit support for SpacemiT SoCs. diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index 801150f4ff0f5..1c9ed434ae93e 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -5,12 +5,15 @@ */ =20 #include +#include #include #include +#include #include #include #include #include +#include #include =20 #include "ccu_common.h" @@ -21,10 +24,13 @@ #include =20 struct spacemit_ccu_data { + const char *reset_name; struct clk_hw **hws; size_t num; }; =20 +static DEFINE_IDA(auxiliary_ids); + /* APBS clocks start, APBS region contains and only contains all PLL clock= s */ =20 /* @@ -710,8 +716,9 @@ static struct clk_hw *k1_ccu_pll_hws[] =3D { }; =20 static const struct spacemit_ccu_data k1_ccu_pll_data =3D { - .hws =3D k1_ccu_pll_hws, - .num =3D ARRAY_SIZE(k1_ccu_pll_hws), + /* The PLL CCU implements no resets */ + .hws =3D k1_ccu_pll_hws, + .num =3D ARRAY_SIZE(k1_ccu_pll_hws), }; =20 static struct clk_hw *k1_ccu_mpmu_hws[] =3D { @@ -751,8 +758,9 @@ static struct clk_hw *k1_ccu_mpmu_hws[] =3D { }; =20 static const struct spacemit_ccu_data k1_ccu_mpmu_data =3D { - .hws =3D k1_ccu_mpmu_hws, - .num =3D ARRAY_SIZE(k1_ccu_mpmu_hws), + .reset_name =3D "mpmu-reset", + .hws =3D k1_ccu_mpmu_hws, + .num =3D ARRAY_SIZE(k1_ccu_mpmu_hws), }; =20 static struct clk_hw *k1_ccu_apbc_hws[] =3D { @@ -859,8 +867,9 @@ static struct clk_hw *k1_ccu_apbc_hws[] =3D { }; =20 static const struct spacemit_ccu_data k1_ccu_apbc_data =3D { - .hws =3D k1_ccu_apbc_hws, - .num =3D ARRAY_SIZE(k1_ccu_apbc_hws), + .reset_name =3D "apbc-reset", + .hws =3D k1_ccu_apbc_hws, + .num =3D ARRAY_SIZE(k1_ccu_apbc_hws), }; =20 static struct clk_hw *k1_ccu_apmu_hws[] =3D { @@ -929,8 +938,9 @@ static struct clk_hw *k1_ccu_apmu_hws[] =3D { }; =20 static const struct spacemit_ccu_data k1_ccu_apmu_data =3D { - .hws =3D k1_ccu_apmu_hws, - .num =3D ARRAY_SIZE(k1_ccu_apmu_hws), + .reset_name =3D "apmu-reset", + .hws =3D k1_ccu_apmu_hws, + .num =3D ARRAY_SIZE(k1_ccu_apmu_hws), }; =20 static int spacemit_ccu_register(struct device *dev, @@ -941,6 +951,10 @@ static int spacemit_ccu_register(struct device *dev, struct clk_hw_onecell_data *clk_data; int i, ret; =20 + /* Nothing to do if the CCU does not implement any clocks */ + if (!data->hws) + return 0; + clk_data =3D devm_kzalloc(dev, struct_size(clk_data, hws, data->num), GFP_KERNEL); if (!clk_data) @@ -981,9 +995,74 @@ static int spacemit_ccu_register(struct device *dev, return ret; } =20 +static void spacemit_cadev_release(struct device *dev) +{ + struct auxiliary_device *adev =3D to_auxiliary_dev(dev); + + ida_free(&auxiliary_ids, adev->id); + kfree(to_spacemit_ccu_adev(adev)); +} + +static void spacemit_adev_unregister(void *data) +{ + struct auxiliary_device *adev =3D data; + + auxiliary_device_delete(adev); + auxiliary_device_uninit(adev); +} + +static int spacemit_ccu_reset_register(struct device *dev, + struct regmap *regmap, + const char *reset_name) +{ + struct spacemit_ccu_adev *cadev; + struct auxiliary_device *adev; + int ret; + + /* Nothing to do if the CCU does not implement a reset controller */ + if (!reset_name) + return 0; + + cadev =3D kzalloc(sizeof(*cadev), GFP_KERNEL); + if (!cadev) + return -ENOMEM; + + cadev->regmap =3D regmap; + + adev =3D &cadev->adev; + adev->name =3D reset_name; + adev->dev.parent =3D dev; + adev->dev.release =3D spacemit_cadev_release; + adev->dev.of_node =3D dev->of_node; + ret =3D ida_alloc(&auxiliary_ids, GFP_KERNEL); + if (ret < 0) + goto err_free_cadev; + adev->id =3D ret; + + ret =3D auxiliary_device_init(adev); + if (ret) + goto err_free_aux_id; + + ret =3D auxiliary_device_add(adev); + if (ret) { + auxiliary_device_uninit(adev); + return ret; + } + + return devm_add_action_or_reset(dev, spacemit_adev_unregister, adev); + +err_free_aux_id: + ida_free(&auxiliary_ids, adev->id); +err_free_cadev: + kfree(cadev); + + return ret; +} + static int k1_ccu_probe(struct platform_device *pdev) { struct regmap *base_regmap, *lock_regmap =3D NULL; + const struct spacemit_ccu_data *data; struct device *dev =3D &pdev->dev; int ret; =20 @@ -1012,11 +1091,16 @@ static int k1_ccu_probe(struct platform_device *pde= v) "failed to get lock regmap\n"); } =20 - ret =3D spacemit_ccu_register(dev, base_regmap, lock_regmap, - of_device_get_match_data(dev)); + data =3D of_device_get_match_data(dev); + + ret =3D spacemit_ccu_register(dev, base_regmap, lock_regmap, data); if (ret) return dev_err_probe(dev, ret, "failed to register clocks\n"); =20 + ret =3D spacemit_ccu_reset_register(dev, base_regmap, data->reset_name); + if (ret) + return dev_err_probe(dev, ret, "failed to register resets\n"); + return 0; } =20 diff --git a/include/soc/spacemit/k1-syscon.h b/include/soc/spacemit/k1-sys= con.h index 039a448c51a07..53eff7691f33d 100644 --- a/include/soc/spacemit/k1-syscon.h +++ b/include/soc/spacemit/k1-syscon.h @@ -5,6 +5,18 @@ #ifndef __SOC_K1_SYSCON_H__ #define __SOC_K1_SYSCON_H__ =20 +/* Auxiliary device used to represent a CCU reset controller */ +struct spacemit_ccu_adev { + struct auxiliary_device adev; + struct regmap *regmap; +}; + +static inline struct spacemit_ccu_adev * +to_spacemit_ccu_adev(struct auxiliary_device *adev) +{ + return container_of(adev, struct spacemit_ccu_adev, adev); +} + /* APBS register offset */ #define APBS_PLL1_SWCR1 0x100 #define APBS_PLL1_SWCR2 0x104 --=20 2.45.2