From nobody Sun Feb 8 03:32:30 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E32C1A3A8D; Tue, 13 May 2025 20:37:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747168679; cv=none; b=tBWIaImVTpr1wlrCktyrUtfaKXpGZxjRekjR24gEy6dsEJh9AiV2AeQ/Qjb7MU3G9Yy8fFdud2s81cl4B6CEHK6E2/79eRTzTZjd9WO0tVvrHfadrZ81mFC1fP87V91umSzd+XvBu604Rlm7/094YY2DCtmP0AdqaVzyQPYgXmw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747168679; c=relaxed/simple; bh=hyHqRWQkgZHimpVOiM5Vr4ymbwLjjHj3vyxzS3WaAW8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mexyEP6OzDEov+HgZ3wWIUEQoWm/Kp/GefiR7GGMKvyT2FWVU7KNai7s1nS6l2OHqJtmiBdKKgafpaE2awtzMBPirqaQoUlbg0TnN48GCWjPvvhKCih6xVe8zzYcQ9csPCUL3Z88dwrdBDr+6XbWIqeLtzwzh2OFQrgg7HclzyI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=IMzBGrsm; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="IMzBGrsm" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1747168678; x=1778704678; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hyHqRWQkgZHimpVOiM5Vr4ymbwLjjHj3vyxzS3WaAW8=; b=IMzBGrsmUbyh3LZjHw5+6kasJf94KGAF0odU2T35e+oa/iEyQj8uEdst fjL/StFctUBF/HiTnH+YEslKoYQDyBhMbL2jUHjNfaOKOk2C4jqIUfLsE tgTrRSZenKwEVfG9aEfRyIyWXiH0qxjh3VaUQmQqaNxeOTBZryMiyJ0jC WDwYyujh2Vfv6DHu3z36fH2VJ2XMzsa+8hAdHLs5crId00JOxYl2SKlv2 tyac11XutO49DmxZI7XdMcJeAyU/NDbtqkOfAkvfeJIz8wN8AUJXIxUcB XIeK/yKZb5LzkgElA9nvEskZ6TDxquRGNQX7gExZs1IbpxZytD7uBOqfy w==; X-CSE-ConnectionGUID: Wa1Coh/cTGiPqoayBXJSMg== X-CSE-MsgGUID: mDH0WrUqRiKRDEvIl3zFsQ== X-IronPort-AV: E=McAfee;i="6700,10204,11432"; a="49160397" X-IronPort-AV: E=Sophos;i="6.15,286,1739865600"; d="scan'208";a="49160397" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2025 13:37:56 -0700 X-CSE-ConnectionGUID: Vhzvh1imRuGZrVTfH1G2PQ== X-CSE-MsgGUID: OduXNNR1QUS8yfqCK9BMdQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,286,1739865600"; d="scan'208";a="138241714" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa008.fm.intel.com with ESMTP; 13 May 2025 13:37:55 -0700 From: Sohil Mehta To: x86@kernel.org, linux-kernel@vger.kernel.org Cc: Xin Li , "H . Peter Anvin" , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , Peter Zijlstra , Sean Christopherson , Adrian Hunter , Kan Liang , Tony Luck , Zhang Rui , Steven Rostedt , Sohil Mehta , Andrew Cooper , "Kirill A . Shutemov" , Jacob Pan , Andi Kleen , Kai Huang , Sandipan Das , linux-perf-users@vger.kernel.org, linux-edac@vger.kernel.org, kvm@vger.kernel.org, linux-pm@vger.kernel.org, linux-trace-kernel@vger.kernel.org Subject: [PATCH v6 1/9] x86/fred, KVM: VMX: Pass event data to the FRED entry point from KVM Date: Tue, 13 May 2025 13:37:55 -0700 Message-ID: <20250513203803.2636561-2-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513203803.2636561-1-sohil.mehta@intel.com> References: <20250513203803.2636561-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Zeng Guang Extend the FRED entry point from KVM to take an extra argument to allow KVM to invoke the FRED event dispatch framework with event data. The first use of this extended API is to pass the NMI-source bitmap for NMI-induced VM exits. Read the VMCS exit qualification field to get the NMI-source information and store it as event data precisely in the format expected by the FRED event framework. Read the VMCS exit qualification unconditionally since almost all upcoming CPUs are expected to enable FRED and NMI-source together. In the rare case that NMI-source isn't enabled, the extra VMREAD would be harmless since the exit qualification is expected to be zero. Suggested-by: Sean Christopherson Signed-off-by: Zeng Guang Signed-off-by: Sohil Mehta --- v6: No change v5: Read the VMCS exit qualification unconditionally. (Sean) Combine related patches into one. --- arch/x86/entry/entry_64_fred.S | 2 +- arch/x86/include/asm/fred.h | 9 +++++---- arch/x86/kvm/vmx/vmx.c | 5 +++-- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/x86/entry/entry_64_fred.S b/arch/x86/entry/entry_64_fred.S index 29c5c32c16c3..a61256be9703 100644 --- a/arch/x86/entry/entry_64_fred.S +++ b/arch/x86/entry/entry_64_fred.S @@ -93,7 +93,7 @@ SYM_FUNC_START(asm_fred_entry_from_kvm) * +--------+-----------------+ */ push $0 /* Reserved, must be 0 */ - push $0 /* Event data, 0 for IRQ/NMI */ + push %rsi /* Event data for IRQ/NMI */ push %rdi /* fred_ss handed in by the caller */ push %rbp pushf diff --git a/arch/x86/include/asm/fred.h b/arch/x86/include/asm/fred.h index 2a29e5216881..a4de57e578c4 100644 --- a/arch/x86/include/asm/fred.h +++ b/arch/x86/include/asm/fred.h @@ -64,14 +64,15 @@ static __always_inline unsigned long fred_event_data(st= ruct pt_regs *regs) =20 void asm_fred_entrypoint_user(void); void asm_fred_entrypoint_kernel(void); -void asm_fred_entry_from_kvm(struct fred_ss); +void asm_fred_entry_from_kvm(struct fred_ss ss, unsigned long edata); =20 __visible void fred_entry_from_user(struct pt_regs *regs); __visible void fred_entry_from_kernel(struct pt_regs *regs); __visible void __fred_entry_from_kvm(struct pt_regs *regs); =20 /* Can be called from noinstr code, thus __always_inline */ -static __always_inline void fred_entry_from_kvm(unsigned int type, unsigne= d int vector) +static __always_inline void fred_entry_from_kvm(unsigned int type, unsigne= d int vector, + unsigned long edata) { struct fred_ss ss =3D { .ss =3D__KERNEL_DS, @@ -81,7 +82,7 @@ static __always_inline void fred_entry_from_kvm(unsigned = int type, unsigned int .lm =3D 1, }; =20 - asm_fred_entry_from_kvm(ss); + asm_fred_entry_from_kvm(ss, edata); } =20 void cpu_init_fred_exceptions(void); @@ -109,7 +110,7 @@ static __always_inline unsigned long fred_event_data(st= ruct pt_regs *regs) { ret static inline void cpu_init_fred_exceptions(void) { } static inline void cpu_init_fred_rsps(void) { } static inline void fred_complete_exception_setup(void) { } -static inline void fred_entry_from_kvm(unsigned int type, unsigned int vec= tor) { } +static inline void fred_entry_from_kvm(unsigned int type, unsigned int vec= tor, unsigned long edata) { } static inline void fred_sync_rsp0(unsigned long rsp0) { } static inline void fred_update_rsp0(void) { } #endif /* CONFIG_X86_FRED */ diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 5c5766467a61..1d43d4a2f6b6 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7079,7 +7079,7 @@ static void handle_external_interrupt_irqoff(struct k= vm_vcpu *vcpu, =20 kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ); if (cpu_feature_enabled(X86_FEATURE_FRED)) - fred_entry_from_kvm(EVENT_TYPE_EXTINT, vector); + fred_entry_from_kvm(EVENT_TYPE_EXTINT, vector, 0); else vmx_do_interrupt_irqoff(gate_offset((gate_desc *)host_idt_base + vector)= ); kvm_after_interrupt(vcpu); @@ -7393,7 +7393,8 @@ static noinstr void vmx_vcpu_enter_exit(struct kvm_vc= pu *vcpu, is_nmi(vmx_get_intr_info(vcpu))) { kvm_before_interrupt(vcpu, KVM_HANDLING_NMI); if (cpu_feature_enabled(X86_FEATURE_FRED)) - fred_entry_from_kvm(EVENT_TYPE_NMI, NMI_VECTOR); + fred_entry_from_kvm(EVENT_TYPE_NMI, NMI_VECTOR, + vmx_get_exit_qual(vcpu)); else vmx_do_nmi_irqoff(); kvm_after_interrupt(vcpu); --=20 2.43.0 From nobody Sun Feb 8 03:32:30 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D795C1F0E39; Tue, 13 May 2025 20:37:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a="49160410" X-IronPort-AV: E=Sophos;i="6.15,286,1739865600"; d="scan'208";a="49160410" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2025 13:37:57 -0700 X-CSE-ConnectionGUID: Xw06lpQSSFSE75MB0qtKqA== X-CSE-MsgGUID: ZI2hiD/kTRa1TZeilup5aw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,286,1739865600"; d="scan'208";a="138241718" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa008.fm.intel.com with ESMTP; 13 May 2025 13:37:56 -0700 From: Sohil Mehta To: x86@kernel.org, linux-kernel@vger.kernel.org Cc: Xin Li , "H . Peter Anvin" , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , Peter Zijlstra , Sean Christopherson , Adrian Hunter , Kan Liang , Tony Luck , Zhang Rui , Steven Rostedt , Sohil Mehta , Andrew Cooper , "Kirill A . Shutemov" , Jacob Pan , Andi Kleen , Kai Huang , Sandipan Das , linux-perf-users@vger.kernel.org, linux-edac@vger.kernel.org, kvm@vger.kernel.org, linux-pm@vger.kernel.org, linux-trace-kernel@vger.kernel.org Subject: [PATCH v6 2/9] x86/cpufeatures: Add the CPUID feature bit for NMI-source reporting Date: Tue, 13 May 2025 13:37:56 -0700 Message-ID: <20250513203803.2636561-3-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513203803.2636561-1-sohil.mehta@intel.com> References: <20250513203803.2636561-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" NMI-source reporting is introduced to report the sources of NMIs with FRED event delivery based on vectors in NMI interrupt messages or the local APIC. This enables the kernel to avoid the latency incurred by going over the entire NMI handler list and reduces ambiguity about the source of an NMI. Enumerate NMI-source reporting in cpufeatures. Also, since NMI-source reporting uses the FRED event dispatch framework, make it dependent on FRED in the CPUID dependency table. This ensures that NMI-source reporting gets disabled when FRED is disabled. NMI-source reporting is intended as a kernel feature and does not need userspace enumeration or configuration. There is no need to expose it to userspace through /proc/cpuinfo. Originally-by: Jacob Pan Signed-off-by: Sohil Mehta --- v6: No change. v5: Add NMI-source to the CPUID dependency table. Do not expose NMI-source feature through /proc/cpuinfo. --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/cpuid-deps.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 6c2c152d8a67..2ced1bc64548 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -321,6 +321,7 @@ #define X86_FEATURE_FRED (12*32+17) /* "fred" Flexible Return and Event D= elivery */ #define X86_FEATURE_LKGS (12*32+18) /* Load "kernel" (userspace) GS */ #define X86_FEATURE_WRMSRNS (12*32+19) /* Non-serializing WRMSR */ +#define X86_FEATURE_NMI_SOURCE (12*32+20) /* NMI-Source reporting with FR= ED */ #define X86_FEATURE_AMX_FP16 (12*32+21) /* AMX fp16 Support */ #define X86_FEATURE_AVX_IFMA (12*32+23) /* Support for VPMADD52= [H,L]UQ */ #define X86_FEATURE_LAM (12*32+26) /* "lam" Linear Address Masking */ diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-d= eps.c index a2fbea0be535..ed0fd35c9290 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -84,6 +84,7 @@ static const struct cpuid_dep cpuid_deps[] =3D { { X86_FEATURE_AMX_TILE, X86_FEATURE_XFD }, { X86_FEATURE_SHSTK, X86_FEATURE_XSAVES }, { X86_FEATURE_FRED, X86_FEATURE_LKGS }, + { X86_FEATURE_NMI_SOURCE, X86_FEATURE_FRED }, {} }; =20 --=20 2.43.0 From nobody Sun Feb 8 03:32:30 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A89C1F3FD0; Tue, 13 May 2025 20:37:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747168681; cv=none; b=m9fsoiOxyKX1Ze3aorC/tiNjnO67PlUdBBmJLglz8M3OCG06EeIKqQWQzlhfZvbogSNlHpcqnPnL/OgBiSyAYqrZ/7ZDCf6hWQNy51s/JuwjRy12vM7KN6rMx9K4n5SgrNFzO3tQL+d8iqZPGSeTHaqNVl+yHe0ftTVV/w1X7II= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747168681; c=relaxed/simple; bh=bf4f0FtErss0et6pnp0FJf7srNyY2MRbqPiZKdJRnTI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CxjFI57nxk3U/WS1LksxPjx0IlSeNYytd41L9eTOx0Zmi7mnM+8tU/q2DbABSS1mP78QMeevdsOptYdSnT5M3hrHdAuCK1Rq9N34islWhf3geGblibOtbZogLh2b7n0ih6wKve3gKQSKUA5NI6UG+1wpxhgnUshuhzgfgcGgQRU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=JE01mFch; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="JE01mFch" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1747168679; x=1778704679; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bf4f0FtErss0et6pnp0FJf7srNyY2MRbqPiZKdJRnTI=; b=JE01mFchDDsEb7Jgd72qw/mV2l08ZVhR2Qk78St/57AMXx+1AoyLbbSq EGLT/7jFY2Yx8CUViwOUCmiTR5lRNrr+qQXDYz58UtZNN2C7x/vjxNhLE ZzalUeRDP+miZmbFDmm4v8sg8uC/w0GRKYtmcccnL9K+h1Ttg43s+Tvvf /4smuXYW8Tuivm2jg8jG4zwbJFi5YxWckEtGPDwnWDiCgZuWqgt5+yeMH iflt7c8vZHfM9Jl23Y9UW1Pp357q35G2KAzwYXl9gIEB/TUaLGQUuYt7D zvZe0iStyhEJ3pjCBFhLCf6xBhua4GsooByLk6NHCrADZUPoGVjtE49e+ w==; X-CSE-ConnectionGUID: 7uRMoZjGRL6bBA9ZgS3bVQ== X-CSE-MsgGUID: Os+mriFyQbqJAnPAfqclug== X-IronPort-AV: E=McAfee;i="6700,10204,11432"; a="49160423" X-IronPort-AV: E=Sophos;i="6.15,286,1739865600"; d="scan'208";a="49160423" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2025 13:37:57 -0700 X-CSE-ConnectionGUID: Ttt9udV+ROufOEwJY9P0VA== X-CSE-MsgGUID: gc+tCI4lRJuPJsW+uHIbkA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,286,1739865600"; d="scan'208";a="138241721" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa008.fm.intel.com with ESMTP; 13 May 2025 13:37:57 -0700 From: Sohil Mehta To: x86@kernel.org, linux-kernel@vger.kernel.org Cc: Xin Li , "H . Peter Anvin" , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , Peter Zijlstra , Sean Christopherson , Adrian Hunter , Kan Liang , Tony Luck , Zhang Rui , Steven Rostedt , Sohil Mehta , Andrew Cooper , "Kirill A . Shutemov" , Jacob Pan , Andi Kleen , Kai Huang , Sandipan Das , linux-perf-users@vger.kernel.org, linux-edac@vger.kernel.org, kvm@vger.kernel.org, linux-pm@vger.kernel.org, linux-trace-kernel@vger.kernel.org Subject: [PATCH v6 3/9] x86/nmi: Extend the registration interface to include the NMI-source vector Date: Tue, 13 May 2025 13:37:57 -0700 Message-ID: <20250513203803.2636561-4-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513203803.2636561-1-sohil.mehta@intel.com> References: <20250513203803.2636561-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To prepare for NMI-source reporting, add a source vector argument to the NMI handler registration interface. Later, this will be used to register NMI handlers with a unique source vector that can be used to identify the originator of the NMI. For now, just extend the interface and pass zero as the source vector for all handlers. No functional change intended. Originally-by: Jacob Pan Signed-off-by: Sohil Mehta Reviewed-by: Xin Li (Intel) --- v6: No change. v5: Split the patch into two parts. This one only extends the interface. --- arch/x86/events/amd/ibs.c | 2 +- arch/x86/events/core.c | 2 +- arch/x86/include/asm/nmi.h | 5 ++++- arch/x86/kernel/apic/hw_nmi.c | 3 +-- arch/x86/kernel/cpu/mce/inject.c | 2 +- arch/x86/kernel/cpu/mshyperv.c | 3 +-- arch/x86/kernel/kgdb.c | 6 ++---- arch/x86/kernel/nmi_selftest.c | 7 +++---- arch/x86/kernel/smp.c | 4 ++-- arch/x86/platform/uv/uv_nmi.c | 4 ++-- drivers/acpi/apei/ghes.c | 2 +- drivers/char/ipmi/ipmi_watchdog.c | 3 +-- drivers/edac/igen6_edac.c | 3 +-- drivers/watchdog/hpwdt.c | 6 +++--- 14 files changed, 24 insertions(+), 28 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 0252b7ea8bca..45dece8bee84 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -1486,7 +1486,7 @@ static __init int perf_event_ibs_init(void) if (ret) goto err_op; =20 - ret =3D register_nmi_handler(NMI_LOCAL, perf_ibs_nmi_handler, 0, "perf_ib= s"); + ret =3D register_nmi_handler(NMI_LOCAL, perf_ibs_nmi_handler, 0, "perf_ib= s", 0); if (ret) goto err_nmi; =20 diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 6866cc5acb0b..b84b8be1f075 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -2115,7 +2115,7 @@ static int __init init_hw_perf_events(void) x86_pmu.config_mask =3D X86_RAW_EVENT_MASK; =20 perf_events_lapic_init(); - register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI"); + register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI", 0); =20 unconstrained =3D (struct event_constraint) __EVENT_CONSTRAINT(0, x86_pmu.cntr_mask64, diff --git a/arch/x86/include/asm/nmi.h b/arch/x86/include/asm/nmi.h index 79d88d12c8fb..f0a577bf7bba 100644 --- a/arch/x86/include/asm/nmi.h +++ b/arch/x86/include/asm/nmi.h @@ -54,6 +54,7 @@ struct nmiaction { u64 max_duration; unsigned long flags; const char *name; + u8 source_vector; }; =20 /** @@ -62,6 +63,7 @@ struct nmiaction { * @fn: The NMI handler * @fg: Flags associated with the NMI handler * @n: Name of the NMI handler + * @src: NMI-source based vector for the NMI handler * @init: Optional __init* attributes for struct nmiaction * * Adds the provided handler to the list of handlers for the specified @@ -75,13 +77,14 @@ struct nmiaction { * * Return: 0 on success, or an error code on failure. */ -#define register_nmi_handler(t, fn, fg, n, init...) \ +#define register_nmi_handler(t, fn, fg, n, src, init...) \ ({ \ static struct nmiaction init fn##_na =3D { \ .list =3D LIST_HEAD_INIT(fn##_na.list), \ .handler =3D (fn), \ .name =3D (n), \ .flags =3D (fg), \ + .source_vector =3D (src), \ }; \ __register_nmi_handler((t), &fn##_na); \ }) diff --git a/arch/x86/kernel/apic/hw_nmi.c b/arch/x86/kernel/apic/hw_nmi.c index 45af535c44a0..612b77660d05 100644 --- a/arch/x86/kernel/apic/hw_nmi.c +++ b/arch/x86/kernel/apic/hw_nmi.c @@ -53,8 +53,7 @@ NOKPROBE_SYMBOL(nmi_cpu_backtrace_handler); =20 static int __init register_nmi_cpu_backtrace_handler(void) { - register_nmi_handler(NMI_LOCAL, nmi_cpu_backtrace_handler, - 0, "arch_bt"); + register_nmi_handler(NMI_LOCAL, nmi_cpu_backtrace_handler, 0, "arch_bt", = 0); return 0; } early_initcall(register_nmi_cpu_backtrace_handler); diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inj= ect.c index 06e3cf7229ce..17804ba0b02f 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -774,7 +774,7 @@ static int __init inject_init(void) =20 debugfs_init(); =20 - register_nmi_handler(NMI_LOCAL, mce_raise_notify, 0, "mce_notify"); + register_nmi_handler(NMI_LOCAL, mce_raise_notify, 0, "mce_notify", 0); mce_register_injector_chain(&inject_nb); =20 setup_inj_struct(&i_mce); diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c index 3e2533954675..d643d6fb3cfa 100644 --- a/arch/x86/kernel/cpu/mshyperv.c +++ b/arch/x86/kernel/cpu/mshyperv.c @@ -548,8 +548,7 @@ static void __init ms_hyperv_init_platform(void) lapic_timer_period); } =20 - register_nmi_handler(NMI_UNKNOWN, hv_nmi_unknown, NMI_FLAG_FIRST, - "hv_nmi_unknown"); + register_nmi_handler(NMI_UNKNOWN, hv_nmi_unknown, NMI_FLAG_FIRST, "hv_nmi= _unknown", 0); #endif =20 #ifdef CONFIG_X86_IO_APIC diff --git a/arch/x86/kernel/kgdb.c b/arch/x86/kernel/kgdb.c index 9c9faa1634fb..ab2d1b79b79e 100644 --- a/arch/x86/kernel/kgdb.c +++ b/arch/x86/kernel/kgdb.c @@ -602,13 +602,11 @@ int kgdb_arch_init(void) if (retval) goto out; =20 - retval =3D register_nmi_handler(NMI_LOCAL, kgdb_nmi_handler, - 0, "kgdb"); + retval =3D register_nmi_handler(NMI_LOCAL, kgdb_nmi_handler, 0, "kgdb", 0= ); if (retval) goto out1; =20 - retval =3D register_nmi_handler(NMI_UNKNOWN, kgdb_nmi_handler, - 0, "kgdb"); + retval =3D register_nmi_handler(NMI_UNKNOWN, kgdb_nmi_handler, 0, "kgdb",= 0); =20 if (retval) goto out2; diff --git a/arch/x86/kernel/nmi_selftest.c b/arch/x86/kernel/nmi_selftest.c index a010e9d062bf..b203e4371816 100644 --- a/arch/x86/kernel/nmi_selftest.c +++ b/arch/x86/kernel/nmi_selftest.c @@ -40,8 +40,7 @@ static int __init nmi_unk_cb(unsigned int val, struct pt_= regs *regs) static void __init init_nmi_testsuite(void) { /* trap all the unknown NMIs we may generate */ - register_nmi_handler(NMI_UNKNOWN, nmi_unk_cb, 0, "nmi_selftest_unk", - __initdata); + register_nmi_handler(NMI_UNKNOWN, nmi_unk_cb, 0, "nmi_selftest_unk", 0, _= _initdata); } =20 static void __init cleanup_nmi_testsuite(void) @@ -63,8 +62,8 @@ static void __init test_nmi_ipi(struct cpumask *mask) { unsigned long timeout; =20 - if (register_nmi_handler(NMI_LOCAL, test_nmi_ipi_callback, - NMI_FLAG_FIRST, "nmi_selftest", __initdata)) { + if (register_nmi_handler(NMI_LOCAL, test_nmi_ipi_callback, NMI_FLAG_FIRST, + "nmi_selftest", 0, __initdata)) { nmi_fail =3D FAILURE; return; } diff --git a/arch/x86/kernel/smp.c b/arch/x86/kernel/smp.c index 18266cc3d98c..b80812aa06c3 100644 --- a/arch/x86/kernel/smp.c +++ b/arch/x86/kernel/smp.c @@ -142,8 +142,8 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_reboot) =20 static int register_stop_handler(void) { - return register_nmi_handler(NMI_LOCAL, smp_stop_nmi_callback, - NMI_FLAG_FIRST, "smp_stop"); + return register_nmi_handler(NMI_LOCAL, smp_stop_nmi_callback, NMI_FLAG_FI= RST, "smp_stop", + 0); } =20 static void native_stop_other_cpus(int wait) diff --git a/arch/x86/platform/uv/uv_nmi.c b/arch/x86/platform/uv/uv_nmi.c index 5c50e550ab63..473c34eb264c 100644 --- a/arch/x86/platform/uv/uv_nmi.c +++ b/arch/x86/platform/uv/uv_nmi.c @@ -1029,10 +1029,10 @@ static int uv_handle_nmi_ping(unsigned int reason, = struct pt_regs *regs) =20 static void uv_register_nmi_notifier(void) { - if (register_nmi_handler(NMI_UNKNOWN, uv_handle_nmi, 0, "uv")) + if (register_nmi_handler(NMI_UNKNOWN, uv_handle_nmi, 0, "uv", 0)) pr_warn("UV: NMI handler failed to register\n"); =20 - if (register_nmi_handler(NMI_LOCAL, uv_handle_nmi_ping, 0, "uvping")) + if (register_nmi_handler(NMI_LOCAL, uv_handle_nmi_ping, 0, "uvping", 0)) pr_warn("UV: PING NMI handler failed to register\n"); } =20 diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index b72772494655..95bd3a64608f 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -1318,7 +1318,7 @@ static void ghes_nmi_add(struct ghes *ghes) { mutex_lock(&ghes_list_mutex); if (list_empty(&ghes_nmi)) - register_nmi_handler(NMI_LOCAL, ghes_notify_nmi, 0, "ghes"); + register_nmi_handler(NMI_LOCAL, ghes_notify_nmi, 0, "ghes", 0); list_add_rcu(&ghes->list, &ghes_nmi); mutex_unlock(&ghes_list_mutex); } diff --git a/drivers/char/ipmi/ipmi_watchdog.c b/drivers/char/ipmi/ipmi_wat= chdog.c index f1875b2bebbc..5db402c4b9e7 100644 --- a/drivers/char/ipmi/ipmi_watchdog.c +++ b/drivers/char/ipmi/ipmi_watchdog.c @@ -1267,8 +1267,7 @@ static void check_parms(void) } } if (do_nmi && !nmi_handler_registered) { - rv =3D register_nmi_handler(NMI_UNKNOWN, ipmi_nmi, 0, - "ipmi"); + rv =3D register_nmi_handler(NMI_UNKNOWN, ipmi_nmi, 0, "ipmi", 0); if (rv) { pr_warn("Can't register nmi handler\n"); return; diff --git a/drivers/edac/igen6_edac.c b/drivers/edac/igen6_edac.c index 5807517ee32d..3a6e7334e94c 100644 --- a/drivers/edac/igen6_edac.c +++ b/drivers/edac/igen6_edac.c @@ -1363,8 +1363,7 @@ static int register_err_handler(void) return 0; } =20 - rc =3D register_nmi_handler(NMI_SERR, ecclog_nmi_handler, - 0, IGEN6_NMI_NAME); + rc =3D register_nmi_handler(NMI_SERR, ecclog_nmi_handler, 0, IGEN6_NMI_NA= ME, 0); if (rc) { igen6_printk(KERN_ERR, "Failed to register NMI handler\n"); return rc; diff --git a/drivers/watchdog/hpwdt.c b/drivers/watchdog/hpwdt.c index ae30e394d176..5246706afcf6 100644 --- a/drivers/watchdog/hpwdt.c +++ b/drivers/watchdog/hpwdt.c @@ -242,13 +242,13 @@ static int hpwdt_init_nmi_decoding(struct pci_dev *de= v) /* * Only one function can register for NMI_UNKNOWN */ - retval =3D register_nmi_handler(NMI_UNKNOWN, hpwdt_pretimeout, 0, "hpwdt"= ); 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d="scan'208";a="138241724" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa008.fm.intel.com with ESMTP; 13 May 2025 13:37:57 -0700 From: Sohil Mehta To: x86@kernel.org, linux-kernel@vger.kernel.org Cc: Xin Li , "H . Peter Anvin" , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , Peter Zijlstra , Sean Christopherson , Adrian Hunter , Kan Liang , Tony Luck , Zhang Rui , Steven Rostedt , Sohil Mehta , Andrew Cooper , "Kirill A . Shutemov" , Jacob Pan , Andi Kleen , Kai Huang , Sandipan Das , linux-perf-users@vger.kernel.org, linux-edac@vger.kernel.org, kvm@vger.kernel.org, linux-pm@vger.kernel.org, linux-trace-kernel@vger.kernel.org Subject: [PATCH v6 4/9] x86/nmi: Assign and register NMI-source vectors Date: Tue, 13 May 2025 13:37:58 -0700 Message-ID: <20250513203803.2636561-5-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513203803.2636561-1-sohil.mehta@intel.com> References: <20250513203803.2636561-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Prior to NMI-source support, the vector information was ignored by the hardware while delivering NMIs. With NMI-source, the architecture currently supports a 16-bit source bitmap to identify the source of the NMI. Upon receiving an NMI, this bitmap is delivered as part of the FRED event delivery mechanism to the kernel. Assign a vector space of 0-15 that is specific to NMI-source and independent of the IDT vector space of 0-255. Being a bitmap, the NMI-source vectors do not have any inherent priority associated with them. The order of executing the NMI handlers is up to the kernel. Existing NMI handling already has a priority mechanism for the NMI handlers, with CPU-specific (NMI_LOCAL) handlers executed first, followed by platform NMI handlers and unknown NMI (NMI_UNKNOWN) handlers being last. Within each of these NMI types, the handlers registered with NMI_FLAG_FIRST are given priority. NMI-source follows the same priority scheme to avoid unnecessary complexity. Therefore, the NMI-source vectors are assigned arbitrarily, except for vectors 0 and 2. Vector 0 is set by the hardware whenever a source vector was not used while generating an NMI or the originator could not be reliably identified. Do not assign it to any handler. Vector 2 is reserved for external NMIs corresponding to Local APIC - LINT1. Some third-party chipsets may send NMI messages with a hardcoded vector of 2, which would result in vector 2 being set in the NMI-source bitmap. To avoid confusion, do not assign vector 2 to any handler. NMI-source vectors are only assigned for NMI_LOCAL type handlers. Platform NMI handlers have a single handler registered per type. They don't need additional source information to differentiate among them. Use the assigned vectors to register the respective NMI handlers. Warn if the vector values are unexpected. A couple of NMI handlers, such as the microcode rendezvous and the crash reboot, do not use the typical NMI registration interface. Leave them as-is for now. Originally-by: Jacob Pan Signed-off-by: Sohil Mehta Reviewed-by: Xin Li (Intel) --- v6: Store source vector unconditionally. Add a warning for unexpected source vector values. v5: Move the vector defines to nmi.h. Combine vector allocation and registration into one patch. Simplify NMI vector names. Describe usage of vector 2 for external NMIs. Get rid of vector priorities. --- arch/x86/events/core.c | 2 +- arch/x86/include/asm/nmi.h | 32 ++++++++++++++++++++++++++++++++ arch/x86/kernel/apic/hw_nmi.c | 2 +- arch/x86/kernel/cpu/mce/inject.c | 2 +- arch/x86/kernel/kgdb.c | 2 +- arch/x86/kernel/nmi.c | 4 ++++ arch/x86/kernel/nmi_selftest.c | 2 +- arch/x86/kernel/smp.c | 2 +- 8 files changed, 42 insertions(+), 6 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index b84b8be1f075..031e908f0d61 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -2115,7 +2115,7 @@ static int __init init_hw_perf_events(void) x86_pmu.config_mask =3D X86_RAW_EVENT_MASK; =20 perf_events_lapic_init(); - register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI", 0); + register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI", NMIS_VE= CTOR_PMI); =20 unconstrained =3D (struct event_constraint) __EVENT_CONSTRAINT(0, x86_pmu.cntr_mask64, diff --git a/arch/x86/include/asm/nmi.h b/arch/x86/include/asm/nmi.h index f0a577bf7bba..b9beb216f2d0 100644 --- a/arch/x86/include/asm/nmi.h +++ b/arch/x86/include/asm/nmi.h @@ -57,6 +57,38 @@ struct nmiaction { u8 source_vector; }; =20 +/** + * NMI-source vectors are used to identify the origin of an NMI and to + * route the NMI directly to the appropriate handler. + * + * On CPUs that support NMI-source reporting with FRED, receiving an NMI + * with a valid vector sets the corresponding bit in the NMI-source + * bitmap. The bitmap is delivered as FRED event data on the stack. + * Multiple NMIs are coalesced in the NMI-source bitmap until the next + * NMI delivery. + * + * If an NMI is received without a vector or beyond the defined range, + * the CPU sets bit 0 of the NMI-source bitmap. + * + * Vector 2 is reserved for external NMIs related to the Local APIC - + * LINT1. Some third-party chipsets may send NMI messages with a + * hardcoded vector of 2, which would result in bit 2 being set in the + * NMI-source bitmap. + * + * The vectors are in no particular priority order. Add new vector + * assignments sequentially in the list below. + */ +#define NMIS_VECTOR_NONE 0 /* Reserved - Set for all unidentified sources = */ +#define NMIS_VECTOR_TEST 1 /* NMI selftest */ +#define NMIS_VECTOR_EXTERNAL 2 /* Reserved - Match External NMI vector 2 */ +#define NMIS_VECTOR_SMP_STOP 3 /* Panic stop CPU */ +#define NMIS_VECTOR_BT 4 /* CPU backtrace */ +#define NMIS_VECTOR_KGDB 5 /* Kernel debugger */ +#define NMIS_VECTOR_MCE 6 /* MCE injection */ +#define NMIS_VECTOR_PMI 7 /* PerfMon counters */ + +#define NMIS_VECTORS_MAX 16 /* Maximum number of NMI-source vectors */ + /** * register_nmi_handler - Register a handler for a specific NMI type * @t: NMI type (e.g. NMI_LOCAL) diff --git a/arch/x86/kernel/apic/hw_nmi.c b/arch/x86/kernel/apic/hw_nmi.c index 612b77660d05..4e04f13d2de9 100644 --- a/arch/x86/kernel/apic/hw_nmi.c +++ b/arch/x86/kernel/apic/hw_nmi.c @@ -53,7 +53,7 @@ NOKPROBE_SYMBOL(nmi_cpu_backtrace_handler); =20 static int __init register_nmi_cpu_backtrace_handler(void) { - register_nmi_handler(NMI_LOCAL, nmi_cpu_backtrace_handler, 0, "arch_bt", = 0); + register_nmi_handler(NMI_LOCAL, nmi_cpu_backtrace_handler, 0, "arch_bt", = NMIS_VECTOR_BT); return 0; } early_initcall(register_nmi_cpu_backtrace_handler); diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inj= ect.c index 17804ba0b02f..a3c753dfce91 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -774,7 +774,7 @@ static int __init inject_init(void) =20 debugfs_init(); =20 - register_nmi_handler(NMI_LOCAL, mce_raise_notify, 0, "mce_notify", 0); + register_nmi_handler(NMI_LOCAL, mce_raise_notify, 0, "mce_notify", NMIS_V= ECTOR_MCE); mce_register_injector_chain(&inject_nb); =20 setup_inj_struct(&i_mce); diff --git a/arch/x86/kernel/kgdb.c b/arch/x86/kernel/kgdb.c index ab2d1b79b79e..9ca4b141da0c 100644 --- a/arch/x86/kernel/kgdb.c +++ b/arch/x86/kernel/kgdb.c @@ -602,7 +602,7 @@ int kgdb_arch_init(void) if (retval) goto out; =20 - retval =3D register_nmi_handler(NMI_LOCAL, kgdb_nmi_handler, 0, "kgdb", 0= ); + retval =3D register_nmi_handler(NMI_LOCAL, kgdb_nmi_handler, 0, "kgdb", N= MIS_VECTOR_KGDB); if (retval) goto out1; =20 diff --git a/arch/x86/kernel/nmi.c b/arch/x86/kernel/nmi.c index be93ec7255bf..1a24e8df1bdf 100644 --- a/arch/x86/kernel/nmi.c +++ b/arch/x86/kernel/nmi.c @@ -182,6 +182,10 @@ int __register_nmi_handler(unsigned int type, struct n= miaction *action) if (WARN_ON_ONCE(!action->handler || !list_empty(&action->list))) return -EINVAL; =20 + /* NMI-source reporting should only be used for NMI_LOCAL */ + WARN_ON_ONCE(type !=3D NMI_LOCAL && action->source_vector); + WARN_ON_ONCE(action->source_vector >=3D NMIS_VECTORS_MAX); + raw_spin_lock_irqsave(&desc->lock, flags); =20 /* diff --git a/arch/x86/kernel/nmi_selftest.c b/arch/x86/kernel/nmi_selftest.c index b203e4371816..5196023b31dc 100644 --- a/arch/x86/kernel/nmi_selftest.c +++ b/arch/x86/kernel/nmi_selftest.c @@ -63,7 +63,7 @@ static void __init test_nmi_ipi(struct cpumask *mask) unsigned long timeout; =20 if (register_nmi_handler(NMI_LOCAL, test_nmi_ipi_callback, NMI_FLAG_FIRST, - "nmi_selftest", 0, __initdata)) { + "nmi_selftest", NMIS_VECTOR_TEST, __initdata)) { nmi_fail =3D FAILURE; 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d="scan'208";a="138241727" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa008.fm.intel.com with ESMTP; 13 May 2025 13:37:58 -0700 From: Sohil Mehta To: x86@kernel.org, linux-kernel@vger.kernel.org Cc: Xin Li , "H . Peter Anvin" , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , Peter Zijlstra , Sean Christopherson , Adrian Hunter , Kan Liang , Tony Luck , Zhang Rui , Steven Rostedt , Sohil Mehta , Andrew Cooper , "Kirill A . Shutemov" , Jacob Pan , Andi Kleen , Kai Huang , Sandipan Das , linux-perf-users@vger.kernel.org, linux-edac@vger.kernel.org, kvm@vger.kernel.org, linux-pm@vger.kernel.org, linux-trace-kernel@vger.kernel.org Subject: [PATCH v6 5/9] x86/nmi: Add support to handle NMIs with source information Date: Tue, 13 May 2025 13:37:59 -0700 Message-ID: <20250513203803.2636561-6-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513203803.2636561-1-sohil.mehta@intel.com> References: <20250513203803.2636561-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The NMI-source bitmap is delivered as FRED event data to the kernel. When available, use NMI-source based filtering to determine the exact handlers to run. Activate NMI-source based filtering only for Local NMIs. While handling platform NMI types (such as SERR and IOCHK), do not use the source bitmap. They have only one handler registered per type, so there is no need to disambiguate between multiple handlers. Some third-party chipsets may send NMI messages with a hardcoded vector of 2, which would result in bit 2 being set in the NMI-source bitmap. Skip the local NMI handlers in this situation. Bit 0 of the source bitmap is set by the hardware whenever a source vector was not used while generating an NMI, or the originator could not be reliably identified. Poll all the registered handlers in that case. When multiple handlers need to be executed, adhere to the existing priority scheme and execute the handlers registered with NMI_FLAG_FIRST before others. The logic for handling legacy NMIs is unaffected since the source bitmap would always have all bits set. Suggested-by: Peter Zijlstra (Intel) Signed-off-by: Sohil Mehta Reviewed-by: Xin Li (Intel) --- v6: Get rid of a separate NMI source matching function Set source_bitmap to ULONG_MAX to match all sources by default v5: Significantly simplify NMI-source handling logic. Get rid of a separate lookup table for NMI-source vectors. Adhere to existing priority scheme for handling NMIs. --- arch/x86/kernel/nmi.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/x86/kernel/nmi.c b/arch/x86/kernel/nmi.c index 1a24e8df1bdf..55ecbe2ab5e4 100644 --- a/arch/x86/kernel/nmi.c +++ b/arch/x86/kernel/nmi.c @@ -130,6 +130,7 @@ static void nmi_check_duration(struct nmiaction *action= , u64 duration) static int nmi_handle(unsigned int type, struct pt_regs *regs) { struct nmi_desc *desc =3D nmi_to_desc(type); + unsigned long source_bitmap =3D ULONG_MAX; nmi_handler_t ehandler; struct nmiaction *a; int handled=3D0; @@ -148,16 +149,45 @@ static int nmi_handle(unsigned int type, struct pt_re= gs *regs) =20 rcu_read_lock(); =20 + /* + * Activate NMI source-based filtering only for Local NMIs. + * + * Platform NMI types (such as SERR and IOCHK) have only one + * handler registered per type, so there is no need to + * disambiguate between multiple handlers. + * + * Also, if a platform source ends up setting bit 2 in the + * source bitmap, the local NMI handlers would be skipped since + * none of them use this reserved vector. + * + * For Unknown NMIs, avoid using the source bitmap to ensure all + * potential handlers have a chance to claim responsibility. + */ + if (cpu_feature_enabled(X86_FEATURE_NMI_SOURCE) && type =3D=3D NMI_LOCAL)= { + source_bitmap =3D fred_event_data(regs); + + /* Reset the bitmap if a valid source could not be identified */ + if (WARN_ON_ONCE(!source_bitmap) || (source_bitmap & BIT(NMIS_VECTOR_NON= E))) + source_bitmap =3D ULONG_MAX; + } + /* * NMIs are edge-triggered, which means if you have enough * of them concurrently, you can lose some because only one * can be latched at any given time. Walk the whole list * to handle those situations. + * + * However, NMI-source reporting does not have this limitation. + * When NMI sources have been identified, only run the handlers + * that match the reported vectors. */ list_for_each_entry_rcu(a, &desc->head, list) { int thishandled; u64 delta; =20 + if (!(source_bitmap & BIT(a->source_vector))) + continue; + delta =3D sched_clock(); thishandled =3D a->handler(type, regs); handled +=3D thishandled; --=20 2.43.0 From nobody Sun Feb 8 03:32:30 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CDF62C0855; Tue, 13 May 2025 20:38:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747168683; cv=none; b=KNJB61Tcm3Bb3aRxppW8SF/3amLW1mq+GOW0AlO261hBzRaqY1OdUNp74+nPK7nVjrunZ28lyjwRyLLqbEPHiZUrDkRisrrKmYKX2RN7gPriHiHNgl/KrvTuXOWW4y7wrHb307z5PXAAZQv5LtdG96o3umBReruoWGLtRqtxxY8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747168683; c=relaxed/simple; bh=m0ZR3/bQ3E+JuoyEu/DfKBk7bwXzCT0Cr8UiXvTRaCk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mse8gahMRvt7bg9tQaPmX2I1yAl/532Tl3JlS4zBkxzJEpPOLs/6DyzBHR/33M1LReSKGPEP7qPB51wDP265mSFkYAtTGzLiJEowrvOWbI7vPXrAjt7EECz4wyXI8wzEf7szUoj6SAsYPbG4d6KNZvIS1IgjhU/EZicQLz5Cq/0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Pt3QOmBE; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Pt3QOmBE" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1747168682; x=1778704682; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=m0ZR3/bQ3E+JuoyEu/DfKBk7bwXzCT0Cr8UiXvTRaCk=; b=Pt3QOmBERNpLjSMKyqHbbtEz9NLKlgLGUTqTHoPsynI5SKiQ/BfwBZaR EE1DV5MK5dPSsZpakI7Si8lZ/W0RZZjtrnIBFYPEqjV2f0WMgKdPj4fVw djzQUvicvDPYl8p0P3hoBTGpFWdzQ4BK/wukJN8v9OR1pZUITMby58A7L TuYNldYO16onwlp1v+bnQ0ap5nGyxBV6NIIeK3Io1Aw3m5rY5m8Cp2Ly7 oe2MIoj+QrYJIwvt/WlzYIQu5Td49MVZuxTbZH6cAuGAjt1NmVFcwVBY6 NNlCKc5faBFra1KYvhCUfgHxuKrRnHUwKPXhEabk89nj60PWY74j96A0h Q==; X-CSE-ConnectionGUID: /vsVIvsQTfO+JoG9DOFFnA== X-CSE-MsgGUID: ePRd51avQXCXWSybPakMXA== X-IronPort-AV: E=McAfee;i="6700,10204,11432"; a="49160462" X-IronPort-AV: E=Sophos;i="6.15,286,1739865600"; d="scan'208";a="49160462" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2025 13:37:59 -0700 X-CSE-ConnectionGUID: XPiyi2ceQZ2ILAxN8vwo7w== X-CSE-MsgGUID: 43jYiV4FRyaygWMzyxlIRA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,286,1739865600"; d="scan'208";a="138241730" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa008.fm.intel.com with ESMTP; 13 May 2025 13:37:58 -0700 From: Sohil Mehta To: x86@kernel.org, linux-kernel@vger.kernel.org Cc: Xin Li , "H . Peter Anvin" , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , Peter Zijlstra , Sean Christopherson , Adrian Hunter , Kan Liang , Tony Luck , Zhang Rui , Steven Rostedt , Sohil Mehta , Andrew Cooper , "Kirill A . Shutemov" , Jacob Pan , Andi Kleen , Kai Huang , Sandipan Das , linux-perf-users@vger.kernel.org, linux-edac@vger.kernel.org, kvm@vger.kernel.org, linux-pm@vger.kernel.org, linux-trace-kernel@vger.kernel.org Subject: [PATCH v6 6/9] x86/nmi: Prepare for the new NMI-source vector encoding Date: Tue, 13 May 2025 13:38:00 -0700 Message-ID: <20250513203803.2636561-7-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513203803.2636561-1-sohil.mehta@intel.com> References: <20250513203803.2636561-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When using the send_IPI_* APIC calls, callers typically use NMI vector 0x2 to trigger NMIs. The APIC APIs convert the NMI vector to the NMI delivery mode, which is eventually used to program the APIC. Before FRED, the hardware would ignore the vector used with NMI delivery mode. However, with NMI-source reporting, the vector information is relayed to the destination CPU, which sets the corresponding bit in the NMI-source bitmap. Unfortunately, the kernel now needs to maintain a new set of NMI vectors and differentiate them from the IDT vectors. Instead of creating a parallel set of send_NMI_* APIs to handle NMI-source vectors, enhance the existing send_IPI_* APIs with a new encoding scheme to handle the NMI delivery mode along with the NMI-source vector. NMI-source vectors would be encoded as: APIC_DM_NMI (0x400) | NMI_SOURCE_VECTOR (0x1-0xF) Also, introduce a helper to prepare the ICR value with the encoded delivery mode and vector. Update the guest paravirtual APIC code to use the new helper as well. While at it, rename APIC_DM_FIXED_MASK to the more appropriate APIC_DM_MASK. Suggested-by: Sean Christopherson Co-developed-by: Xin Li (Intel) Signed-off-by: Xin Li (Intel) Signed-off-by: Sohil Mehta --- v6: Remove a redundant else statement. v5: Use a simiplified encoding scheme for NMI-source vectors. --- arch/x86/include/asm/apic.h | 30 +++++++++++++++++++++++++++++ arch/x86/include/asm/apicdef.h | 2 +- arch/x86/kernel/apic/ipi.c | 4 ++-- arch/x86/kernel/apic/local.h | 24 ++++++++++++----------- arch/x86/kernel/kvm.c | 9 +-------- drivers/thermal/intel/therm_throt.c | 2 +- 6 files changed, 48 insertions(+), 23 deletions(-) diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index c903d358405d..9c3d5932d591 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -470,6 +470,36 @@ static __always_inline bool apic_id_valid(u32 apic_id) return apic_id <=3D apic->max_apic_id; } =20 +/* + * Prepare the delivery mode and vector for the ICR. + * + * NMI-source vectors have the NMI delivery mode encoded within them to + * differentiate them from the IDT vectors. IDT vector 0x2 (NMI_VECTOR) + * is treated as an NMI request but without any NMI-source information. + */ +static inline u16 __prepare_ICR_DM_vector(u16 dm_vector) +{ + u16 vector =3D dm_vector & APIC_VECTOR_MASK; + u16 dm =3D dm_vector & APIC_DM_MASK; + + if (dm =3D=3D APIC_DM_NMI) { + /* + * Pre-FRED, the actual vector is ignored for NMIs, but + * zero it if NMI-source reporting is not supported to + * avoid breakage on misbehaving hardware or hypervisors. + */ + if (!cpu_feature_enabled(X86_FEATURE_NMI_SOURCE)) + vector =3D 0; + + return dm | vector; + } + + if (vector =3D=3D NMI_VECTOR) + return APIC_DM_NMI; + + return APIC_DM_FIXED | vector; +} + #else /* CONFIG_X86_LOCAL_APIC */ =20 static inline u32 apic_read(u32 reg) { return 0; } diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h index 094106b6a538..3fb8fa73f6aa 100644 --- a/arch/x86/include/asm/apicdef.h +++ b/arch/x86/include/asm/apicdef.h @@ -87,8 +87,8 @@ #define APIC_ICR_BUSY 0x01000 #define APIC_DEST_LOGICAL 0x00800 #define APIC_DEST_PHYSICAL 0x00000 +#define APIC_DM_MASK 0x00700 #define APIC_DM_FIXED 0x00000 -#define APIC_DM_FIXED_MASK 0x00700 #define APIC_DM_LOWEST 0x00100 #define APIC_DM_SMI 0x00200 #define APIC_DM_REMRD 0x00300 diff --git a/arch/x86/kernel/apic/ipi.c b/arch/x86/kernel/apic/ipi.c index 98a57cb4aa86..4e8bc42f3bd5 100644 --- a/arch/x86/kernel/apic/ipi.c +++ b/arch/x86/kernel/apic/ipi.c @@ -158,7 +158,7 @@ static void __default_send_IPI_shortcut(unsigned int sh= ortcut, int vector) * issues where otherwise the system hangs when the panic CPU tries * to stop the others before launching the kdump kernel. */ - if (unlikely(vector =3D=3D NMI_VECTOR)) + if (unlikely(is_nmi_vector(vector))) apic_mem_wait_icr_idle_timeout(); else apic_mem_wait_icr_idle(); @@ -175,7 +175,7 @@ void __default_send_IPI_dest_field(unsigned int dest_ma= sk, int vector, unsigned int dest_mode) { /* See comment in __default_send_IPI_shortcut() */ - if (unlikely(vector =3D=3D NMI_VECTOR)) + if (unlikely(is_nmi_vector(vector))) apic_mem_wait_icr_idle_timeout(); else apic_mem_wait_icr_idle(); diff --git a/arch/x86/kernel/apic/local.h b/arch/x86/kernel/apic/local.h index bdcf609eb283..9a54c589a4bf 100644 --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -24,22 +24,24 @@ extern u32 x2apic_max_apicid; =20 /* IPI */ =20 +u16 __prepare_ICR_DM_vector(u16 vector); + DECLARE_STATIC_KEY_FALSE(apic_use_ipi_shorthand); =20 +/* NMI-source vectors have the delivery mode encoded within them */ +static inline bool is_nmi_vector(u16 vector) +{ + if ((vector & APIC_DM_MASK) =3D=3D APIC_DM_NMI) + return true; + if ((vector & APIC_VECTOR_MASK) =3D=3D NMI_VECTOR) + return true; + return false; +} + static inline unsigned int __prepare_ICR(unsigned int shortcut, int vector, unsigned int dest) { - unsigned int icr =3D shortcut | dest; - - switch (vector) { - default: - icr |=3D APIC_DM_FIXED | vector; - break; - case NMI_VECTOR: - icr |=3D APIC_DM_NMI; - break; - } - return icr; + return shortcut | dest | __prepare_ICR_DM_vector(vector); } =20 void default_init_apic_ldr(void); diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c index 3be9b3342c67..aa45fe4fecd0 100644 --- a/arch/x86/kernel/kvm.c +++ b/arch/x86/kernel/kvm.c @@ -517,14 +517,7 @@ static void __send_ipi_mask(const struct cpumask *mask= , int vector) =20 local_irq_save(flags); =20 - switch (vector) { - default: - icr =3D APIC_DM_FIXED | vector; - break; - case NMI_VECTOR: - icr =3D APIC_DM_NMI; - break; - } + icr =3D __prepare_ICR_DM_vector(vector); =20 for_each_cpu(cpu, mask) { apic_id =3D per_cpu(x86_cpu_to_apicid, cpu); diff --git a/drivers/thermal/intel/therm_throt.c b/drivers/thermal/intel/th= erm_throt.c index e69868e868eb..83dd53cb4fc7 100644 --- a/drivers/thermal/intel/therm_throt.c +++ b/drivers/thermal/intel/therm_throt.c @@ -740,7 +740,7 @@ void intel_init_thermal(struct cpuinfo_x86 *c) * BIOS has programmed on AP based on BSP's info we saved since BIOS * is always setting the same value for all threads/cores. */ - if ((h & APIC_DM_FIXED_MASK) !=3D APIC_DM_FIXED) + if ((h & APIC_DM_MASK) !=3D APIC_DM_FIXED) apic_write(APIC_LVTTHMR, lvtthmr_init); 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X-CSE-ConnectionGUID: YZLLzq3mTjOjqhTkHQ8J5w== X-CSE-MsgGUID: HVx6UgARTS64GM6nkYlYgg== X-IronPort-AV: E=McAfee;i="6700,10204,11432"; a="49160474" X-IronPort-AV: E=Sophos;i="6.15,286,1739865600"; d="scan'208";a="49160474" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2025 13:38:00 -0700 X-CSE-ConnectionGUID: LnsfcjOvSLCJQFVQ6UcCKg== X-CSE-MsgGUID: c3Uf+7qEQGarDivPmKTZrg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,286,1739865600"; d="scan'208";a="138241733" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa008.fm.intel.com with ESMTP; 13 May 2025 13:37:59 -0700 From: Sohil Mehta To: x86@kernel.org, linux-kernel@vger.kernel.org Cc: Xin Li , "H . Peter Anvin" , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , Peter Zijlstra , Sean Christopherson , Adrian Hunter , Kan Liang , Tony Luck , Zhang Rui , Steven Rostedt , Sohil Mehta , Andrew Cooper , "Kirill A . Shutemov" , Jacob Pan , Andi Kleen , Kai Huang , Sandipan Das , linux-perf-users@vger.kernel.org, linux-edac@vger.kernel.org, kvm@vger.kernel.org, linux-pm@vger.kernel.org, linux-trace-kernel@vger.kernel.org Subject: [PATCH v6 7/9] x86/nmi: Enable NMI-source for IPIs delivered as NMIs Date: Tue, 13 May 2025 13:38:01 -0700 Message-ID: <20250513203803.2636561-8-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513203803.2636561-1-sohil.mehta@intel.com> References: <20250513203803.2636561-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With the IPI handling APIs ready to support the new NMI encoding, encode the NMI delivery mode directly with the NMI-source vectors to trigger NMIs. Move most of the existing NMI-based IPIs to use the new NMI-source vectors, except for the microcode rendezvous NMI and the crash reboot NMI. NMI handling for them is special-cased in exc_nmi() and does not need NMI-source reporting. However, in the future, it might be useful to assign a source vector to all NMI sources to improve isolation and debuggability. Originally-by: Jacob Pan Suggested-by: Sean Christopherson Co-developed-by: Xin Li (Intel) Signed-off-by: Xin Li (Intel) Signed-off-by: Sohil Mehta --- v6: Include asm/nmi.h to avoid compile errors. (LKP) v5: Encode APIC_DM_NMI directly with the NMI-source vector. --- arch/x86/include/asm/apic.h | 8 ++++++++ arch/x86/kernel/apic/hw_nmi.c | 2 +- arch/x86/kernel/cpu/mce/inject.c | 2 +- arch/x86/kernel/kgdb.c | 2 +- arch/x86/kernel/nmi_selftest.c | 2 +- arch/x86/kernel/smp.c | 2 +- 6 files changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 9c3d5932d591..99033bfb26ea 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -14,6 +14,7 @@ #include #include #include +#include #include =20 #define ARCH_APICTIMER_STOPS_ON_C3 1 @@ -23,6 +24,13 @@ #define APIC_EXTNMI_ALL 1 #define APIC_EXTNMI_NONE 2 =20 +/* Trigger NMIs with source information */ +#define TEST_NMI (APIC_DM_NMI | NMIS_VECTOR_TEST) +#define SMP_STOP_NMI (APIC_DM_NMI | NMIS_VECTOR_SMP_STOP) +#define BT_NMI (APIC_DM_NMI | NMIS_VECTOR_BT) +#define KGDB_NMI (APIC_DM_NMI | NMIS_VECTOR_KGDB) +#define MCE_NMI (APIC_DM_NMI | NMIS_VECTOR_MCE) + /* * Debugging macros */ diff --git a/arch/x86/kernel/apic/hw_nmi.c b/arch/x86/kernel/apic/hw_nmi.c index 4e04f13d2de9..586f4b25feae 100644 --- a/arch/x86/kernel/apic/hw_nmi.c +++ b/arch/x86/kernel/apic/hw_nmi.c @@ -33,7 +33,7 @@ u64 hw_nmi_get_sample_period(int watchdog_thresh) #ifdef arch_trigger_cpumask_backtrace static void nmi_raise_cpu_backtrace(cpumask_t *mask) { - __apic_send_IPI_mask(mask, NMI_VECTOR); + __apic_send_IPI_mask(mask, BT_NMI); } =20 void arch_trigger_cpumask_backtrace(const cpumask_t *mask, int exclude_cpu) diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inj= ect.c index a3c753dfce91..6328a607ffc4 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -269,7 +269,7 @@ static void __maybe_unused raise_mce(struct mce *m) mce_irq_ipi, NULL, 0); preempt_enable(); } else if (m->inject_flags & MCJ_NMI_BROADCAST) - __apic_send_IPI_mask(mce_inject_cpumask, NMI_VECTOR); + __apic_send_IPI_mask(mce_inject_cpumask, MCE_NMI); } start =3D jiffies; while (!cpumask_empty(mce_inject_cpumask)) { diff --git a/arch/x86/kernel/kgdb.c b/arch/x86/kernel/kgdb.c index 9ca4b141da0c..3dedc5f57541 100644 --- a/arch/x86/kernel/kgdb.c +++ b/arch/x86/kernel/kgdb.c @@ -416,7 +416,7 @@ static void kgdb_disable_hw_debug(struct pt_regs *regs) */ void kgdb_roundup_cpus(void) { - apic_send_IPI_allbutself(NMI_VECTOR); + apic_send_IPI_allbutself(KGDB_NMI); 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a="49160486" X-IronPort-AV: E=Sophos;i="6.15,286,1739865600"; d="scan'208";a="49160486" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2025 13:38:00 -0700 X-CSE-ConnectionGUID: UCq+j34SQnyxy4tBG8PDfQ== X-CSE-MsgGUID: VT1VdeJ9T1Sfv0wsLdaadw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,286,1739865600"; d="scan'208";a="138241737" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa008.fm.intel.com with ESMTP; 13 May 2025 13:37:59 -0700 From: Sohil Mehta To: x86@kernel.org, linux-kernel@vger.kernel.org Cc: Xin Li , "H . Peter Anvin" , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , Peter Zijlstra , Sean Christopherson , Adrian Hunter , Kan Liang , Tony Luck , Zhang Rui , Steven Rostedt , Sohil Mehta , Andrew Cooper , "Kirill A . Shutemov" , Jacob Pan , Andi Kleen , Kai Huang , Sandipan Das , linux-perf-users@vger.kernel.org, linux-edac@vger.kernel.org, kvm@vger.kernel.org, linux-pm@vger.kernel.org, linux-trace-kernel@vger.kernel.org Subject: [PATCH v6 8/9] perf/x86: Enable NMI-source reporting for perfmon Date: Tue, 13 May 2025 13:38:02 -0700 Message-ID: <20250513203803.2636561-9-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513203803.2636561-1-sohil.mehta@intel.com> References: <20250513203803.2636561-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jacob Pan Program the designated PMI NMI-source vector into the local vector table for the PMU. An NMI for the PMU would directly invoke the PMI handler without polling other NMI handlers, resulting in reduced PMI delivery latency. Co-developed-by: Zeng Guang Signed-off-by: Zeng Guang Signed-off-by: Jacob Pan Signed-off-by: Sohil Mehta Reviewed-by: Kan Liang Tested-by: Sandipan Das # AMD overlapping bits Reviewed-by: Xin Li (Intel) --- v6: Picked up a tested-by tag. v5: No significant change. --- arch/x86/events/core.c | 4 ++-- arch/x86/events/intel/core.c | 6 +++--- arch/x86/include/asm/apic.h | 1 + 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 031e908f0d61..42b270526631 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -1695,7 +1695,7 @@ int x86_pmu_handle_irq(struct pt_regs *regs) * This generic handler doesn't seem to have any issues where the * unmasking occurs so it was left at the top. */ - apic_write(APIC_LVTPC, APIC_DM_NMI); + apic_write(APIC_LVTPC, PERF_NMI); =20 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { if (!test_bit(idx, cpuc->active_mask)) @@ -1737,7 +1737,7 @@ void perf_events_lapic_init(void) /* * Always use NMI for PMU */ - apic_write(APIC_LVTPC, APIC_DM_NMI); + apic_write(APIC_LVTPC, PERF_NMI); } =20 static int diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 09d2d66c9f21..87c624686c58 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3202,7 +3202,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs) * NMI handler. */ if (!late_ack && !mid_ack) - apic_write(APIC_LVTPC, APIC_DM_NMI); + apic_write(APIC_LVTPC, PERF_NMI); intel_bts_disable_local(); cpuc->enabled =3D 0; __intel_pmu_disable_all(true); @@ -3239,7 +3239,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs) =20 done: if (mid_ack) - apic_write(APIC_LVTPC, APIC_DM_NMI); + apic_write(APIC_LVTPC, PERF_NMI); /* Only restore PMU state when it's active. See x86_pmu_disable(). */ cpuc->enabled =3D pmu_enabled; if (pmu_enabled) @@ -3252,7 +3252,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs) * Haswell CPUs. */ if (late_ack) - apic_write(APIC_LVTPC, APIC_DM_NMI); + apic_write(APIC_LVTPC, PERF_NMI); return handled; } =20 diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 99033bfb26ea..d637717d42bd 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -30,6 +30,7 @@ #define BT_NMI (APIC_DM_NMI | NMIS_VECTOR_BT) #define KGDB_NMI (APIC_DM_NMI | NMIS_VECTOR_KGDB) #define MCE_NMI (APIC_DM_NMI | NMIS_VECTOR_MCE) +#define PERF_NMI (APIC_DM_NMI | NMIS_VECTOR_PMI) =20 /* * Debugging macros --=20 2.43.0 From nobody Sun Feb 8 03:32:30 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A88452C17B4; Tue, 13 May 2025 20:38:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747168685; cv=none; b=ncSjJl2maBQILEfIgy46H3ssL2DYx7z7uOy6tk/04u6K1Py6PUB1BDWmeupOr9Biaowal7IGeYnkxcutXvRZoWlAciuTSsyGV0+hAxsLJhHLuV45FEL2rO9zLfzyeGKST6F8LaA2IJn0QsZjl9a/Ub/8olwC3/Q3HHs0PbsOwGg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747168685; c=relaxed/simple; bh=8Lfg9L/fBQ9McgK/dl0rQJBpGwpkcPv9aMzRa9sr5kc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=V1Ms2vF3NuxUfnT+F71N+eP2nPO/6mrcgG2FEzHIzt82CTgaQVR07WTrdmCGCkpIM+KSNJOzXBdHKAXkrQZ2004xOMK0tgk2t0sGKJYOkKLLWKzx1Uuia3HyKKEMh8cpDfd3tDJ+5CSMWHzwfDR2ThWDjSseL6DSn1zb/SlguCM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=OUyPI5xp; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="OUyPI5xp" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1747168684; x=1778704684; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8Lfg9L/fBQ9McgK/dl0rQJBpGwpkcPv9aMzRa9sr5kc=; b=OUyPI5xpaQO5qddYja9TgsmtJW3APQXRZkxkIWms6nvh9nOP5rKhEjjF pEo4T3Z1xfKddAHHy8HRKCoQqkcmS++FZrzAjSUaTTsFMSH12RnyTgmXO zVtTsNKemEyPirWrA7L1kVSTxCMJSKaVndi9g7JT1/xe7uK0+f3mCMN/j 07KFe6hwYtarL0j9HjlCF/djcGWWLwg+l5RM+VCcGs67Z19/6LLrYIje1 998EMvPUpJpeA0bUy77IvCRfXZol22BCqPt7ZeR6vpVWhDH7K7g/98Efm 68T99nyXJ2bHwFPMgusmRYK0P3FnGf+6Cod+m0zczZOtHWm6fVOD7pQPU g==; X-CSE-ConnectionGUID: sHn1M0CkT5SwsCqbiKocig== X-CSE-MsgGUID: bt2PDjDSTwGYKOTEdWgW0A== X-IronPort-AV: E=McAfee;i="6700,10204,11432"; a="49160498" X-IronPort-AV: E=Sophos;i="6.15,286,1739865600"; d="scan'208";a="49160498" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2025 13:38:01 -0700 X-CSE-ConnectionGUID: DqlVOjUOSpWSPEPN/6PMmA== X-CSE-MsgGUID: 7rhg0/1BTDuX7xq0+Blbfg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,286,1739865600"; d="scan'208";a="138241740" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa008.fm.intel.com with ESMTP; 13 May 2025 13:38:00 -0700 From: Sohil Mehta To: x86@kernel.org, linux-kernel@vger.kernel.org Cc: Xin Li , "H . Peter Anvin" , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , Peter Zijlstra , Sean Christopherson , Adrian Hunter , Kan Liang , Tony Luck , Zhang Rui , Steven Rostedt , Sohil Mehta , Andrew Cooper , "Kirill A . Shutemov" , Jacob Pan , Andi Kleen , Kai Huang , Sandipan Das , linux-perf-users@vger.kernel.org, linux-edac@vger.kernel.org, kvm@vger.kernel.org, linux-pm@vger.kernel.org, linux-trace-kernel@vger.kernel.org Subject: [PATCH v6 9/9] x86/nmi: Print source information with the unknown NMI console message Date: Tue, 13 May 2025 13:38:03 -0700 Message-ID: <20250513203803.2636561-10-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513203803.2636561-1-sohil.mehta@intel.com> References: <20250513203803.2636561-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The NMI-source bitmap is critical information provided by the NMI-source reporting feature. It is very useful in debugging unknown NMIs since it can pinpoint the exact source that caused the NMI. Print the source bitmap along with the "Unknown NMI" kernel log message. Signed-off-by: Sohil Mehta --- v6: Drop the tracepoint modification part for now. v5: New patch --- arch/x86/kernel/nmi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/kernel/nmi.c b/arch/x86/kernel/nmi.c index 55ecbe2ab5e4..7a288603683f 100644 --- a/arch/x86/kernel/nmi.c +++ b/arch/x86/kernel/nmi.c @@ -376,6 +376,9 @@ unknown_nmi_error(unsigned char reason, struct pt_regs = *regs) pr_emerg_ratelimited("Uhhuh. NMI received for unknown reason %02x on CPU = %d.\n", reason, smp_processor_id()); =20 + if (cpu_feature_enabled(X86_FEATURE_NMI_SOURCE)) + pr_emerg_ratelimited("NMI-source bitmap is 0x%lx\n", fred_event_data(reg= s)); + if (unknown_nmi_panic || panic_on_unrecovered_nmi) nmi_panic(regs, "NMI: Not continuing"); =20 --=20 2.43.0