From nobody Mon Feb 9 06:31:14 2026 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A30A245008; Tue, 13 May 2025 15:46:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747151206; cv=none; b=Sf9vgy4b2vYaXV2wWMQNQSW9U5y/0bJ6H4DrFd0C9kIB3r7wc184IikYYOAoEKsPXQnceJnefDFp4AGFPtJNlIAf/+ssoFRcuJ1IrONp37hMF9os885evGYqQZ32ne6D9W+jI0FihvcDQbAakNomWQUCBfFIlM4bEX9OCGCypw0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747151206; c=relaxed/simple; bh=Rp+eIdADM/nkDaSGzqkO3OHPcwqxVLISWejxOsH3XFg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YMDXXxqdtOLPDCjeKzywDKnrqEzWH5H9BiTQO2th8hRjKCNcGY2UQPjjegGk4ZamznIA+IcKdk/CX77EA8UCgWuYm4un8KuALDHds89gu9/Rw+dfTPqLURHQ+k/kZFrbELaNwkOXa47tVfCBvmLClPgrTtQYpNvJOyhxiiUNZuo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Bf917HXh; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Bf917HXh" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-43cf05f0c3eso37924555e9.0; Tue, 13 May 2025 08:46:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1747151201; x=1747756001; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AOxHk/73nK91rx9FCQs18rpM0IVD1C67FeXMDSvIFJI=; b=Bf917HXhEqmWEs6H5VyNKZK1dlOhiOcTcgdjMFq7CzXkLa+BOmwxF9G6ePXI8u3gj1 KLzM8fs8xTZkoIRGi7/SmXnvPJUShExfalmgFgwGX1o5fF4LRG/gFA241UWljVSlJFaD +DyRo3DISd64tf3QAJ8d8hyCQmuLcTZzAoTgkyYNAONPnOObMNGEQq7ESkNKQg5BbPT8 PVp1tNhH9aCocTQpauVOgIfvOVDUHUrkhatc1Go+E+3vhFGNwemnkZVFHbQBLViENtHV edySA13yDTjPPWbSjdXmKO02nsNP8iFYskfxnYzmgqPvU+L7zuIEZ3ounc4Zqbm5jY4b /bMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747151201; x=1747756001; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AOxHk/73nK91rx9FCQs18rpM0IVD1C67FeXMDSvIFJI=; b=MAA/+E41E7cWA/4nyMa4jxVelgdR0Cm6kZvvnwoqo3xfxnFEbTUiebovrwLcm3HraG eR9JzLzbZnPjuxmyGVLm3xWHaWNAYf/bzgx1IoIq3quGq0S5c8F4r4aAP0jsQiNT1Cdq Paq5FIyXNY38yaC8gqG1+YmIF+q/y7+P0sQ9ak3+L87oFtL7Vw8pM3hUYlUDcLbYaURd q2L0OhiSYGVS+vpU3Jlw+6qLzX6AudnkbmLXUvlPCQczS8dnDOFLvR9YeH4xstrBXjW1 xfUPyOrKeAMi+Ulq59wzuGS2dnSJ2VqzvztCbBZJ2TiuluIqUn+4S3T9WWT4Qk0m7BRo eTRw== X-Forwarded-Encrypted: i=1; AJvYcCXMSQbc4r/pK1FQrcCQszwR7pEzcnBgvmY/WSSRl5NWfok+rODCgbDtRhjjijze2abjCocUf00hqZKW9+c=@vger.kernel.org, AJvYcCXt0KUcb01gx2GajoXUFlxCOI5BNHpKRlfk3A80aearT3V08txaVpErPu8WcEtsqoOnyu6zPiCppz1BebG34/4JYNk=@vger.kernel.org X-Gm-Message-State: AOJu0Yxke9X4fWKU2dSLR1SHRhZ56PKy0/mPi5rF0+7JrF8p3c0LTUmU JUwLxXwzy6qQCadq3EVqIxGgajSgKoaJJ+/nbt8JyBgVcAT25e4kIuUgVqmW X-Gm-Gg: ASbGncup8u+gn+IaHESfqTneSP21cSf+Anz5UJIuTKWZqyGx3myqB4AI1TCyqSN+SiR Kwsc9qp2b35Mwik/FlETYeT0edzRj2bURFgOfiOJW9lNFmEyo+wZm3tRWRVfpPMXfqVjDoTUZjg cKrP9iDvqnp69xt/ys6F383OTxsKgkrtgDmoDGBsktl1Xp/OR0e5/09uOml8TifXA/txtWcWz9m wulYhSMSQp7xCFQGp8Wn1Yon8t95YOQTju9aiw9ophs5nW3qOVhx9XqWJPfUgZWrW40LEglj6H4 0akUDlPqc2vagfD5RzbL/W9rJr3oLWQ4wyKAcFrGDWYCC4bdiWXbShaTe3+7X7MLT0lXMwFolCk QgTFQlsNZ4Q== X-Google-Smtp-Source: AGHT+IHjA9kxBNqFGlWJrtqwm6tF0CAfbIQ3Z6o5d+j7aDhFhNJbRe+H0Oj29V2beUpcVT9tGT+ZXA== X-Received: by 2002:a05:600c:c07:b0:43d:300f:fa3d with SMTP id 5b1f17b1804b1-442d6d18abfmr155256055e9.5.1747151201323; Tue, 13 May 2025 08:46:41 -0700 (PDT) Received: from iku.example.org ([2a06:5906:61b:2d00:c996:6219:e8d3:1274]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442d596a5e4sm183724645e9.31.2025.05.13.08.46.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 May 2025 08:46:40 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , linux-renesas-soc@vger.kernel.org Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 1/5] clk: renesas: r9a09g056-cpg: Add clock and reset entries for GBETH0/1 Date: Tue, 13 May 2025 16:46:31 +0100 Message-ID: <20250513154635.273664-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250513154635.273664-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250513154635.273664-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add clock and reset entries for GBETH instances. Include core clocks for PTP, sourced from PLLETH, and add PLLs, dividers, and static mux clocks used as clock sources for the GBETH IP. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a09g056-cpg.c | 66 +++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/drivers/clk/renesas/r9a09g056-cpg.c b/drivers/clk/renesas/r9a0= 9g056-cpg.c index e2712a25c43a..5582041455c5 100644 --- a/drivers/clk/renesas/r9a09g056-cpg.c +++ b/drivers/clk/renesas/r9a09g056-cpg.c @@ -28,6 +28,7 @@ enum clk_ids { CLK_PLLCLN, CLK_PLLDTY, CLK_PLLCA55, + CLK_PLLETH, =20 /* Internal Core Clocks */ CLK_PLLCM33_DIV16, @@ -35,6 +36,15 @@ enum clk_ids { CLK_PLLCLN_DIV8, CLK_PLLDTY_ACPU, CLK_PLLDTY_ACPU_DIV4, + CLK_PLLDTY_DIV8, + CLK_PLLETH_DIV_250_FIX, + CLK_PLLETH_DIV_125_FIX, + CLK_CSDIV_PLLETH_GBE0, + CLK_CSDIV_PLLETH_GBE1, + CLK_SMUX2_GBE0_TXCLK, + CLK_SMUX2_GBE0_RXCLK, + CLK_SMUX2_GBE1_TXCLK, + CLK_SMUX2_GBE1_RXCLK, =20 /* Module Clocks */ MOD_CLK_BASE, @@ -57,6 +67,19 @@ static const struct clk_div_table dtable_2_64[] =3D { {0, 0}, }; =20 +static const struct clk_div_table dtable_2_100[] =3D { + {0, 2}, + {1, 10}, + {2, 100}, + {0, 0}, +}; + +/* Mux clock tables */ +static const char * const smux2_gbe0_rxclk[] =3D { ".plleth_gbe0", "et0_rx= clk" }; +static const char * const smux2_gbe0_txclk[] =3D { ".plleth_gbe0", "et0_tx= clk" }; +static const char * const smux2_gbe1_rxclk[] =3D { ".plleth_gbe1", "et1_rx= clk" }; +static const char * const smux2_gbe1_txclk[] =3D { ".plleth_gbe1", "et1_tx= clk" }; + static const struct cpg_core_clk r9a09g056_core_clks[] __initconst =3D { /* External Clock Inputs */ DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL), @@ -68,6 +91,7 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __= initconst =3D { DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3), DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55), + DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3), =20 /* Internal Core Clocks */ DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), @@ -77,6 +101,18 @@ static const struct cpg_core_clk r9a09g056_core_clks[] = __initconst =3D { =20 DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dta= ble_2_64), DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, = 4), + DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8), + + DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4), + DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_F= IX, 1, 2), + DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0, + CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL0, dtable_2_100), + DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1, + CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL1, dtable_2_100), + DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_= gbe0_txclk), + DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_= gbe0_rxclk), + DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_= gbe1_txclk), + DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_= gbe1_rxclk), =20 /* Core Clocks */ DEF_FIXED("sys_0_pclk", R9A09G056_SYS_0_PCLK, CLK_QEXTAL, 1, 1), @@ -89,6 +125,10 @@ static const struct cpg_core_clk r9a09g056_core_clks[] = __initconst =3D { DEF_DDIV("ca55_0_coreclk3", R9A09G056_CA55_0_CORE_CLK3, CLK_PLLCA55, CDDIV1_DIVCTL3, dtable_1_8), DEF_FIXED("iotop_0_shclk", R9A09G056_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1,= 1), + DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G056_GBETH_0_CLK_PTP_REF_I, + CLK_PLLETH_DIV_125_FIX, 1, 1), + DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G056_GBETH_1_CLK_PTP_REF_I, + CLK_PLLETH_DIV_125_FIX, 1, 1), }; =20 static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst =3D { @@ -120,6 +160,30 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[]= __initconst =3D { BUS_MSTOP(8, BIT(4))), DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14, BUS_MSTOP(8, BIT(4))), + DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, = 24, + BUS_MSTOP(8, BIT(5)), 1), + DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, = 25, + BUS_MSTOP(8, BIT(5)), 1), + DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10= , 5, 26, + BUS_MSTOP(8, BIT(5)), 1), + DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11= , 5, 27, + BUS_MSTOP(8, BIT(5)), 1), + DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28, + BUS_MSTOP(8, BIT(5))), + DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29, + BUS_MSTOP(8, BIT(5))), + DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5,= 30, + BUS_MSTOP(8, BIT(6)), 1), + DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5,= 31, + BUS_MSTOP(8, BIT(6)), 1), + DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0,= 6, 0, + BUS_MSTOP(8, BIT(6)), 1), + DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1,= 6, 1, + BUS_MSTOP(8, BIT(6)), 1), + DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12, 2, 6, 2, + BUS_MSTOP(8, BIT(6))), + DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3, + BUS_MSTOP(8, BIT(6))), }; =20 static const struct rzv2h_reset r9a09g056_resets[] __initconst =3D { @@ -130,6 +194,8 @@ static const struct rzv2h_reset r9a09g056_resets[] __in= itconst =3D { DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */ DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */ DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */ + DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */ + DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */ }; =20 const struct rzv2h_cpg_info r9a09g056_cpg_info __initconst =3D { --=20 2.49.0 From nobody Mon Feb 9 06:31:14 2026 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C9912BE0F4; Tue, 13 May 2025 15:46:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747151206; cv=none; b=GGQ3VcGqbis3IRiZN7XBwWIb3zobxp/2H4HWjRHYSPv/yCMBx9EY2866ZULU9nc1rSmJq2o3pDTEQWFaEbcSDsUUG4r13JElOmqWr+znX++cXcqN9R/9XQhDPTrqrxGGHPS+/U1hvFNa+ZWsHZKxr+g+08UoZnqwD8uAZ/MYVvE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747151206; c=relaxed/simple; bh=7OObJFxfpZp1B8oXL+u4n3UpxgBKQ5XeeE4l+y+8bGs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Ih+2wsSExvF+6vrfrXMIe/+wr3FZNMuKLXKjqnw+zkFcpzaFELIoBYwR/yS8fP0sy5peT7WJL3jT7Moz7mdA9m/SVcqdP1PjLpJD84NYXmVSI48LdEuu3M+7PpX94W/g1YjeA8KAKmHiMZD8ZypOLqzPT22AAAb0SMLynez3W/Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ILAYyKUL; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ILAYyKUL" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-43d0618746bso44390225e9.2; Tue, 13 May 2025 08:46:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1747151203; x=1747756003; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Qy89hG9RDC9tHSW4zOkJGpVnZSzDfakkMpz+ikecyME=; b=ILAYyKULRth6QB4SQlCtX2eGm7/c9FBAva1o1UukawMywZp3gHveU4zszWpFCs04H3 Vd2BolGksaKb0gXch709SrNwT0VnQB6jqPcZ08fk6BP+E0o2w7loe/0xzB+1DoEYmtkw BP0C1ydJkoyS2s5EwHqh+lmxUWXZAvUQbqY4yicAomNMT8Uez89q3fugjnnzQtjD2z/S QO/Fw/9T14O2uBK34ESfAEZky2cr17v98n0EEAMEi4BhbOgvshJl1X2AwLK1kG+rZSD8 PcS+iYFyJS2WcqlqjAYwcEFZr3ScYqfsFVFGijdhujB/WuuBMgTOflsbrU138tzigFBu JOvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747151203; x=1747756003; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Qy89hG9RDC9tHSW4zOkJGpVnZSzDfakkMpz+ikecyME=; b=F8VYtkxmVEPPkMwUnon6kOez6ikw4Qlh/ll9nwHP3h56gHKExLsfuTo1JoSUlAcM0o 86nPSEdQYljywE1uspW8oB3QlDe0Hdk/cTN74eyfmfLGAxoboigcqm6tG6mFhuRYjO14 SIh97FHBhY4YpWsnDjMuxtKZFEujJuhakY3oH24/gfRNhdX1MjMl/+nZDEBbdmyNewFZ sZ2n/YJJJBSbBpfWkRklmqsC5bxZ4LOln2UJ99wuw7SkhE4Ggjf2DeRTAm97KWCB2Eej GHFBouq5dowbSfHwO2Zzbl1q56KUHUESAgtjGbu0K10uv+IJpBrrn8uclPj6sh41p/2m K+Qg== X-Forwarded-Encrypted: i=1; AJvYcCUqC7bDXnlbnkPXkrqbLR/wtjiJDjh2mcPqsIQQKOjeCd8k3qZh6UYQiPAVNJlwFY6tK9DwnhFUobGjyHw=@vger.kernel.org, AJvYcCVZwRjRu8d0U1W4d4ehVc4MnZ+1l6fwDXF3y1y/x+6uc83HZsVhS4mq4JeqprTqsL2Z4DJEXhG3BRdmMqL0gyq73H4=@vger.kernel.org X-Gm-Message-State: AOJu0YyASbvXfwc6tvCbE/xDfi3TRor85RtwTN6Jmdhx1aeXeT4lsMUG uFJNGRg+CZgJXoSqluUyohb4xuyh5wVetxTWc3VcvuFnjUY2bA/5bT9+zKBo X-Gm-Gg: ASbGncsE4RV/JEtQWwrKdIwU9pVnd+hsoF95kORigX2vqxPYLOtWiWPKeYrv3FI4mkB rFq8mgWCPg3lI0r7v0pxiS5XbN8m9PuRb1sd/rdO6/NbWSZ0FjgoL5+Ep2DR35cHQagOqUcZIWv RLHuPkQQRW1BnvhOnJXfpgouZbJz0co2Cs4AmoEC56zvbpxHp+cY5dTEU2x7PcLw9jRSopnxPh2 WHZmEaoUM9Ci30Yxa0vEBEwRXcbq50ytR7rUjcqD5tEwj4wa1MB/18Ez/RFPP3oYXhPMkkNToJJ JmaWnMLOfKC9/N6VrOUpxbwNncsgHkapizOP4lm/f//9wPfQJ1xeatAJvzHChxaH4iQMMv0RsHe 2uWHsnH9T+w== X-Google-Smtp-Source: AGHT+IGkXKhFbr9hf0yD5nL5be1Q4mtJy3U+YmCf6vFEaqGgeKkNb8K5asqIxkl8QQ0jO3CWgb6AmA== X-Received: by 2002:a05:600c:8708:b0:43c:f3e4:d6f6 with SMTP id 5b1f17b1804b1-442d6ddeb99mr179265345e9.31.1747151202588; Tue, 13 May 2025 08:46:42 -0700 (PDT) Received: from iku.example.org ([2a06:5906:61b:2d00:c996:6219:e8d3:1274]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442d596a5e4sm183724645e9.31.2025.05.13.08.46.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 May 2025 08:46:41 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , linux-renesas-soc@vger.kernel.org Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 2/5] clk: renesas: r9a09g056-cpg: Add clock and reset entries for OSTM instances Date: Tue, 13 May 2025 16:46:32 +0100 Message-ID: <20250513154635.273664-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250513154635.273664-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250513154635.273664-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Introduce a new fixed divider .pllcln_div16 which is sourced from PLLCLN and add PCLK module clocks gtm_0_pclk through gtm_7_pclk for OSTM0-7. Add corresponding reset lines GTM_0_PRESETZ through GTM_7_PRESETZ to control the OSTM instances. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a09g056-cpg.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/clk/renesas/r9a09g056-cpg.c b/drivers/clk/renesas/r9a0= 9g056-cpg.c index 5582041455c5..c57583e7f659 100644 --- a/drivers/clk/renesas/r9a09g056-cpg.c +++ b/drivers/clk/renesas/r9a09g056-cpg.c @@ -34,6 +34,7 @@ enum clk_ids { CLK_PLLCM33_DIV16, CLK_PLLCLN_DIV2, CLK_PLLCLN_DIV8, + CLK_PLLCLN_DIV16, CLK_PLLDTY_ACPU, CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_DIV8, @@ -98,6 +99,7 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __= initconst =3D { =20 DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2), DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8), + DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16), =20 DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dta= ble_2_64), DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, = 4), @@ -134,6 +136,22 @@ static const struct cpg_core_clk r9a09g056_core_clks[]= __initconst =3D { static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst =3D { DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19, BUS_MSTOP(3, BIT(5))), + DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3, + BUS_MSTOP(5, BIT(10))), + DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4, + BUS_MSTOP(5, BIT(11))), + DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5, + BUS_MSTOP(2, BIT(13))), + DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6, + BUS_MSTOP(2, BIT(14))), + DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7, + BUS_MSTOP(11, BIT(13))), + DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8, + BUS_MSTOP(11, BIT(14))), + DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9, + BUS_MSTOP(11, BIT(15))), + DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10, + BUS_MSTOP(12, BIT(0))), DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15, BUS_MSTOP(3, BIT(14))), DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3, @@ -190,6 +208,14 @@ static const struct rzv2h_reset r9a09g056_resets[] __i= nitconst =3D { DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */ DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */ DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */ + DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */ + DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */ + DEF_RST(6, 15, 3, 0), /* GTM_2_PRESETZ */ + DEF_RST(7, 0, 3, 1), /* GTM_3_PRESETZ */ + DEF_RST(7, 1, 3, 2), /* GTM_4_PRESETZ */ + DEF_RST(7, 2, 3, 3), /* GTM_5_PRESETZ */ + DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */ + DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */ DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */ DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */ DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */ --=20 2.49.0 From nobody Mon Feb 9 06:31:14 2026 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 591812BE7BD; Tue, 13 May 2025 15:46:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747151208; cv=none; b=c21umQfnN+5jac5VzrYwRPSm1R6TU5wlb9qYSMCzyRXWUY52cQ0mla9Tymz7SYpoHgL0ABtrKSf1DE4wjl3Z6nUejPKruRclf+2D8Byg3skAsvFs6HVyXrrO+QttJtv+eRpEzxseFCF/V7WA9l9Q2MjyMziqp9+VqVicUQCjdnU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747151208; c=relaxed/simple; bh=LI3mbOUtgq+1PPe2kyvkUpTF5WLNyxcZW8ejjH9IOX4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=H07PXVS6ruzczbeQZvIgTpd1stJ0u0g39knzozjhZwm11EeGdpeWugAHsQyUgxARTZkMyqrZgVCYob9AJsJzdjBwTpV9egPdAaZXx8fxJDXp/ivFjeEJK4tJHaIkVnCzicKB8uv+/Z7p2aVctFDrA9Shf+esMlcZO+1ofVMHLfk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=XYcZY5cO; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="XYcZY5cO" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-43cfebc343dso38710495e9.2; Tue, 13 May 2025 08:46:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1747151203; x=1747756003; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G47Vz6fvEHe6vCJ7AEcadKs65EoTqDV9LPlrLeWYtgs=; b=XYcZY5cOTlH59WNlzDA2mtH5enXRSYUrEMXdqwBtrJb5EpB5/U85ifvjIUIvRM8ojG oOgt7rgMI6D9F+vVbcgikNFQq3o2ZGmYlmxpSJ3CxZQcIMRc1KGaTShnkzq5y5Xq5uxb FxUfFYk0nFB9kfepOtN2cb0yt0mN3Z2RSCVWJrJvfkql79P22R2b56SiuHL35uwYv/XV e48iJNueBsBYp5K2qWnkEkkKqRxATq5UxTI2EmTEcAlASZAZn2DxWg8+Vi1+JPtUwhRO HwMNMpl3fDRQ1URLh4iXJN/8kF/LK6pqTZdze2vUf8IQwYeEBA9cEeOfu78gILWz7Wqc 5MQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747151203; x=1747756003; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G47Vz6fvEHe6vCJ7AEcadKs65EoTqDV9LPlrLeWYtgs=; b=HXg5HzpUmeYmPVkJJFsrsl7iRURQ5zpYXvNJsoYzzhDF7e8TWkvzz82UtsrZ0/YJXn EdTR5w/3zaipPW1UWxdtVWeNlnBOQzxukDSKiUJRC6SQPKlOyDdv8QufwlWT4H1+O9xE Bo59QRd6bTGD9Ro+5RAxnDCyw1JY/UWqNhvYpHuQVwbT6BiWj10TPj924PferqPUTDvd q8K/lLSugrLCW08ekKOuSKj9rOrYvFvcRkeOknNzI0RsnY+FUnl5yEQHdhelOSso7tg4 CVNcqCiziW8CFjwFfLvw3MAZk3RrljFUMwxm5DXfI3aw0p458/L67J2vtVPXThJNYRB6 WHSw== X-Forwarded-Encrypted: i=1; AJvYcCXGIyKwXIAivCuuYgto3aCgFmr7YC0C46ts1FexkpocU0ssqxaFpI/KTkmh4jvEAOdnAIG9iMTKPZwmb94=@vger.kernel.org, AJvYcCXYQn9uBOnYAVDIxJEpCw2s6yA8LvRA/kwGQU/DWXiBzXaxAonjX3ZH+19Fnk6cTTR6mOBkT/bxeUdwZH2Ml4+HOsk=@vger.kernel.org X-Gm-Message-State: AOJu0YxhiIKW3yn37jcrCgWJuVoiSFi+5PeHL19VBA5IKlTYOQMJbZtx T01jRV89uNHvGurEYh8ucs8WUE2tlbEj6cOsLd9EdSUZCx/V+08e X-Gm-Gg: ASbGncttQQgb80y5VX26YkSIvqluo0Z2chzYXLhFz6FOqVyQupictvf42VQZHrmxDpF rjQe+YpA0S5HYPANZJEq46r88ItEJomTxWQkW9r0Lq6/FS5zHf1bTeOocDE80I5U/pTiBJXDiQZ Tag0UxqX0lq/sd4JYUeoNmb+CBYrEyLGb2s/D6jVxzQdtGjfQ8yPAaM+7tOUxP0O/BxelGzQyxZ awoTt2J2uV42RjhUdEZAzvOWfqreasjqBaReE/fDVFj+tB8kCYzIluh7uMvd/VM/ONzb2f9Va27 XrIpRRc6eQ/IJM8M/YvMj3fvhQNVydiTD3CdSQy33/AITIckq/yonnLtUxdHpBtdEnMEhYrmPal pkbXcD15OSP25EpPyeXTw X-Google-Smtp-Source: AGHT+IFlgguu579T11n1XG3482eOGf2Xqxwq8atO6NLI+PD9ZnCX/USeEANd62pNzKgdi0sTjcor+g== X-Received: by 2002:a05:600c:528a:b0:441:d43d:4f68 with SMTP id 5b1f17b1804b1-442d6d645d2mr170703775e9.15.1747151203337; Tue, 13 May 2025 08:46:43 -0700 (PDT) Received: from iku.example.org ([2a06:5906:61b:2d00:c996:6219:e8d3:1274]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442d596a5e4sm183724645e9.31.2025.05.13.08.46.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 May 2025 08:46:42 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , linux-renesas-soc@vger.kernel.org Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 3/5] clk: renesas: r9a09g056: Add clock and reset entries for RIIC controllers Date: Tue, 13 May 2025 16:46:33 +0100 Message-ID: <20250513154635.273664-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250513154635.273664-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250513154635.273664-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add module clock and reset definitions for RIIC controllers 0-8, which are available on the RZ/V2N (R9A09G056) SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a09g056-cpg.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/clk/renesas/r9a09g056-cpg.c b/drivers/clk/renesas/r9a0= 9g056-cpg.c index c57583e7f659..a489e718a9c2 100644 --- a/drivers/clk/renesas/r9a09g056-cpg.c +++ b/drivers/clk/renesas/r9a09g056-cpg.c @@ -154,6 +154,24 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[]= __initconst =3D { BUS_MSTOP(12, BIT(0))), DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15, BUS_MSTOP(3, BIT(14))), + DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19, + BUS_MSTOP(3, BIT(13))), + DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20, + BUS_MSTOP(1, BIT(1))), + DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21, + BUS_MSTOP(1, BIT(2))), + DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22, + BUS_MSTOP(1, BIT(3))), + DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23, + BUS_MSTOP(1, BIT(4))), + DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24, + BUS_MSTOP(1, BIT(5))), + DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25, + BUS_MSTOP(1, BIT(6))), + DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26, + BUS_MSTOP(1, BIT(7))), + DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27, + BUS_MSTOP(1, BIT(8))), DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3, BUS_MSTOP(8, BIT(2))), DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4, @@ -217,6 +235,15 @@ static const struct rzv2h_reset r9a09g056_resets[] __i= nitconst =3D { DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */ DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */ DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */ + DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */ + DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */ + DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */ + DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */ + DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */ + DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */ + DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */ + DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */ + DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */ DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */ DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */ DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */ --=20 2.49.0 From nobody Mon Feb 9 06:31:14 2026 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 006412BE7A8; Tue, 13 May 2025 15:46:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747151207; cv=none; b=LTZ6H5fSh7yIpWPTAo1JZiZu2S4tVfu3iX+57LAUKj7dkMk4XAZ9IWqtiaQI49GmBhTZBZnzQeJQZK9h6XeRqOvvx9IotjD+7s4Y6jUl3ISArR4FgBo4OqEPe4NkLKCtOjK9ky9mIsksdPaRdx0DpvI8j3OzYQpiNLX0pCEJfXk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747151207; c=relaxed/simple; bh=Ei3c30IkgDbDFBAIgcKxhxiqZ5bn2Gk1/GLZH03kNh4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Mh0Kpc7x4KIS48dupWb/bBxJZptdWCkb5WvVwboJE3Nnrol9KbMbkxpU1X8Ae5KF70UBmTa1sBhpG3LbMkqTYK4UwKeYDSAFkKLqEILFN+dZz/p04JiJpKVqmHqnss+QeVHmLdUpfE/cLC3M3QSJgzIqpYTjhFBn57dxOnDBk80= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=kHwF8iYS; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="kHwF8iYS" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-441d1ed82dbso61439815e9.0; Tue, 13 May 2025 08:46:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1747151204; x=1747756004; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=frTcHJ1Ea1WqOcJu3ebjls25uv02kObZU7xmSP4EXMc=; b=kHwF8iYSlpdaHEEFWRYzPaiiP3fFqqoA2pEsjOQHeZkyU0pvijA4sPksy84ZC2Fr7N 4pkVK1PSPPskC/iyCygrm6zL40Wc3/HxyTZyA99YERnW6hmL/tHT53uId7WIOXEhkEgB z364N5mUZNuSZkdyVZoo56CrQiZNijVnXfr32xvotsssn3ZoxpyK0to+OZSGZF/hNvq1 6k3r7pa/5Xf4wD49plsFNiQD7+i9Spjhe7yQknzlcUK2qhtv/N29OkwqZZgq3HeKbn6/ vKAXXGTI7vQhEo00gh3ApowlEM3SsAH8Oz5bQCVk10zAq4jIuUirodqjgfAG8EPC8W+R 9wSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747151204; x=1747756004; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=frTcHJ1Ea1WqOcJu3ebjls25uv02kObZU7xmSP4EXMc=; b=fwMPpoplCu+D1mLdhrIpYZ9yqoTd0UmT1hR8cq0r7JfsUJ8XNwsrHrszg71qODXuDa HeFPFVD4FOpsrxXebB/KU4IE5hnPSEaTGnlluXp8ViBZiTILDrvL6eqJBvBFS8I+7ham iEnYhi1RXCel61WP4H+5hM/FHOuAvUSc/Llz+vNmXEd5v8Z0zRkIUa4semVw+aqizHLH mDJn0Y6RM8swq2VF52FUuRT7qbJ9DbmcGfmxIMn3PBvN+rbgJHbg02vk5LGoNjl/29V3 TyqaA/f6E4wXhJ/wMdjI0Bd/lKneMnlGwz/flxMbloY+8YKv1W8ziAYjyxAiKODi0SH1 5JIA== X-Forwarded-Encrypted: i=1; AJvYcCUXWI52jhsGw7Np1hfUk8OYjnwadsNd8fmIWx+J8uS6cHYCBmvGPWFN/ItIODtXFukQI8xskcciaKm8kHQ=@vger.kernel.org, AJvYcCWTq7F2Ys0SSbvILbdGVXGLL0XJ+oIn6mHgWVhBk0z83GTOCcRY9I3AOrIjAcZJ9VaFS2yKxk2Oa9okmg+amQe7610=@vger.kernel.org X-Gm-Message-State: AOJu0YwEWNeFd7oIqmbeY0HHD/bDRnAJoqg8+tCgS7xjvucMqlB9KDJq /RBxmPBHQjw65ZEnxTvJ8G6J6kj819CYmZdRtSmChuCBPOBqueoH X-Gm-Gg: ASbGnctOvG7pbCIkP1ZRlUE7C11GCVqQ81k5sUHgDSCoSY00SyPctK6YLMBdWFDM+9s uNtxUi1wbaT+oDmJrUpfx7t3FB0e0VVTQmYD/5k0MMSlS7a9cBrV6WfDKG3UiGWMVyoIOOdElL0 Fncmqp5xmAws/4oTE6gPPrYWImMO16VcEwR2ZmjmZtPUfo7yzkW1JXpy/+mZfP1mtU0ZR/nIiY+ paEWeNSQqr2PdOAg4ga603VW/OHYTk5RExzPmme4kSJmKVOj/YSeoHiCQrjCvHH9ogoVaut2am8 YTKJeVzQ16dYnknrsqhNayvJFCf9YhX7SQIChf64+QnX7eJoBBab84dLamDDowORvzmQU117mTb +j2g01US+Vw== X-Google-Smtp-Source: AGHT+IFlZs4KN3x+jOO4Zys+qXTA4GLl+QCzqzAAx4N+sG7pzBc9R0NdKbUP5Da7aaiajbltT2pLcw== X-Received: by 2002:a05:600c:6095:b0:43b:c0fa:f9cd with SMTP id 5b1f17b1804b1-442d6d0a9ebmr147133625e9.7.1747151204078; Tue, 13 May 2025 08:46:44 -0700 (PDT) Received: from iku.example.org ([2a06:5906:61b:2d00:c996:6219:e8d3:1274]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442d596a5e4sm183724645e9.31.2025.05.13.08.46.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 May 2025 08:46:43 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , linux-renesas-soc@vger.kernel.org Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 4/5] clk: renesas: r9a09g056: Add clock and reset entries for WDT controllers Date: Tue, 13 May 2025 16:46:34 +0100 Message-ID: <20250513154635.273664-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250513154635.273664-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250513154635.273664-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add module clock and reset definitions for WDT0-3, which are available on the RZ/V2N (R9A09G056) SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a09g056-cpg.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/clk/renesas/r9a09g056-cpg.c b/drivers/clk/renesas/r9a0= 9g056-cpg.c index a489e718a9c2..7e34c4259a6c 100644 --- a/drivers/clk/renesas/r9a09g056-cpg.c +++ b/drivers/clk/renesas/r9a09g056-cpg.c @@ -152,6 +152,22 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[]= __initconst =3D { BUS_MSTOP(11, BIT(15))), DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10, BUS_MSTOP(12, BIT(0))), + DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11, + BUS_MSTOP(3, BIT(10))), + DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12, + BUS_MSTOP(3, BIT(10))), + DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13, + BUS_MSTOP(1, BIT(0))), + DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14, + BUS_MSTOP(1, BIT(0))), + DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15, + BUS_MSTOP(5, BIT(12))), + DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16, + BUS_MSTOP(5, BIT(12))), + DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17, + BUS_MSTOP(5, BIT(13))), + DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18, + BUS_MSTOP(5, BIT(13))), DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15, BUS_MSTOP(3, BIT(14))), DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19, @@ -234,6 +250,10 @@ static const struct rzv2h_reset r9a09g056_resets[] __i= nitconst =3D { DEF_RST(7, 2, 3, 3), /* GTM_5_PRESETZ */ DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */ DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */ + DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */ + DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */ + DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */ + DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */ DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */ DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */ DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */ --=20 2.49.0 From nobody Mon Feb 9 06:31:14 2026 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C71122BE7BB; Tue, 13 May 2025 15:46:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747151208; cv=none; b=J7QsCzw9jBXqAnoDWMJ1II3OBWoc3tF870jSmiwYl/6Y3Qfmma0N4UuPtKpMrKGphj1QspKrng7LypBG9WNTXvgMM7HGU6hwpRTKEIVOLe4VtGKwalnN7fB469cp80OtXc+11vqkiFTyA6ZIX1EBIRek2+tQi0T9pHomW90dyE4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747151208; c=relaxed/simple; bh=ND04u7mZCxafVj4HkDYoTBQzQ6yOCjXLrkgDWK76YaQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eP3H8CielEiVvrNmNxRM2pRz5hJL5WAqzH8ipK7Ce8SjTIU8/6rMvdO3wJLIklakBtIoBcESEAVX4GcTvgFVGHL9ZRh/5HVhVx4BFln4nYOmzdDgC//Wq8VLpPlgQyDyzLA/UQAKudxuTRRFLmAiSOC6Ws678pKtoSOieHqeOrQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=RtgVW5OP; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="RtgVW5OP" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-43edecbfb94so59655705e9.1; Tue, 13 May 2025 08:46:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1747151205; x=1747756005; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FefmbA6pOI8PMez6FVUK7e8M/BJCoNBt+TOUtcp4/mE=; b=RtgVW5OPGq+QFT+rUGwwHybPNiwtwgL+BwpBsYWu0f4MkJSq4e06QP9jV9kZ1n/gJO tvlDme3G1G3g0yj56jx4SNX5fP9l53QQIM8JjCvv5pIsjHl2qbZq3acXs97vdLRXfmH+ FyZoB6VL9Dqj4TNDYMEPG1G7s3upzjV17Ih5n6XM5QIF3AGBAzkBKWitKAkpISJBGNK6 vxI0Ls5p4uLj7afuxbIbNqvDUVZflKlvhIP5m+lix0Blm4UnHYRcEADm+04iQwC/PII7 NkXe7ChpTCF8fmnnzizUBRj1/GpTVSQXduWNp870KjWYvEWzY74mHji0AxkE0lxU38Ch X6ZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747151205; x=1747756005; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FefmbA6pOI8PMez6FVUK7e8M/BJCoNBt+TOUtcp4/mE=; b=FUTdJ+5KSf5iPbxoQwv9QmNyO5EyPEUZhv+gTxFeQ1/s4NTjk+l4+ZCzcjRjuDApUU 06WBOKqtYI1PrHGPBncpe68ERCFZMJ712TMl1jeUNaYgS2eLcy+MrT+qAyHxnTR9r/QD PWjEQ53Ut+TL1jvQ6zx0BePjFNeUPw5CKJQsaqrhlwFoHlgxHQ8qGkaSSTU/x6RYX2tp MbSd6E9R17dVUQGzpfpiqFKpogA8GHDAtseHfOSg5bpvQAO1jiOlUsHNVW4rRauhW3pi AH96VkHEQ8+NmmUWc3Dr42Mq0E0Uw6y3BN2IqidDOEyMV7PT88tV/fAJbJu17vmvm7jh w5cw== X-Forwarded-Encrypted: i=1; AJvYcCWK6vCg/mNxtRCcqyZrTxSA6uHAt5ICe6qPtc7ZbK6U7EBmDinfWoeXPn07sfrBvAyGFLvDA9u6ffEhl6w=@vger.kernel.org, AJvYcCWQKCSU4xpL+weitoXpgzw2zwrVtHHasC92dqAli4e0mAegp9JgvTnI1/+gfawavWNVmqzb9V8Bi+CtxwSsOJMvPbU=@vger.kernel.org X-Gm-Message-State: AOJu0Yyni/UCuoWLX0QuvRkADXlINXSYT1D7Uzco756fF8iiiRXdDA8e /pjWMwe8kBa8z4Zcu3zGRTne5lvJ16jypuO3+0MdPye+bSN42+X9 X-Gm-Gg: ASbGnctfPW25Mdpp4U0eU2ws0Ugjcl5LkTTa26GM/jQ0/kg5iY7aZaBRj/CO/Qg+GK2 9Ctu3Lc7hljIC7Di+NgPRFVIq4rtkRpkRUF+y9N25uUU0BsyHl8fZFDsvIpztLe5WOTTzNl/z7l cx6Dwo0OtdDvLFpbA0kJCEKLaegH4ylStbKGWW9MUjCwRIl6wn7xMpI4cL62qLQ3ESfVUqMlQCL ATC4GceUk1hiwSfmy3XMaV6H7Y/Bth1TAgW7OV6Qv/Cke3IF7rIbWKb4Tj+fXPsO5lys2Bmu96n uErBrDdnIORndlJkEhIlyOZj9xKtxY0tIY4tiShanvb/rK5onGnvhz72378LQLC63eD4FjfyOLz c1uq5YreVxGxUIGlSdUsu X-Google-Smtp-Source: AGHT+IFd8YocAXJjTASlpGSxIniCnwA35PkUAppMddBcuuzZsCyPcwTDS+GvCWNTdIIq1aTPh1OcOQ== X-Received: by 2002:a05:600c:6487:b0:43c:e70d:44f0 with SMTP id 5b1f17b1804b1-442d6d516efmr165814595e9.19.1747151204757; Tue, 13 May 2025 08:46:44 -0700 (PDT) Received: from iku.example.org ([2a06:5906:61b:2d00:c996:6219:e8d3:1274]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442d596a5e4sm183724645e9.31.2025.05.13.08.46.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 May 2025 08:46:44 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , linux-renesas-soc@vger.kernel.org Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 5/5] clk: renesas: r9a09g056: Add clocks and resets for Mali-G31 GPU Date: Tue, 13 May 2025 16:46:35 +0100 Message-ID: <20250513154635.273664-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250513154635.273664-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250513154635.273664-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add clock and reset support for the Mali-G31 GPU on the Renesas RZ/V2N (R9A09G056) SoC. This includes adding clock sources required for the module clocks. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a09g056-cpg.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/clk/renesas/r9a09g056-cpg.c b/drivers/clk/renesas/r9a0= 9g056-cpg.c index 7e34c4259a6c..13b5db79aab4 100644 --- a/drivers/clk/renesas/r9a09g056-cpg.c +++ b/drivers/clk/renesas/r9a09g056-cpg.c @@ -29,6 +29,7 @@ enum clk_ids { CLK_PLLDTY, CLK_PLLCA55, CLK_PLLETH, + CLK_PLLGPU, =20 /* Internal Core Clocks */ CLK_PLLCM33_DIV16, @@ -36,6 +37,7 @@ enum clk_ids { CLK_PLLCLN_DIV8, CLK_PLLCLN_DIV16, CLK_PLLDTY_ACPU, + CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_DIV8, CLK_PLLETH_DIV_250_FIX, @@ -46,6 +48,7 @@ enum clk_ids { CLK_SMUX2_GBE0_RXCLK, CLK_SMUX2_GBE1_TXCLK, CLK_SMUX2_GBE1_RXCLK, + CLK_PLLGPU_GEAR, =20 /* Module Clocks */ MOD_CLK_BASE, @@ -93,6 +96,7 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __= initconst =3D { DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55), DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3), + DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU), =20 /* Internal Core Clocks */ DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), @@ -102,6 +106,7 @@ static const struct cpg_core_clk r9a09g056_core_clks[] = __initconst =3D { DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16), =20 DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dta= ble_2_64), + DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, = 2), DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, = 4), DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8), =20 @@ -116,6 +121,8 @@ static const struct cpg_core_clk r9a09g056_core_clks[] = __initconst =3D { DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_= gbe1_txclk), DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_= gbe1_rxclk), =20 + DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dta= ble_2_64), + /* Core Clocks */ DEF_FIXED("sys_0_pclk", R9A09G056_SYS_0_PCLK, CLK_QEXTAL, 1, 1), DEF_DDIV("ca55_0_coreclk0", R9A09G056_CA55_0_CORE_CLK0, CLK_PLLCA55, @@ -236,6 +243,12 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[]= __initconst =3D { BUS_MSTOP(8, BIT(6))), DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3, BUS_MSTOP(8, BIT(6))), + DEF_MOD("gpu_0_clk", CLK_PLLGPU_GEAR, 15, 0, 7, 16, + BUS_MSTOP(3, BIT(4))), + DEF_MOD("gpu_0_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17, + BUS_MSTOP(3, BIT(4))), + DEF_MOD("gpu_0_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18, + BUS_MSTOP(3, BIT(4))), }; =20 static const struct rzv2h_reset r9a09g056_resets[] __initconst =3D { @@ -269,6 +282,9 @@ static const struct rzv2h_reset r9a09g056_resets[] __in= itconst =3D { DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */ DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */ DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */ + DEF_RST(13, 13, 6, 14), /* GPU_0_RESETN */ + DEF_RST(13, 14, 6, 15), /* GPU_0_AXI_RESETN */ + DEF_RST(13, 15, 6, 16), /* GPU_0_ACE_RESETN */ }; =20 const struct rzv2h_cpg_info r9a09g056_cpg_info __initconst =3D { --=20 2.49.0