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Tue, 13 May 2025 04:12:18 -0700 (PDT) Date: Tue, 13 May 2025 13:12:02 +0200 In-Reply-To: <20250513111157.717727-8-ardb+git@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250513111157.717727-8-ardb+git@google.com> X-Developer-Key: i=ardb@kernel.org; a=openpgp; fpr=F43D03328115A198C90016883D200E9CA6329909 X-Developer-Signature: v=1; a=openpgp-sha256; l=4607; i=ardb@kernel.org; h=from:subject; bh=9j53WpWB7md8IeK5be3OARrIP92+C+LWx2Fx91Qse0c=; b=owGbwMvMwCFmkMcZplerG8N4Wi2JIUNZk5nvXoDgNGEO3hti0/iXqMlP5TleEMI22/p8Ade2E GZmS42OUhYGMQ4GWTFFFoHZf9/tPD1RqtZ5lizMHFYmkCEMXJwCMJF9BYwMW9YsrMj/zziXvbmz K27Nk+ocS6dNkj05j+bIst96dzw7jeF/wk3dA8ZS+gwBu3S+PrvgOKlogmr6L+uMr0uED8YFBZR xAgA= X-Mailer: git-send-email 2.49.0.1045.g170613ef41-goog Message-ID: <20250513111157.717727-12-ardb+git@google.com> Subject: [RFC PATCH v2 4/6] x86/boot: Set 5-level paging CPU cap before entering C code From: Ard Biesheuvel To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, Ard Biesheuvel , Ingo Molnar , Linus Torvalds Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel In order for pgtable_l5_enabled() to be reliable wherever it is used and however early, set the associated CPU capability from asm code before entering the startup C code. Signed-off-by: Ard Biesheuvel --- arch/x86/include/asm/cpufeature.h | 12 +++++++++--- arch/x86/kernel/asm-offsets.c | 8 ++++++++ arch/x86/kernel/asm-offsets_32.c | 9 --------- arch/x86/kernel/cpu/common.c | 3 --- arch/x86/kernel/head_64.S | 15 +++++++++++++++ 5 files changed, 32 insertions(+), 15 deletions(-) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufe= ature.h index 893cbca37fe9..1b5de40e7bf7 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -2,10 +2,10 @@ #ifndef _ASM_X86_CPUFEATURE_H #define _ASM_X86_CPUFEATURE_H =20 +#ifdef __KERNEL__ +#ifndef __ASSEMBLER__ #include =20 -#if defined(__KERNEL__) && !defined(__ASSEMBLER__) - #include #include #include @@ -137,5 +137,11 @@ static __always_inline bool _static_cpu_has(u16 bit) #define CPU_FEATURE_TYPEVAL boot_cpu_data.x86_vendor, boot_cpu_data.x86, \ boot_cpu_data.x86_model =20 -#endif /* defined(__KERNEL__) && !defined(__ASSEMBLER__) */ +#else /* !defined(__ASSEMBLER__) */ + .macro setup_force_cpu_cap, cap:req + btsl $\cap % 32, boot_cpu_data+CPUINFO_x86_capability+4*(\cap / 32)(%rip) + btsl $\cap % 32, cpu_caps_set+4*(\cap / 32)(%rip) + .endm +#endif /* !defined(__ASSEMBLER__) */ +#endif /* defined(__KERNEL__) */ #endif /* _ASM_X86_CPUFEATURE_H */ diff --git a/arch/x86/kernel/asm-offsets.c b/arch/x86/kernel/asm-offsets.c index ad4ea6fb3b6c..6259b474073b 100644 --- a/arch/x86/kernel/asm-offsets.c +++ b/arch/x86/kernel/asm-offsets.c @@ -33,6 +33,14 @@ =20 static void __used common(void) { + OFFSET(CPUINFO_x86, cpuinfo_x86, x86); + OFFSET(CPUINFO_x86_vendor, cpuinfo_x86, x86_vendor); + OFFSET(CPUINFO_x86_model, cpuinfo_x86, x86_model); + OFFSET(CPUINFO_x86_stepping, cpuinfo_x86, x86_stepping); + OFFSET(CPUINFO_cpuid_level, cpuinfo_x86, cpuid_level); + OFFSET(CPUINFO_x86_capability, cpuinfo_x86, x86_capability); + OFFSET(CPUINFO_x86_vendor_id, cpuinfo_x86, x86_vendor_id); + BLANK(); OFFSET(TASK_threadsp, task_struct, thread.sp); #ifdef CONFIG_STACKPROTECTOR diff --git a/arch/x86/kernel/asm-offsets_32.c b/arch/x86/kernel/asm-offsets= _32.c index 2b411cd00a4e..e0a292db97b2 100644 --- a/arch/x86/kernel/asm-offsets_32.c +++ b/arch/x86/kernel/asm-offsets_32.c @@ -12,15 +12,6 @@ void foo(void); =20 void foo(void) { - OFFSET(CPUINFO_x86, cpuinfo_x86, x86); - OFFSET(CPUINFO_x86_vendor, cpuinfo_x86, x86_vendor); - OFFSET(CPUINFO_x86_model, cpuinfo_x86, x86_model); - OFFSET(CPUINFO_x86_stepping, cpuinfo_x86, x86_stepping); - OFFSET(CPUINFO_cpuid_level, cpuinfo_x86, cpuid_level); - OFFSET(CPUINFO_x86_capability, cpuinfo_x86, x86_capability); - OFFSET(CPUINFO_x86_vendor_id, cpuinfo_x86, x86_vendor_id); - BLANK(); - OFFSET(PT_EBX, pt_regs, bx); OFFSET(PT_ECX, pt_regs, cx); OFFSET(PT_EDX, pt_regs, dx); diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index aaa6d9e51ef1..ea49322ba151 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1672,9 +1672,6 @@ static void __init early_identify_cpu(struct cpuinfo_= x86 *c) setup_clear_cpu_cap(X86_FEATURE_PCID); #endif =20 - if (IS_ENABLED(CONFIG_X86_5LEVEL) && (native_read_cr4() & X86_CR4_LA57)) - setup_force_cpu_cap(X86_FEATURE_5LEVEL_PAGING); - detect_nopl(); } =20 diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index 069420853304..b4742942bece 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -27,6 +27,7 @@ #include #include #include +#include =20 /* * We are not able to switch in one step to the final KERNEL ADDRESS SPACE @@ -58,6 +59,20 @@ SYM_CODE_START_NOALIGN(startup_64) */ mov %rsi, %r15 =20 +#ifdef CONFIG_X86_5LEVEL + /* + * Set the X86_FEATURE_5LEVEL_PAGING capability before calling into the + * C code, so that it is guaranteed to have a consistent view of any + * global pseudo-constants that are derived from pgtable_l5_enabled(). + */ + mov %cr4, %rax + btl $X86_CR4_LA57_BIT, %eax + jnc 0f + + setup_force_cpu_cap X86_FEATURE_5LEVEL_PAGING +0: +#endif + /* Set up the stack for verify_cpu() */ leaq __top_init_kernel_stack(%rip), %rsp =20 --=20 2.49.0.1045.g170613ef41-goog