From nobody Sun Feb 8 12:31:27 2026 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE59A23E342 for ; Tue, 13 May 2025 09:49:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747129799; cv=none; b=HLDnzXPmYnwBXEZBEjsGePxvsDYecZBvqIFu8K0aQ5q4mu8SwQWQ0IwsczcGnqDp9o93lX0VUkPuJgwqK4QQLD23jV6sWF5/xoaYyNMiOVby1bAP85zUzzIpAWRhBTpQv2Ggaq9RGb7v5OECD1AgsaY4/DC3a3TaBp2OOvhJtAg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747129799; c=relaxed/simple; bh=VbnAmLxBB+9ni3Y9B/gXoAlfLtNObeur1VJCWbvyhdM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DPtOOGs0PzVNc7gTMPXYNQRPdYiHo+Zs+YGU5CniPYMz2rT3hGz4p6pd1zCD0qSvSLLqW80EVLM1W0JC4pFfw3DirrtcAGaGeFFcOZ8o5tJnfQbvySasbR6+q+0IJwU0aTQSenZqogvcrTJr6hsiQFyblPawGNBLfFDeIXhv8rM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 54D9njYE044800 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 13 May 2025 17:49:45 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Tue, 13 May 2025 17:49:44 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , Ben Zong-You Xie Subject: [PATCH v3 1/9] riscv: add Andes SoC family Kconfig support Date: Tue, 13 May 2025 17:49:25 +0800 Message-ID: <20250513094933.1631493-2-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250513094933.1631493-1-ben717@andestech.com> References: <20250513094933.1631493-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 54D9njYE044800 Content-Type: text/plain; charset="utf-8" The first SoC in the Andes series is QiLai. It includes a high-performance quad-core RISC-V AX45MP cluster and one NX27V vector processor. For further information, refer to [1]. [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qil= ai-chip/ Signed-off-by: Ben Zong-You Xie --- arch/riscv/Kconfig.errata | 2 +- arch/riscv/Kconfig.socs | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index e318119d570d..be76883704a6 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -12,7 +12,7 @@ config ERRATA_ANDES =20 config ERRATA_ANDES_CMO bool "Apply Andes cache management errata" - depends on ERRATA_ANDES && ARCH_R9A07G043 + depends on ERRATA_ANDES && (ARCH_R9A07G043 || ARCH_ANDES) select RISCV_DMA_NONCOHERENT default y help diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index a9c3d2f6debc..1bf5637f2601 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -1,5 +1,14 @@ menu "SoC selection" =20 +config ARCH_ANDES + bool "Andes SoCs" + depends on MMU && !XIP_KERNEL + select ERRATA_ANDES + select ERRATA_ANDES_CMO + select AX45MP_L2_CACHE + help + This enables support for Andes SoC platform hardware. + config ARCH_MICROCHIP_POLARFIRE def_bool ARCH_MICROCHIP =20 --=20 2.34.1 From nobody Sun Feb 8 12:31:27 2026 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6424823C512 for ; Tue, 13 May 2025 09:49:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747129797; cv=none; b=I2vLaONbfd7Bpo9/NWq+k0zw5lwc3ZHmlxxX9LGe+ClIZ17tlUjgZQc+CqH91qwH7bM50S9g8Z4nCcW9U41CaIxTb8T8AZ//ny7PoKOfeOjfrRm702w8d+YzFmeqr8j9b0FKHozmAcMRLPkigT5SRXGW8HK+ND7pOsELM9EFWDw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747129797; c=relaxed/simple; bh=yzqm8sYUzNx5OEOtx6mbvv3KN216jilVVat1M/ReGHY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=IgUO+kxcINGaiKgus7QG4Zto/i8EJ3/SsDM0+hvXFIIm1BnoYebOThR3bGkATukGfTE3x7U2UdoeSt21bu2M+pc6jFmz+YbYIJJCs5MWdmRamlvuB+xthabXghYbo9O0Dx3F14AjEMdhaGR+mcQJEbuQs9VeNhizlbSBjCMqniE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 54D9nkN6044809 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 13 May 2025 17:49:46 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Tue, 13 May 2025 17:49:46 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , Ben Zong-You Xie Subject: [PATCH v3 2/9] dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings Date: Tue, 13 May 2025 17:49:26 +0800 Message-ID: <20250513094933.1631493-3-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250513094933.1631493-1-ben717@andestech.com> References: <20250513094933.1631493-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 54D9nkN6044809 Content-Type: text/plain; charset="utf-8" Add DT binding documentation for the Andes QiLai SoC and the Voyager development board. Reviewed-by: Rob Herring (Arm) Signed-off-by: Ben Zong-You Xie --- .../devicetree/bindings/riscv/andes.yaml | 25 +++++++++++++++++++ MAINTAINERS | 5 ++++ 2 files changed, 30 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/andes.yaml diff --git a/Documentation/devicetree/bindings/riscv/andes.yaml b/Documenta= tion/devicetree/bindings/riscv/andes.yaml new file mode 100644 index 000000000000..aa1edf1fdec7 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/andes.yaml @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/andes.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andes SoC-based boards + +maintainers: + - Ben Zong-You Xie + +description: + Andes SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - andestech,voyager + - const: andestech,qilai + +additionalProperties: true diff --git a/MAINTAINERS b/MAINTAINERS index 96b827049501..a0ccac1cca29 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20725,6 +20725,11 @@ F: drivers/irqchip/irq-riscv-intc.c F: include/linux/irqchip/riscv-aplic.h F: include/linux/irqchip/riscv-imsic.h +RISC-V ANDES SoC Support +M: Ben Zong-You Xie +S: Maintained +F: Documentation/devicetree/bindings/riscv/andes.yaml + RISC-V ARCHITECTURE M: Paul Walmsley M: Palmer Dabbelt -- 2.34.1 From nobody Sun Feb 8 12:31:27 2026 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E988C2417D4 for ; Tue, 13 May 2025 09:49:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747129802; cv=none; b=uWoPJOWBt16j4Pwd9J3oXSDBYqLRvUi3RBqkPtpH3AwBV7O/C8g1exPEY9odhM36gyaJtDRdoN/uA9uHiNghiaUaB1Y43uMxWGpplOVed26eu0DJYS116Z8956fmA/6VVflDncsmiTLWdYeBbkl4pxhlHJHAlkGqKg305uxVwA8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747129802; c=relaxed/simple; bh=b5uKANygrYv7VbDwymHsPSONF7altvL6n5B/jXaeNwM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=KGuU9+YDzwy6eOlDf88tSzE7ziuKfSUXDTIzdf9XNBEDnop3l9BvJZOQm2khxGgFmZRU60MYXZxsveS4sojapWDqAHSUaDNSUmmd1he/7p1D7SFgy5OpR5xgqjyVJ7BoQhXS4aqN3HItx8k/lei4e77kLtbypvtnvwvXpn3c4WQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 54D9nlSh044846 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 13 May 2025 17:49:47 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Tue, 13 May 2025 17:49:47 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , Ben Zong-You Xie Subject: [PATCH v3 3/9] dt-bindings: interrupt-controller: add Andes QiLai PLIC Date: Tue, 13 May 2025 17:49:27 +0800 Message-ID: <20250513094933.1631493-4-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250513094933.1631493-1-ben717@andestech.com> References: <20250513094933.1631493-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 54D9nlSh044846 Content-Type: text/plain; charset="utf-8" Add a new compatible string for Andes QiLai PLIC. Acked-by: Rob Herring (Arm) Signed-off-by: Ben Zong-You Xie --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,= plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/si= five,plic-1.0.0.yaml index 3dfe425909d1..7ae61518e9b7 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml @@ -53,6 +53,7 @@ properties: oneOf: - items: - enum: + - andestech,qilai-plic - renesas,r9a07g043-plic - const: andestech,nceplic100 - items: -- 2.34.1 From nobody Sun Feb 8 12:31:27 2026 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24F0E23E35D for ; Tue, 13 May 2025 09:50:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747129844; cv=none; b=PSmcmQRIFL9800YA0kSGxzpG9MhgjSfzslGR3Qitykzpwk5lW6PJbSl0ICg+8vI7hoFo6Pj6k9IryP+oOJQsQGkz4b5K+36zOnPeqUVnWvKT3harLfehMj2CKufJa1n1hK2pmaKt3Y6bssedHgZhx5TXmgwh0pYP518atSbPYuU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747129844; c=relaxed/simple; bh=2YncXzplbke0CiVuENDEMM/YVb58EgApc++U9eqskQA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=l/1WOrWc9cKYHr5yAZGum64W5NVLOlJaSsuJmnm/GVtiizdwvuagSMF6VJ8HIYF12OYHYkpkbD+hY3I8is6g+Lzg1GFgrpTXb3L9EvgomMvhZz9uwS6CRDar91BDlJKGmLvn4iUFHCmDe8PgKs616agEJDIMXAsUwBR6ZMgxV6Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 54D9nnDD044857 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 13 May 2025 17:49:49 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Tue, 13 May 2025 17:49:49 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , Ben Zong-You Xie , Conor Dooley Subject: [PATCH v3 4/9] dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller Date: Tue, 13 May 2025 17:49:28 +0800 Message-ID: <20250513094933.1631493-5-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250513094933.1631493-1-ben717@andestech.com> References: <20250513094933.1631493-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 54D9nnDD044857 Content-Type: text/plain; charset="utf-8" Add the DT binding documentation for Andes machine-level software interrupt controller. In the Andes platform such as QiLai SoC, the PLIC module is instantiated a second time with all interrupt sources tied to zero as the software interrupt controller (PLICSW). PLICSW can generate machine-level software interrupts through programming its registers. Acked-by: Conor Dooley Signed-off-by: Ben Zong-You Xie --- .../andestech,plicsw.yaml | 54 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= andestech,plicsw.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/andeste= ch,plicsw.yaml b/Documentation/devicetree/bindings/interrupt-controller/and= estech,plicsw.yaml new file mode 100644 index 000000000000..eb2eb611ac09 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/andestech,plic= sw.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/andestech,plicsw.y= aml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andes machine-level software interrupt controller + +description: + In the Andes platform such as QiLai SoC, the PLIC module is instantiated= a + second time with all interrupt sources tied to zero as the software inte= rrupt + controller (PLIC_SW). PLIC_SW directly connects to the machine-mode + inter-processor interrupt lines of CPUs, so RISC-V per-CPU local interru= pt + controller is the parent interrupt controller for PLIC_SW. PLIC_SW can + generate machine-mode inter-processor interrupts through programming its + registers. + +maintainers: + - Ben Zong-You Xie + +properties: + compatible: + items: + - enum: + - andestech,qilai-plicsw + - const: andestech,plicsw + + reg: + maxItems: 1 + + interrupts-extended: + minItems: 1 + maxItems: 15872 + description: + Specifies which harts are connected to the PLIC_SW. Each item must p= oints + to a riscv,cpu-intc node, which has a riscv cpu node as parent. + +additionalProperties: false + +required: + - compatible + - reg + - interrupts-extended + +examples: + - | + interrupt-controller@400000 { + compatible =3D "andestech,qilai-plicsw", "andestech,plicsw"; + reg =3D <0x400000 0x400000>; + interrupts-extended =3D <&cpu0intc 3>, + <&cpu1intc 3>, + <&cpu2intc 3>, + <&cpu3intc 3>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index a0ccac1cca29..645d7137cb07 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20728,6 +20728,7 @@ F: include/linux/irqchip/riscv-imsic.h RISC-V ANDES SoC Support M: Ben Zong-You Xie S: Maintained +F: Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw= .yaml F: Documentation/devicetree/bindings/riscv/andes.yaml RISC-V ARCHITECTURE -- 2.34.1 From nobody Sun Feb 8 12:31:27 2026 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29BF92441B8 for ; Tue, 13 May 2025 09:50:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747129847; cv=none; b=kSBRiEz5SSPDaCoTyd2YMSgdbdX3r0vFLbuVRN5rd4eu0DTCE67iuy9ELHtSU/Er5qdRSAcyhRpn/+OhPFtCik7kQ9QM2414+I1YFMNBW0n8tM1CIr81uqi3coqnEARRiLfhSPVeCbI3uoh35Nb86qDxndyoN0R8NFKSKlJM2E8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747129847; c=relaxed/simple; bh=pE00uCTIvhPmghgm1yPqWBS0KhYlBMQjtjn/MUMREMo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=JWdkKt/nwhG5icv+Rn9+eJcPdTM0vju9Ja0c0WdUJ0pExPoN8HMkUMrj2yrNXmqmAEAdZsWFDxVbC9rzvNhkRZBrnC4lO87cpP08FCJ1xgNCZBpJm7ZVetXaKmvKSV3M5Od5tbH6/Xmpq8SuvJCo37OimHC+e0D0UG1647iBd4w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 54D9noxM044858 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 13 May 2025 17:49:50 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Tue, 13 May 2025 17:49:50 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , Ben Zong-You Xie , Conor Dooley Subject: [PATCH v3 5/9] dt-bindings: timer: add Andes machine timer Date: Tue, 13 May 2025 17:49:29 +0800 Message-ID: <20250513094933.1631493-6-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250513094933.1631493-1-ben717@andestech.com> References: <20250513094933.1631493-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 54D9noxM044858 Content-Type: text/plain; charset="utf-8" Add the DT binding documentation for Andes machine timer. The RISC-V architecture defines a machine timer that provides a real-time counter and generates timer interrupts. Andes machiner timer (PLMT0) is the implementation of the machine timer, and it contains memory-mapped registers (mtime and mtimecmp). This device supports up to 32 cores. Acked-by: Conor Dooley Signed-off-by: Ben Zong-You Xie --- .../bindings/timer/andestech,plmt0.yaml | 53 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/andestech,plmt0= .yaml diff --git a/Documentation/devicetree/bindings/timer/andestech,plmt0.yaml b= /Documentation/devicetree/bindings/timer/andestech,plmt0.yaml new file mode 100644 index 000000000000..90b612096004 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/andestech,plmt0.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/andestech,plmt0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andes machine-level timer + +description: + The Andes machine-level timer device (PLMT0) provides machine-level timer + functionality for a set of HARTs on a RISC-V platform. It has a single + fixed-frequency monotonic time counter (MTIME) register and a time compa= re + register (MTIMECMP) for each HART connected to the PLMT0. A timer interr= upt is + generated if MTIME >=3D MTIMECMP. + +maintainers: + - Ben Zong-You Xie + +properties: + compatible: + items: + - enum: + - andestech,qilai-plmt + - const: andestech,plmt0 + + reg: + maxItems: 1 + + interrupts-extended: + minItems: 1 + maxItems: 32 + description: + Specifies which harts are connected to the PLMT0. Each item must poi= nts + to a riscv,cpu-intc node, which has a riscv cpu node as parent. The + PLMT0 supports 1 hart up to 32 harts. + +additionalProperties: false + +required: + - compatible + - reg + - interrupts-extended + +examples: + - | + interrupt-controller@100000 { + compatible =3D "andestech,qilai-plmt", "andestech,plmt0"; + reg =3D <0x100000 0x100000>; + interrupts-extended =3D <&cpu0intc 7>, + <&cpu1intc 7>, + <&cpu2intc 7>, + <&cpu3intc 7>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 645d7137cb07..d1e1b98dfe7b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20730,6 +20730,7 @@ M: Ben Zong-You Xie S: Maintained F: Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw= .yaml F: Documentation/devicetree/bindings/riscv/andes.yaml +F: Documentation/devicetree/bindings/timer/andestech,plmt0.yaml RISC-V ARCHITECTURE M: Paul Walmsley -- 2.34.1 From nobody Sun Feb 8 12:31:27 2026 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 254F71EB5E5 for ; Tue, 13 May 2025 09:50:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747129818; cv=none; b=np+6awn+jTdE/VGnUsJ8iL9GxN4258jLU5i1IYJ+lADx0HSjJ2E6+C0r43QT1ptWzHChaT6JPmKgNvC3iAI39tcam2WLlOinqBnbTE1avDho4cWU8ui/l3DfZSxP3PfW8l0hQeGo+5cdQxMrHaDB+zQBkSbmpP/tczDECkuGgZI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747129818; c=relaxed/simple; bh=TUKwT3goQGW7BgcxvA/BGgnrg1MvnylmSbViGWkZyUE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mFP0bB1E1HQSaXQTbVyA/BNFHdCgM31eMUl5g5ZGA1/iEA8VRZ0rvcZTCfpddIzzgloa6meifOphuQXmKJIF1uW3tA+gLEtITBzA6TewV+wU5hgBU+jhgZv1tPFh8O1t77jnuUFstTx+9AbX8jMYNyUgyGjIQ3s+EA0Zw1QDzYg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 54D9nqRh044911 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 13 May 2025 17:49:52 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Tue, 13 May 2025 17:49:51 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , Ben Zong-You Xie Subject: [PATCH v3 6/9] dt-bindings: cache: add QiLai compatible to ax45mp Date: Tue, 13 May 2025 17:49:30 +0800 Message-ID: <20250513094933.1631493-7-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250513094933.1631493-1-ben717@andestech.com> References: <20250513094933.1631493-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 54D9nqRh044911 Content-Type: text/plain; charset="utf-8" Add a new compatible string for ax45mp-cache on QiLai SoC. Also, add allOf constraints to enforce specific cache-sets and cache-size values for each compatible string. Signed-off-by: Ben Zong-You Xie --- .../cache/andestech,ax45mp-cache.yaml | 52 +++++++++++++++++-- 1 file changed, 47 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache= .yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml index df8bba14f758..dc03ffae6c9f 100644 --- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml @@ -28,7 +28,9 @@ select: properties: compatible: items: - - const: renesas,r9a07g043f-ax45mp-cache + - enum: + - andestech,qilai-ax45mp-cache + - renesas,r9a07g043f-ax45mp-cache - const: andestech,ax45mp-cache - const: cache =20 @@ -44,11 +46,9 @@ properties: cache-level: const: 2 =20 - cache-sets: - enum: [1024, 2048] + cache-sets: true =20 - cache-size: - enum: [131072, 262144, 524288, 1048576, 2097152] + cache-size: true =20 cache-unified: true =20 @@ -66,7 +66,49 @@ required: - cache-size - cache-unified =20 +allOf: + - if: + properties: + compatible: + contains: + const: andestech,qilai-ax45mp-cache + + then: + properties: + cache-sets: + const: 2048 + cache-size: + const: 2097152 + + - if: + properties: + compatible: + contains: + const: renesas,r9a07g043f-ax45mp-cache + + then: + properties: + cache-sets: + const: 1024 + cache-size: + const: 262144 + examples: + - | + #include + + l2_cache: cache-controller@200000 { + compatible =3D "andestech,qilai-ax45mp-cache", "andestech,ax45mp-c= ache", + "cache"; + reg =3D <0x00200000 0x100000>; + interrupts =3D <16 IRQ_TYPE_LEVEL_HIGH>; + cache-line-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <2048>; + cache-size =3D <2097152>; + cache-unified; + }; + - | #include =20 --=20 2.34.1 From nobody Sun Feb 8 12:31:27 2026 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD5A423C4F8 for ; Tue, 13 May 2025 09:50:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747129821; cv=none; b=mv+/10ge40kPG0PaF7jXWukoPp1omIWth3TPUxBQCiIIr8KQalv2Z/MTXjODWorHGQxIn0vItBFUlFjqZHFFhW4Rv8KBjKEsvv2nSLvKCkcozU7svXTIY9veGg47Rp7ew43nva1W4h8+z3Yf5cUZtHPfG8HNr5+IoVHhn1YL+RI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747129821; c=relaxed/simple; bh=cuDY3+5xTbWJxxT9kRqhaRAPrxvv8oStiu958NEBvRc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=at/BdS0TAs8FZkonzcUqPykEmkcf8uyAVjdc++PxO7FG+3peLIpcArleEJfRU8oqLRWh2xhjE+d1Y1ABZTFiprPBTYyq8ApEt2xNsnuunBnqew5nr+UnaBUYUWXhZKUTuubThfcb/T2aA05jRwMJzTNd9FLSU9NnG3Il04+Fo5A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 54D9nrVs044932 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 13 May 2025 17:49:53 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Tue, 13 May 2025 17:49:53 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , Ben Zong-You Xie Subject: [PATCH v3 7/9] riscv: dts: andes: add QiLai SoC device tree Date: Tue, 13 May 2025 17:49:31 +0800 Message-ID: <20250513094933.1631493-8-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250513094933.1631493-1-ben717@andestech.com> References: <20250513094933.1631493-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 54D9nrVs044932 Content-Type: text/plain; charset="utf-8" Introduce the initial device tree support for the Andes QiLai SoC. For further information, you can refer to [1]. [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qil= ai-chip/ Signed-off-by: Ben Zong-You Xie --- MAINTAINERS | 2 + arch/riscv/boot/dts/andes/qilai.dtsi | 186 +++++++++++++++++++++++++++ 2 files changed, 188 insertions(+) create mode 100644 arch/riscv/boot/dts/andes/qilai.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index d1e1b98dfe7b..fd3c2deed699 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20728,9 +20728,11 @@ F: include/linux/irqchip/riscv-imsic.h RISC-V ANDES SoC Support M: Ben Zong-You Xie S: Maintained +T: git: https://github.com/ben717-linux/linux F: Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw= .yaml F: Documentation/devicetree/bindings/riscv/andes.yaml F: Documentation/devicetree/bindings/timer/andestech,plmt0.yaml +F: arch/riscv/boot/dts/andes/ =20 RISC-V ARCHITECTURE M: Paul Walmsley diff --git a/arch/riscv/boot/dts/andes/qilai.dtsi b/arch/riscv/boot/dts/and= es/qilai.dtsi new file mode 100644 index 000000000000..de3de32f8c39 --- /dev/null +++ b/arch/riscv/boot/dts/andes/qilai.dtsi @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Andes Technology Corporation. All rights reserved. + */ + +/dts-v1/; + +#include + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <62500000>; + + cpu0: cpu@0 { + compatible =3D "andestech,ax45mp", "riscv"; + device_type =3D "cpu"; + reg =3D <0>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm", "xandespmu"; + mmu-type =3D "riscv,sv39"; + clock-frequency =3D <100000000>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <256>; + i-cache-line-size =3D <64>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <128>; + d-cache-line-size =3D <64>; + next-level-cache =3D <&l2_cache>; + + cpu0_intc: interrupt-controller { + compatible =3D "andestech,cpu-intc", "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu1: cpu@1 { + compatible =3D "andestech,ax45mp", "riscv"; + device_type =3D "cpu"; + reg =3D <1>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm", "xandespmu"; + mmu-type =3D "riscv,sv39"; + clock-frequency =3D <100000000>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <256>; + i-cache-line-size =3D <64>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <128>; + d-cache-line-size =3D <64>; + next-level-cache =3D <&l2_cache>; + + cpu1_intc: interrupt-controller { + compatible =3D "andestech,cpu-intc", + "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu2: cpu@2 { + compatible =3D "andestech,ax45mp", "riscv"; + device_type =3D "cpu"; + reg =3D <2>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm", "xandespmu"; + mmu-type =3D "riscv,sv39"; + clock-frequency =3D <100000000>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <256>; + i-cache-line-size =3D <64>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <128>; + d-cache-line-size =3D <64>; + next-level-cache =3D <&l2_cache>; + + cpu2_intc: interrupt-controller { + compatible =3D "andestech,cpu-intc", + "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu3: cpu@3 { + compatible =3D "andestech,ax45mp", "riscv"; + device_type =3D "cpu"; + reg =3D <3>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm", "xandespmu"; + mmu-type =3D "riscv,sv39"; + clock-frequency =3D <100000000>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <256>; + i-cache-line-size =3D <64>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <128>; + d-cache-line-size =3D <64>; + next-level-cache =3D <&l2_cache>; + + cpu3_intc: interrupt-controller { + compatible =3D "andestech,cpu-intc", + "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + }; + + soc { + compatible =3D "simple-bus"; + ranges; + interrupt-parent =3D <&plic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + plmt: timer@100000 { + compatible =3D "andestech,qilai-plmt", "andestech,plmt0"; + reg =3D <0x0 0x00100000 0x0 0x100000>; + interrupts-extended =3D <&cpu0_intc 7>, + <&cpu1_intc 7>, + <&cpu2_intc 7>, + <&cpu3_intc 7>; + }; + + l2_cache: cache-controller@200000 { + compatible =3D "andestech,qilai-ax45mp-cache", + "andestech,ax45mp-cache", "cache"; + reg =3D <0x0 0x00200000 0x0 0x100000>; + interrupts =3D <16 IRQ_TYPE_LEVEL_HIGH>; + cache-line-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <2048>; + cache-size =3D <0x200000>; + cache-unified; + }; + + plic_sw: interrupt-controller@400000 { + compatible =3D "andestech,qilai-plicsw", + "andestech,plicsw"; + reg =3D <0x0 0x00400000 0x0 0x400000>; + interrupts-extended =3D <&cpu0_intc 3>, + <&cpu1_intc 3>, + <&cpu2_intc 3>, + <&cpu3_intc 3>; + }; + + plic: interrupt-controller@2000000 { + compatible =3D "andestech,qilai-plic", + "andestech,nceplic100"; + reg =3D <0x0 0x02000000 0x0 0x2000000>; + #address-cells =3D <0>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>; + riscv,ndev =3D <71>; + }; + + uart0: serial@30300000 { + compatible =3D "andestech,uart16550", "ns16550a"; + reg =3D <0x0 0x30300000 0x0 0x100000>; + interrupts =3D <9 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency =3D <50000000>; + reg-offset =3D <32>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + no-loopback-test; + }; + }; +}; --=20 2.34.1 From nobody Sun Feb 8 12:31:27 2026 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0DCEC242D6E for ; Tue, 13 May 2025 09:50:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Tue, 13 May 2025 17:49:54 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Tue, 13 May 2025 17:49:54 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , Ben Zong-You Xie Subject: [PATCH v3 8/9] riscv: dts: andes: add Voyager board device tree Date: Tue, 13 May 2025 17:49:32 +0800 Message-ID: <20250513094933.1631493-9-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250513094933.1631493-1-ben717@andestech.com> References: <20250513094933.1631493-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 54D9nshY044934 Content-Type: text/plain; charset="utf-8" Introduce the device tree support for Voyager development board. Currently only support booting into console with only uart, other features will be added later. Signed-off-by: Ben Zong-You Xie --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/andes/Makefile | 2 ++ arch/riscv/boot/dts/andes/qilai-voyager.dts | 28 +++++++++++++++++++++ 3 files changed, 31 insertions(+) create mode 100644 arch/riscv/boot/dts/andes/Makefile create mode 100644 arch/riscv/boot/dts/andes/qilai-voyager.dts diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index 64a898da9aee..3b99e91efa25 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 subdir-y +=3D allwinner +subdir-y +=3D andes subdir-y +=3D canaan subdir-y +=3D microchip subdir-y +=3D renesas diff --git a/arch/riscv/boot/dts/andes/Makefile b/arch/riscv/boot/dts/andes= /Makefile new file mode 100644 index 000000000000..c545c668ef70 --- /dev/null +++ b/arch/riscv/boot/dts/andes/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ANDES) +=3D qilai-voyager.dtb diff --git a/arch/riscv/boot/dts/andes/qilai-voyager.dts b/arch/riscv/boot/= dts/andes/qilai-voyager.dts new file mode 100644 index 000000000000..fa7d2b32a9b4 --- /dev/null +++ b/arch/riscv/boot/dts/andes/qilai-voyager.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 Andes Technology Corporation. All rights reserved. + */ + +#include "qilai.dtsi" + +/ { + model =3D "Voyager"; + compatible =3D "andestech,voyager", "andestech,qilai"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory@400000000 { + device_type =3D "memory"; + reg =3D <0x4 0x00000000 0x4 0x00000000>; + }; +}; + +&uart0 { + status =3D "okay"; +}; --=20 2.34.1 From nobody Sun Feb 8 12:31:27 2026 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED31723A9BE for ; Tue, 13 May 2025 09:50:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747129858; cv=none; b=JcnBBj9hXPQWJB5BQ9fSbO4ak2MS416c3d4tgowgZEeV7DZydSt/ZrRHATmsyxx5KfHsaucezSG90aHAziTLL+pIkvydfj7BMNM5yC5mEEZ9+XMMa8HO/d2zbzYYf0qfrntIzqeekrP81vpdl5EeqsxHwlRaqfWBa2DXKyIP+Z0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747129858; c=relaxed/simple; bh=MUNzFZca4jP1Wzj7p7OSBhZbTeKUQVOelMr5pj0uSLM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=uEJH8ik139JYmJ/t3SheZBiq9+42y6zMeydFX7Ra2VmCvg3qT0BKkbfrz787ZCIkqrHOjIxvsGIfjSS+NoyoaMfapkymDtDFmL3ggW77Pk1EvuJjcOxNvkFpA6wlKPFz4DmtJdD/SWqLpllUTDAwUoG3Djki7gZjDRNW64L10/Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 54D9ntro044935 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 13 May 2025 17:49:55 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Tue, 13 May 2025 17:49:55 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , Ben Zong-You Xie , Conor Dooley Subject: [PATCH v3 9/9] riscv: defconfig: enable Andes SoC Date: Tue, 13 May 2025 17:49:33 +0800 Message-ID: <20250513094933.1631493-10-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250513094933.1631493-1-ben717@andestech.com> References: <20250513094933.1631493-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 54D9ntro044935 Content-Type: text/plain; charset="utf-8" Enable Andes SoC config in defconfig to allow the default upstream kernel to boot on Voyager board. Acked-by: Conor Dooley Signed-off-by: Ben Zong-You Xie --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index eea825ee58e1..29a97cbf4ee6 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -25,6 +25,7 @@ CONFIG_BLK_DEV_INITRD=3Dy CONFIG_EXPERT=3Dy # CONFIG_SYSFS_SYSCALL is not set CONFIG_PROFILING=3Dy +CONFIG_ARCH_ANDES=3Dy CONFIG_ARCH_MICROCHIP=3Dy CONFIG_ARCH_SIFIVE=3Dy CONFIG_ARCH_SOPHGO=3Dy -- 2.34.1