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charset="utf-8" In preparation for the upcoming driver update, we need to relocate the current driver. This will help ensure a clean transition and avoid any potential conflicts with the new driver. This patch is crucial for keeping our directory organized and facilitating a smooth integration of the new driver. Signed-off-by: Yassine Ouaissa --- MAINTAINERS | 2 +- drivers/media/platform/allegro-dvt/Kconfig | 16 +--------------- drivers/media/platform/allegro-dvt/Makefile | 5 +---- .../media/platform/allegro-dvt/zynqmp/Kconfig | 17 +++++++++++++++++ .../media/platform/allegro-dvt/zynqmp/Makefile | 6 ++++++ .../allegro-dvt/{ =3D> zynqmp}/allegro-core.c | 0 .../allegro-dvt/{ =3D> zynqmp}/allegro-mail.c | 0 .../allegro-dvt/{ =3D> zynqmp}/allegro-mail.h | 0 .../allegro-dvt/{ =3D> zynqmp}/nal-h264.c | 0 .../allegro-dvt/{ =3D> zynqmp}/nal-h264.h | 0 .../allegro-dvt/{ =3D> zynqmp}/nal-hevc.c | 0 .../allegro-dvt/{ =3D> zynqmp}/nal-hevc.h | 0 .../allegro-dvt/{ =3D> zynqmp}/nal-rbsp.c | 0 .../allegro-dvt/{ =3D> zynqmp}/nal-rbsp.h | 0 14 files changed, 26 insertions(+), 20 deletions(-) create mode 100644 drivers/media/platform/allegro-dvt/zynqmp/Kconfig create mode 100644 drivers/media/platform/allegro-dvt/zynqmp/Makefile rename drivers/media/platform/allegro-dvt/{ =3D> zynqmp}/allegro-core.c (1= 00%) rename drivers/media/platform/allegro-dvt/{ =3D> zynqmp}/allegro-mail.c (1= 00%) rename drivers/media/platform/allegro-dvt/{ =3D> zynqmp}/allegro-mail.h (1= 00%) rename drivers/media/platform/allegro-dvt/{ =3D> zynqmp}/nal-h264.c (100%) rename drivers/media/platform/allegro-dvt/{ =3D> zynqmp}/nal-h264.h (100%) rename drivers/media/platform/allegro-dvt/{ =3D> zynqmp}/nal-hevc.c (100%) rename drivers/media/platform/allegro-dvt/{ =3D> zynqmp}/nal-hevc.h (100%) rename drivers/media/platform/allegro-dvt/{ =3D> zynqmp}/nal-rbsp.c (100%) rename drivers/media/platform/allegro-dvt/{ =3D> zynqmp}/nal-rbsp.h (100%) diff --git a/MAINTAINERS b/MAINTAINERS index fa1e04e87d1d..d81d2756cb2e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -806,7 +806,7 @@ R: Pengutronix Kernel Team L: linux-media@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/media/allegro,al5e.yaml -F: drivers/media/platform/allegro-dvt/ +F: drivers/media/platform/allegro-dvt/zynqmp =20 ALLIED VISION ALVIUM CAMERA DRIVER M: Tommaso Merciai diff --git a/drivers/media/platform/allegro-dvt/Kconfig b/drivers/media/pla= tform/allegro-dvt/Kconfig index 2182e1277568..e9008614c27b 100644 --- a/drivers/media/platform/allegro-dvt/Kconfig +++ b/drivers/media/platform/allegro-dvt/Kconfig @@ -2,18 +2,4 @@ =20 comment "Allegro DVT media platform drivers" =20 -config VIDEO_ALLEGRO_DVT - tristate "Allegro DVT Video IP Core" - depends on V4L_MEM2MEM_DRIVERS - depends on VIDEO_DEV - depends on ARCH_ZYNQMP || COMPILE_TEST - select V4L2_MEM2MEM_DEV - select VIDEOBUF2_DMA_CONTIG - select REGMAP_MMIO - help - Support for the encoder video IP core by Allegro DVT. This core is - found for example on the Xilinx ZynqMP SoC in the EV family and is - called VCU in the reference manual. - - To compile this driver as a module, choose M here: the module - will be called allegro. +source "drivers/media/platform/allegro-dvt/zynqmp/Kconfig" diff --git a/drivers/media/platform/allegro-dvt/Makefile b/drivers/media/pl= atform/allegro-dvt/Makefile index 66108a303774..d2aa6875edcf 100644 --- a/drivers/media/platform/allegro-dvt/Makefile +++ b/drivers/media/platform/allegro-dvt/Makefile @@ -1,6 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 =20 -allegro-objs :=3D allegro-core.o allegro-mail.o -allegro-objs +=3D nal-rbsp.o nal-h264.o nal-hevc.o - -obj-$(CONFIG_VIDEO_ALLEGRO_DVT) +=3D allegro.o +obj-y +=3D zynqmp/ diff --git a/drivers/media/platform/allegro-dvt/zynqmp/Kconfig b/drivers/me= dia/platform/allegro-dvt/zynqmp/Kconfig new file mode 100644 index 000000000000..0a0a697c420d --- /dev/null +++ b/drivers/media/platform/allegro-dvt/zynqmp/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config VIDEO_ALLEGRO_DVT + tristate "Allegro DVT Video IP Core for ZynqMP" + depends on V4L_MEM2MEM_DRIVERS + depends on VIDEO_DEV + depends on ARCH_ZYNQMP || COMPILE_TEST + select V4L2_MEM2MEM_DEV + select VIDEOBUF2_DMA_CONTIG + select REGMAP_MMIO + help + Support for the encoder video IP core by Allegro DVT. This core is + found for example on the Xilinx ZynqMP SoC in the EV family and is + called VCU in the reference manual. + + To compile this driver as a module, choose M here: the module + will be called allegro. diff --git a/drivers/media/platform/allegro-dvt/zynqmp/Makefile b/drivers/m= edia/platform/allegro-dvt/zynqmp/Makefile new file mode 100644 index 000000000000..66108a303774 --- /dev/null +++ b/drivers/media/platform/allegro-dvt/zynqmp/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 + +allegro-objs :=3D allegro-core.o allegro-mail.o +allegro-objs +=3D nal-rbsp.o nal-h264.o nal-hevc.o + +obj-$(CONFIG_VIDEO_ALLEGRO_DVT) +=3D allegro.o diff --git a/drivers/media/platform/allegro-dvt/allegro-core.c b/drivers/me= dia/platform/allegro-dvt/zynqmp/allegro-core.c similarity index 100% rename from drivers/media/platform/allegro-dvt/allegro-core.c rename to drivers/media/platform/allegro-dvt/zynqmp/allegro-core.c diff --git a/drivers/media/platform/allegro-dvt/allegro-mail.c b/drivers/me= dia/platform/allegro-dvt/zynqmp/allegro-mail.c similarity index 100% rename from drivers/media/platform/allegro-dvt/allegro-mail.c rename to drivers/media/platform/allegro-dvt/zynqmp/allegro-mail.c diff --git a/drivers/media/platform/allegro-dvt/allegro-mail.h b/drivers/me= dia/platform/allegro-dvt/zynqmp/allegro-mail.h similarity index 100% rename from drivers/media/platform/allegro-dvt/allegro-mail.h rename to drivers/media/platform/allegro-dvt/zynqmp/allegro-mail.h diff --git a/drivers/media/platform/allegro-dvt/nal-h264.c b/drivers/media/= platform/allegro-dvt/zynqmp/nal-h264.c similarity index 100% rename from drivers/media/platform/allegro-dvt/nal-h264.c rename to drivers/media/platform/allegro-dvt/zynqmp/nal-h264.c diff --git a/drivers/media/platform/allegro-dvt/nal-h264.h b/drivers/media/= platform/allegro-dvt/zynqmp/nal-h264.h similarity index 100% rename from drivers/media/platform/allegro-dvt/nal-h264.h rename to drivers/media/platform/allegro-dvt/zynqmp/nal-h264.h diff --git a/drivers/media/platform/allegro-dvt/nal-hevc.c b/drivers/media/= platform/allegro-dvt/zynqmp/nal-hevc.c similarity index 100% rename from drivers/media/platform/allegro-dvt/nal-hevc.c rename to drivers/media/platform/allegro-dvt/zynqmp/nal-hevc.c diff --git a/drivers/media/platform/allegro-dvt/nal-hevc.h b/drivers/media/= platform/allegro-dvt/zynqmp/nal-hevc.h similarity index 100% rename from drivers/media/platform/allegro-dvt/nal-hevc.h rename to drivers/media/platform/allegro-dvt/zynqmp/nal-hevc.h diff --git a/drivers/media/platform/allegro-dvt/nal-rbsp.c b/drivers/media/= platform/allegro-dvt/zynqmp/nal-rbsp.c similarity index 100% rename from drivers/media/platform/allegro-dvt/nal-rbsp.c rename to drivers/media/platform/allegro-dvt/zynqmp/nal-rbsp.c diff --git a/drivers/media/platform/allegro-dvt/nal-rbsp.h b/drivers/media/= platform/allegro-dvt/zynqmp/nal-rbsp.h similarity index 100% rename from drivers/media/platform/allegro-dvt/nal-rbsp.h rename to drivers/media/platform/allegro-dvt/zynqmp/nal-rbsp.h --=20 2.30.2 From nobody Mon Feb 9 14:16:01 2026 Received: from PA5P264CU001.outbound.protection.outlook.com (mail-francecentralazon11020076.outbound.protection.outlook.com [52.101.167.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E645820DD7D; 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charset="utf-8" Add allegrodvt vendor prefix so it may be used in future device. compatibles Signed-off-by: Yassine Ouaissa --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 86f6a19b28ae..90bc1ec721ed 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -81,7 +81,7 @@ patternProperties: description: Aldec, Inc. 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charset="utf-8" Add compatible for video decoder on allegrodvt Gen 3 IP. Signed-off-by: Yassine Ouaissa --- .../bindings/media/allegrodvt,al300-vdec.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/allegrodvt,al30= 0-vdec.yaml diff --git a/Documentation/devicetree/bindings/media/allegrodvt,al300-vdec.= yaml b/Documentation/devicetree/bindings/media/allegrodvt,al300-vdec.yaml new file mode 100644 index 000000000000..4218892d6950 --- /dev/null +++ b/Documentation/devicetree/bindings/media/allegrodvt,al300-vdec.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/allegrodvt,al300-vdec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allegro DVT Video IP Decoder Gen 3 + +maintainers: + - Yassine OUAISSA + +description: + The al300-vdec represents the latest generation of Allegro DVT IP decodi= ng + technology, offering significant advancements over its predecessors. + This new decoder features enhanced processing capabilities with improved + throughput and reduced latency. + + Communication between the host driver software and the MCU is implemented + through a specialized mailbox interface mechanism. This mailbox system + provides a structured channel for exchanging commands, parameters, and + status information between the host CPU and the MCU controlling the codec + engines. + +properties: + compatible: + const: allegrodvt,al300-vdec + + reg: + items: + - description: The registers + - description: the MCU APB register + + reg-names: + items: + - const: regs + - const: apb + + interrupts: + maxItems: 1 + + clocks: + items: + - description: MCU clock + + clock-names: + items: + - const: mcu_clk + + memory-region: + maxItems: 1 + + firmware-name: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - interrupts + - clocks + - clock-names + +additionalProperties: False + +examples: + - | + axi { + #address-cells =3D <2>; + #size-cells =3D <2>; + + ald300@a0120000 { + compatible =3D "allegrodvt,al300-vdec"; + reg =3D <0 0xa0120000 0 0x10000>, + <1 0x80000000 0 0x80000>; + reg-names =3D "regs", "apb"; + interrupts =3D <0 96 4>; + clocks =3D <&mcu_clock_dec>; + clock-names =3D "mcu_clk"; + firmware-name =3D "al300_vdec.fw"; + }; + }; + +... --=20 2.30.2 From nobody Mon Feb 9 14:16:01 2026 Received: from PA5P264CU001.outbound.protection.outlook.com (mail-francecentralazon11020088.outbound.protection.outlook.com [52.101.167.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 030B01E9B14; Tue, 13 May 2025 08:37:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.167.88 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747125471; cv=fail; b=Z9wxHCFR6rLFEqNegqmeqRfUSKUFdhRWaEFDiRXvcq2lw21/2HpJlJlJEv6EmdiG7StaSqIILsgKutAe+rp3lbDfIZbPFYJ2VZF2nibEVGM+tOND7Bks3RJ+5hMRwdeM9uyMXQbrwafAd2GaI/bmILuHQClQDlTDV2Aud2yQ95c= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747125471; c=relaxed/simple; bh=UM3lN1bOo4EWavrguOCzNa8IwjQNCxdcNP2RV90cxoE=; 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Michael Tretter , Yassine OUAISSA , Pengutronix Kernel Team , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Simek , Neil Armstrong , Heiko Stuebner , Aradhya Bhatia , =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= , Junhao Xie , Manivannan Sadhasivam , Kever Yang , Hans Verkuil , Joe Hattori , Gaosheng Cui , Sebastian Fricke , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Christophe JAILLET , Wolfram Sang , Ricardo Ribalda , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [RESEND PATCH 5/5] media: allegro-dvt: Add Gen 3 IP stateful decoder driver Date: Tue, 13 May 2025 10:35:50 +0200 Message-Id: <20250513083609.328422-6-yassine.ouaissa@allegrodvt.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20250513083609.328422-1-yassine.ouaissa@allegrodvt.com> References: <20250513083609.328422-1-yassine.ouaissa@allegrodvt.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: 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formats: NV12, NV16, I420, and P010 for capture Signed-off-by: Yassine Ouaissa --- drivers/media/platform/allegro-dvt/Kconfig | 1 + drivers/media/platform/allegro-dvt/Makefile | 1 + .../media/platform/allegro-dvt/al300/Kconfig | 12 + .../media/platform/allegro-dvt/al300/Makefile | 6 + .../allegro-dvt/al300/al_codec_common.c | 789 +++++++++ .../allegro-dvt/al300/al_codec_common.h | 226 +++ .../allegro-dvt/al300/al_codec_util.c | 179 ++ .../allegro-dvt/al300/al_codec_util.h | 186 ++ .../platform/allegro-dvt/al300/al_vdec_drv.c | 1533 +++++++++++++++++ .../platform/allegro-dvt/al300/al_vdec_drv.h | 94 + 10 files changed, 3027 insertions(+) create mode 100644 drivers/media/platform/allegro-dvt/al300/Kconfig create mode 100644 drivers/media/platform/allegro-dvt/al300/Makefile create mode 100644 drivers/media/platform/allegro-dvt/al300/al_codec_commo= n.c create mode 100644 drivers/media/platform/allegro-dvt/al300/al_codec_commo= n.h create mode 100644 drivers/media/platform/allegro-dvt/al300/al_codec_util.c create mode 100644 drivers/media/platform/allegro-dvt/al300/al_codec_util.h create mode 100644 drivers/media/platform/allegro-dvt/al300/al_vdec_drv.c create mode 100644 drivers/media/platform/allegro-dvt/al300/al_vdec_drv.h diff --git a/drivers/media/platform/allegro-dvt/Kconfig b/drivers/media/pla= tform/allegro-dvt/Kconfig index e9008614c27b..0d01ed0ad08a 100644 --- a/drivers/media/platform/allegro-dvt/Kconfig +++ b/drivers/media/platform/allegro-dvt/Kconfig @@ -2,4 +2,5 @@ =20 comment "Allegro DVT media platform drivers" =20 +source "drivers/media/platform/allegro-dvt/al300/Kconfig" source "drivers/media/platform/allegro-dvt/zynqmp/Kconfig" diff --git a/drivers/media/platform/allegro-dvt/Makefile b/drivers/media/pl= atform/allegro-dvt/Makefile index d2aa6875edcf..c70ca19a47fb 100644 --- a/drivers/media/platform/allegro-dvt/Makefile +++ b/drivers/media/platform/allegro-dvt/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 =20 +obj-y +=3D al300/ obj-y +=3D zynqmp/ diff --git a/drivers/media/platform/allegro-dvt/al300/Kconfig b/drivers/med= ia/platform/allegro-dvt/al300/Kconfig new file mode 100644 index 000000000000..74bafb286250 --- /dev/null +++ b/drivers/media/platform/allegro-dvt/al300/Kconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config VIDEO_ALLEGRO_DVT_D300 + tristate "Allegro DVT Video IP Decode Gen 3" + depends on V4L_MEM2MEM_DRIVERS + depends on VIDEO_DEV && OF && HAS_DMA + select V4L2_MEM2MEM_DEV + select VIDEOBUF2_DMA_CONTIG + select REGMAP_MMIO + help + This is a video4linux2 driver for the Allegro DVT IP Decode Gen 3, + that support codecs : AVC (H.264), HEVC (H.265), and JPEG. diff --git a/drivers/media/platform/allegro-dvt/al300/Makefile b/drivers/me= dia/platform/allegro-dvt/al300/Makefile new file mode 100644 index 000000000000..3c50caccb731 --- /dev/null +++ b/drivers/media/platform/allegro-dvt/al300/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 + +al300-vdec-objs :=3D al_codec_common.o al_codec_util.o +al300-vdec-objs +=3D al_vdec_drv.o + +obj-$(CONFIG_VIDEO_ALLEGRO_DVT_D300) +=3D al300-vdec.o diff --git a/drivers/media/platform/allegro-dvt/al300/al_codec_common.c b/d= rivers/media/platform/allegro-dvt/al300/al_codec_common.c new file mode 100644 index 000000000000..8c0700dd8abf --- /dev/null +++ b/drivers/media/platform/allegro-dvt/al300/al_codec_common.c @@ -0,0 +1,789 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Core MCU functionality including firmware loading, + * memory allocation, and general MCU interaction interfaces + * + * Copyright (c) 2025 Allegro DVT. + * Author: Yassine OUAISSA + */ +#include +#include +#include +#include +#include +#include +#include + +#include "al_codec_common.h" + +#define AL_CODEC_UID 0x0000 +#define AL_CODEC_UID_ID 0x30AB6E51 +#define AL_CODEC_RESET 0x0010 +#define AL_CODEC_RESET_CMD BIT(0) +#define AL_CODEC_COMM_MASK BIT(0) +#define AL_CODEC_IRQ_MASK 0x0014 +#define AL_CODEC_IRQ_STATUS_CLEAR 0x0018 +#define AL_CODEC_IRQ_MCU_2_CPU BIT(30) +#define AL_CODEC_MCU_CLK 0x0400 +#define AL_CODEC_MCU_CLK_ENABLE BIT(0) +#define AL_CODEC_MCU_CLK_DISABLE 0 +#define AL_CODEC_MCU_RST 0x0404 +#define AL_CODEC_MCU_RST_ENABLE BIT(0) +#define AL_CODEC_MCU_RST_DISABLE 0 +#define AL_CODEC_MCU_IRQ 0x040C +#define AL_CODEC_MCU_BOOT_ADDR 0x0410 +#define AL_CODEC_MCU_APB_ADDR 0x0418 +#define AL_CODEC_MCU_PERIPHERAL_ADDR 0x0428 +#define AL_CODEC_MCU_IP_INTERRUPT_MASK 0x0440 +#define AL_CODEC_INSTRUCTION_DATA_OFFSET 0x0450 +#define AL_CODEC_IP_OFFSET GENMASK(26, 25) +#define AL_CODEC_APB_MASK GENMASK(26, 0) +#define AL_CODEC_MAX_ADDR GENMASK_ULL(38, 0) + +#define AL_CODEC_MCU_BOOT_RESET_WAIT 2 /* in ms */ + +/* + * struct codec_dma_buf - Allocated dma buffer + * + * @list: list head for buffer queue + * @paddr: physical address of the allcated DMA buffer + * @vaddr: virtual address of the allocated DMA buffer + * @size: Size of allocated dma memory + */ +struct codec_dma_buf { + void *vaddr; + dma_addr_t paddr; + u32 size; + struct list_head list; +}; + +struct mb_header { + u64 start; + u64 end; +} __packed; + +struct boot_header { + u32 bh_version; + u32 fw_version; + char model[16]; + u64 vaddr_start; + u64 vaddr_end; + u64 vaddr_boot; + struct mb_header h2m; + struct mb_header m2h; + u64 machine_id; + /* fill by driver before fw boot */ + u64 ip_start; + u64 ip_end; + u64 mcu_clk_rate; +} __packed; + +/* Regmap config */ +static const struct regmap_config al_regmap_config =3D { + .name =3D "regs", + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .max_register =3D 0xfff, + .fast_io =3D true, + .cache_type =3D REGCACHE_NONE, + .can_multi_write =3D true, +}; + +static inline int al_common_read(struct al_common_dev *dev, u32 offset, + u32 *val) +{ + return regmap_read(dev->regmap, offset, val); +} + +static inline int al_common_write(struct al_common_dev *dev, u32 offset, + u32 val) +{ + return regmap_write(dev->regmap, offset, val); +} + +static inline int al_common_write_multiple(struct al_common_dev *dev, + u32 offset, const void *val, + u32 num_regs) +{ + return regmap_bulk_write(dev->regmap, offset, val, num_regs); +} + +static inline int common_update_bits(struct al_common_dev *dev, u32 offset, + u32 mask, u32 val) +{ + return regmap_update_bits(dev->regmap, offset, mask, val); +} + +static void common_trigger_mcu_irq(void *arg) +{ + struct al_common_dev *dev =3D arg; + + common_update_bits(dev, AL_CODEC_MCU_IRQ, AL_CODEC_COMM_MASK, BIT(0)); +} + +static void common_reset(struct al_common_dev *dev) +{ + /* reset ip */ + common_update_bits(dev, AL_CODEC_RESET, AL_CODEC_COMM_MASK, + AL_CODEC_RESET_CMD); + + /* reset and stop mcu */ + al_common_write(dev, AL_CODEC_MCU_CLK, AL_CODEC_MCU_CLK_ENABLE); + al_common_write(dev, AL_CODEC_MCU_RST, AL_CODEC_MCU_RST_ENABLE); + /* time to reset the mct */ + mdelay(AL_CODEC_MCU_BOOT_RESET_WAIT); + al_common_write(dev, AL_CODEC_MCU_CLK, AL_CODEC_MCU_CLK_DISABLE); + + common_update_bits(dev, AL_CODEC_MCU_IRQ, AL_CODEC_COMM_MASK, 0); + al_common_write(dev, AL_CODEC_MCU_IP_INTERRUPT_MASK, 0); + + mdelay(AL_CODEC_MCU_BOOT_RESET_WAIT * 5); + common_update_bits(dev, AL_CODEC_MCU_RST, AL_CODEC_COMM_MASK, + AL_CODEC_MCU_RST_DISABLE); +} + +static int common_probe_check_and_setup_hw(struct al_common_dev *dev) +{ + unsigned int id; + int ret; + + /* Check regmap */ + if (WARN_ON(!dev->regmap)) + return -EINVAL; + + ret =3D al_common_read(dev, AL_CODEC_UID, &id); + + if (ret) + return ret; + + if (id !=3D AL_CODEC_UID_ID) { + al_codec_err(dev, "bad device id, expected 0x%08x, got 0x%08x", + AL_CODEC_UID_ID, id); + return -ENODEV; + } + + common_reset(dev); + al_common_write(dev, AL_CODEC_IRQ_MASK, AL_CODEC_IRQ_MCU_2_CPU); + + return 0; +} + +static void common_dma_buf_insert(struct al_common_dev *dev, + struct codec_dma_buf *buf) +{ + mutex_lock(&dev->buf_lock); + list_add(&buf->list, &dev->alloc_buffers); + mutex_unlock(&dev->buf_lock); +} + +static void common_dma_buf_remove(struct al_common_dev *dev, + struct codec_dma_buf *buf) +{ + mutex_lock(&dev->buf_lock); + list_del(&buf->list); + mutex_unlock(&dev->buf_lock); +} + +static struct codec_dma_buf *common_dma_buf_lookup(struct al_common_dev *d= ev, + dma_addr_t buf_paddr) +{ + struct codec_dma_buf *buf =3D NULL; + + mutex_lock(&dev->buf_lock); + list_for_each_entry(buf, &dev->alloc_buffers, list) + if (likely(buf->paddr =3D=3D buf_paddr)) + break; + + mutex_unlock(&dev->buf_lock); + + return list_entry_is_head(buf, &dev->alloc_buffers, list) ? NULL : buf; +} + +static void common_dma_buf_cleanup(struct al_common_dev *dev) +{ + struct codec_dma_buf *buf, *tmp; + + mutex_lock(&dev->buf_lock); + list_for_each_entry_safe(buf, tmp, &dev->alloc_buffers, list) { + dma_free_coherent(&dev->pdev->dev, buf->size, buf->vaddr, + buf->paddr); + list_del(&buf->list); + kfree(buf); + } + mutex_unlock(&dev->buf_lock); +} + +static void *common_dma_alloc(struct al_common_dev *dev, size_t size, + dma_addr_t *paddr, gfp_t flag) +{ + void *vaddr; + + vaddr =3D dma_alloc_coherent(&dev->pdev->dev, size, paddr, flag); + + if (!vaddr) + return NULL; + + /* PADDR <=3D (2^39 - 1) (39-bit MCU PADDR) */ + if ((*paddr + size) > AL_CODEC_MAX_ADDR) { + al_codec_err(dev, "mem check failed for 0x%16llx of size %zu", + *paddr, size); + dma_free_coherent(&dev->pdev->dev, size, vaddr, *paddr); + return NULL; + } + + return vaddr; +} + +void al_common_remove(struct al_common_dev *dev) +{ + common_dma_buf_cleanup(dev); + if (dev->fw_cpu_mem) + dma_free_coherent(&dev->pdev->dev, dev->fw_size, + dev->fw_cpu_mem, dev->fw_phys_addr); + + /* reset device */ + common_reset(dev); + clk_disable_unprepare(dev->mcu_clk); +} + +static void handle_alloc_memory_req(struct al_common_dev *dev, + struct msg_itf_header *hdr) +{ + struct msg_itf_alloc_mem_reply_full reply; + struct msg_itf_alloc_mem_req req; + struct codec_dma_buf *buf; + int ret; + + reply.reply.phyAddr =3D 0; + ret =3D al_common_get_data(dev, (char *)&req, hdr->payload_len); + if (ret) { + al_codec_err(dev, "Unable to get cma req"); + return; + } + + buf =3D kmalloc(sizeof(*buf), GFP_KERNEL); + if (!buf) + goto send_reply; + + buf->size =3D req.uSize; + buf->vaddr =3D common_dma_alloc(dev, req.uSize, &buf->paddr, GFP_KERNEL); + if (!buf->vaddr) + goto send_reply; + + reply.reply.phyAddr =3D (u64)buf->paddr; + common_dma_buf_insert(dev, buf); + +send_reply: + reply.hdr.type =3D MSG_ITF_TYPE_ALLOC_MEM_REPLY; + /* both fields embed info need to finish request */ + reply.hdr.drv_ctx_hdl =3D hdr->drv_ctx_hdl; + reply.hdr.drv_cmd_hdl =3D hdr->drv_cmd_hdl; + reply.hdr.payload_len =3D sizeof(reply.reply); + + ret =3D al_common_send(dev, &reply.hdr); + if (ret) { + al_codec_err(dev, "Unable to reply to cma alloc"); + common_dma_buf_remove(dev, buf); + } +} + +static void handle_free_memory_req(struct al_common_dev *dev, + struct msg_itf_header *hdr) +{ + struct msg_itf_free_mem_reply_full reply; + struct msg_itf_free_mem_req req; + struct codec_dma_buf *buf; + int ret; + + reply.reply.ret =3D -1; + ret =3D al_common_get_data(dev, (char *)&req, hdr->payload_len); + if (ret) { + al_codec_err(dev, "Unable to put cma req"); + return; + } + + buf =3D common_dma_buf_lookup(dev, req.phyAddr); + al_codec_dbg(3, "req.phyAddr =3D %p =3D> %p, Size %d", + (void *)(long)req.phyAddr, buf, buf->size); + if (!buf) { + al_codec_err(dev, "Unable to get dma handle for %p", + (void *)(long)req.phyAddr); + reply.reply.ret =3D -EINVAL; + goto send_reply; + } + + dma_free_coherent(&dev->pdev->dev, buf->size, buf->vaddr, buf->paddr); + common_dma_buf_remove(dev, buf); + reply.reply.ret =3D 0; + +send_reply: + reply.hdr.type =3D MSG_ITF_TYPE_FREE_MEM_REPLY; + /* both fields embed info need to hinish request */ + reply.hdr.drv_ctx_hdl =3D hdr->drv_ctx_hdl; + reply.hdr.drv_cmd_hdl =3D hdr->drv_cmd_hdl; + reply.hdr.payload_len =3D sizeof(reply.reply); + + ret =3D al_common_send(dev, &reply.hdr); + if (ret) + al_codec_err(dev, "Unable to reply to cma free"); +} + +static void handle_mcu_console_print(struct al_common_dev *dev, + struct msg_itf_header *hdr) +{ +#if defined(DEBUG) + struct msg_itf_write_req *req; + int ret; + + /* one more byte to be sure to have a zero terminated string */ + req =3D kzalloc(hdr->payload_len + 1, GFP_KERNEL); + if (!req) { + al_common_skip_data(dev, hdr->payload_len); + al_codec_err(dev, "Unable to alloc memory"); + return; + } + + ret =3D al_codec_msg_get_data(&dev->mb_m2h, (char *)req, + hdr->payload_len); + if (ret) { + al_codec_err(dev, "Unable to get request"); + kfree(req); + return; + } + + al_mcu_dbg("%s", (char *)(req + 1)); + kfree(req); +#else + al_common_skip_data(dev, hdr->payload_len); +#endif +} + +static void process_one_message(struct al_common_dev *dev, + struct msg_itf_header *hdr) +{ + if (hdr->type =3D=3D MSG_ITF_TYPE_ALLOC_MEM_REQ) + handle_alloc_memory_req(dev, hdr); + else if (hdr->type =3D=3D MSG_ITF_TYPE_FREE_MEM_REQ) + handle_free_memory_req(dev, hdr); + else if (hdr->type =3D=3D MSG_ITF_TYPE_WRITE_REQ) + handle_mcu_console_print(dev, hdr); + else if (hdr->type =3D=3D MSG_ITF_TYPE_MCU_ALIVE) + complete(&dev->completion); + else + dev->process_msg_cb(dev->cb_arg, hdr); +} + +static void common_reply_handle(struct al_common_dev *dev) +{ + struct msg_itf_header hdr; + int ret; + + while (1) { + ret =3D al_codec_msg_get_header(&dev->mb_m2h, &hdr); + if (ret) + break; + + process_one_message(dev, &hdr); + } +} + +static irqreturn_t common_irq_handler(int irq, void *data) +{ + struct al_common_dev *dev =3D data; + + /* poll all messages */ + common_reply_handle(dev); + + return IRQ_HANDLED; +} + +static irqreturn_t common_hardirq_handler(int irq, void *data) +{ + struct al_common_dev *dev =3D data; + u32 irq_status; + int ret; + + ret =3D al_common_read(dev, AL_CODEC_IRQ_STATUS_CLEAR, &irq_status); + if (ret || !irq_status) + return IRQ_NONE; + + al_common_write(dev, AL_CODEC_IRQ_STATUS_CLEAR, AL_CODEC_IRQ_MCU_2_CPU); + + return IRQ_WAKE_THREAD; +} + +static inline u64 get_machine_boot_addr(struct al_common_dev *dev, + struct boot_header *bh) +{ + return dev->fw_phys_addr + bh->vaddr_boot - bh->vaddr_start; +} + +static int common_start_fw(struct al_common_dev *dev, struct boot_header *= bh) +{ + u64 boot_addr; + u32 regbuf[2] =3D { 0 }; + int ret; + + boot_addr =3D get_machine_boot_addr(dev, bh); + regbuf[0] =3D upper_32_bits(boot_addr); + regbuf[1] =3D lower_32_bits(boot_addr); + + ret =3D al_common_write_multiple(dev, AL_CODEC_MCU_BOOT_ADDR, regbuf, + ARRAY_SIZE(regbuf)); + if (ret) { + al_codec_err(dev, "Unable to set the MCU boot address"); + return ret; + } + + al_codec_dbg(3, "boot_addr =3D %pad\n", &boot_addr); + + /* Enable the MCU clock */ + ret =3D common_update_bits(dev, AL_CODEC_MCU_CLK, AL_CODEC_COMM_MASK, + AL_CODEC_MCU_CLK_ENABLE); + + if (ret) { + al_codec_err(dev, " failed to enable the MCU clock"); + return ret; + } + + return !wait_for_completion_timeout(&dev->completion, HZ); +} + +static inline u64 common_get_periph_addr(struct al_common_dev *dev) +{ + struct resource *res; + + res =3D platform_get_resource_byname(dev->pdev, IORESOURCE_MEM, "apb"); + if (!res) { + al_codec_err(dev, "Unable to find APB start address"); + return 0; + } + + if (res->start & AL_CODEC_APB_MASK) { + al_codec_err(dev, "APB start address is invalid"); + return 0; + } + + return res->start; +} + +static int common_alloc_and_setup_fw_memory(struct al_common_dev *dev, + struct boot_header *bh) +{ + u64 periph_addr; + u32 regbuf[4] =3D { 0 }; + int ret; + + dev->fw_cpu_mem =3D common_dma_alloc(dev, dev->fw_size, + &dev->fw_phys_addr, GFP_KERNEL); + if (!dev->fw_cpu_mem) + return -ENOMEM; + + ret =3D al_common_write_multiple(dev, AL_CODEC_INSTRUCTION_DATA_OFFSET, + regbuf, ARRAY_SIZE(regbuf)); + if (ret) { + al_codec_err(dev, "failed to set the (i/d)Cache address"); + return ret; + } + + periph_addr =3D common_get_periph_addr(dev); + + regbuf[0] =3D upper_32_bits(periph_addr); + regbuf[1] =3D lower_32_bits(periph_addr); + ret =3D al_common_write_multiple(dev, AL_CODEC_MCU_PERIPHERAL_ADDR, + regbuf, 2); + if (ret) { + al_codec_err(dev, "failed to set the periph address"); + return ret; + } + + al_codec_dbg(3, "fw phys_addr =3D %pad", &dev->fw_phys_addr); + al_codec_dbg(3, "fw virt_addr =3D 0x%p", dev->fw_cpu_mem); + al_codec_dbg(3, "periph_addr =3D %pad", &periph_addr); + + return 0; +} + +static void common_fw_callback(const struct firmware *fw, void *context) +{ + struct al_common_dev *dev =3D context; + struct boot_header bh, *bhw; + u64 periph_addr =3D 0; + int ret; + + if (!fw) { + al_codec_err(dev, "The MCU firmware not found!"); + return; + } + + /* Copy the Firmware header */ + memcpy(&bh, fw->data, sizeof(bh)); + dev->fw_size =3D bh.vaddr_end - bh.vaddr_start; + + if (bh.bh_version < AL_BOOT_VERSION(2, 0, 0) || + bh.bh_version >=3D AL_BOOT_VERSION(3, 0, 0)) { + al_codec_err(dev, "bad boot header version"); + goto fw_release; + } + + if (WARN(bh.machine_id !=3D 2, "Wrong machine ID")) + goto fw_release; + + periph_addr =3D common_get_periph_addr(dev); + + if (!periph_addr) { + al_codec_err(dev, "Unable to get the periph addr"); + goto fw_release; + } + + al_codec_dbg(3, "bh version =3D 0x%08x", bh.bh_version); + al_codec_dbg(3, "fw version =3D 0x%08x", bh.fw_version); + al_codec_dbg(3, "fw model =3D %s", bh.model); + al_codec_dbg(3, "vaddress start =3D 0x%016llx", bh.vaddr_start); + al_codec_dbg(3, "vaddress end =3D 0x%016llx", bh.vaddr_end); + al_codec_dbg(3, "boot address =3D 0x%016llx", bh.vaddr_boot); + al_codec_dbg(3, "machineid =3D %lld", bh.machine_id); + al_codec_dbg(3, "periph address =3D 0x%016llx", periph_addr); + + ret =3D common_alloc_and_setup_fw_memory(dev, &bh); + if (ret) { + al_codec_err(dev, "out of memory %d", ret); + goto fw_release; + } + + al_codec_dbg(2, "Copy %zu bytes of fw", fw->size); + memcpy(dev->fw_cpu_mem, fw->data, fw->size); + + al_codec_mb_init(&dev->mb_h2m, + dev->fw_cpu_mem + bh.h2m.start - bh.vaddr_start, + bh.h2m.end - bh.h2m.start, MB_IFT_MAGIC_H2M); + al_codec_mb_init(&dev->mb_m2h, + dev->fw_cpu_mem + bh.m2h.start - bh.vaddr_start, + bh.m2h.end - bh.m2h.start, MB_IFT_MAGIC_M2H); + + /* give fw information about registers location */ + bhw =3D dev->fw_cpu_mem; + bhw->ip_start =3D periph_addr + AL_CODEC_IP_OFFSET; + bhw->ip_end =3D bhw->ip_start + resource_size(&dev->regs_info); + bhw->mcu_clk_rate =3D clk_get_rate(dev->mcu_clk); + + al_codec_dbg(3, "ip start =3D 0x%016llx", bhw->ip_start); + al_codec_dbg(3, "ip end =3D 0x%016llx", bhw->ip_end); + al_codec_dbg(3, "mcu clock rate is %llu", bhw->mcu_clk_rate); + + ret =3D common_start_fw(dev, &bh); + if (ret) { + al_codec_err(dev, "fw start has failed"); + goto fw_release; + } + + dev_info(&dev->pdev->dev, "mcu has boot successfully !\n"); + dev->fw_ready_cb(dev->cb_arg); + +fw_release: + release_firmware(fw); +} + +static int common_firmware_request_nowait(struct al_common_dev *dev) +{ + al_codec_dbg(2, "request fw %s", dev->fw_name); + + return request_firmware_nowait(THIS_MODULE, true, dev->fw_name, + &dev->pdev->dev, GFP_KERNEL, dev, + common_fw_callback); +} + +static int common_setup_dma(struct al_common_dev *dev) +{ + int ret; + + /* setup dma memory mask */ + ret =3D dma_set_mask_and_coherent(&dev->pdev->dev, DMA_BIT_MASK(64)); + if (ret) { + al_codec_err(dev, "failed to set dma"); + return -EINVAL; + } + + /* Try to use reserved memory if we got one */ + ret =3D of_reserved_mem_device_init(&dev->pdev->dev); + if (ret && ret !=3D ENODEV) + dev_warn(&dev->pdev->dev, + "No reserved memory, use cma instead\n"); + + return 0; +} + +int al_common_probe(struct platform_device *pdev, struct al_common_dev *de= v) +{ + struct resource *res; + void __iomem *regs; + int irq; + int ret; + + dev->pdev =3D pdev; + mutex_init(&dev->buf_lock); + INIT_LIST_HEAD(&dev->alloc_buffers); + init_completion(&dev->completion); + + /* The MCU has already default clock value */ + dev->mcu_clk =3D devm_clk_get(&pdev->dev, "mcu_clk"); + if (IS_ERR(dev->mcu_clk)) { + al_codec_err(dev, "failed to get MCU core clock"); + return PTR_ERR(dev->mcu_clk); + } + + ret =3D clk_prepare_enable(dev->mcu_clk); + if (ret) { + al_codec_err(dev, "Cannot enable MCU clock: %d\n", ret); + return ret; + } + + /* setup dma memory */ + ret =3D common_setup_dma(dev); + if (ret) + goto disable_clk; + + /* Hw registers */ + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); + if (!res) { + al_codec_err(dev, "regs resource missing from device tree"); + ret =3D -EINVAL; + goto disable_clk; + } + + dev->regs_info =3D *res; + + regs =3D devm_ioremap_resource(&pdev->dev, res); + if (!regs) { + al_codec_err(dev, "failed to map registers"); + ret =3D -ENOMEM; + goto disable_clk; + } + + dev->regmap =3D + devm_regmap_init_mmio(&pdev->dev, regs, &al_regmap_config); + + if (IS_ERR(dev->regmap)) { + al_codec_err(dev, "init regmap failed"); + ret =3D PTR_ERR(dev->regmap); + goto disable_clk; + } + + irq =3D platform_get_irq(pdev, 0); + if (irq < 0) { + al_codec_err(dev, "Failed to get IRQ"); + ret =3D -EINVAL; + goto disable_clk; + } + + ret =3D devm_request_threaded_irq(&pdev->dev, irq, common_hardirq_handler, + common_irq_handler, IRQF_SHARED, + dev_name(&pdev->dev), dev); + if (ret) { + al_codec_err(dev, "Unable to register irq handler"); + goto disable_clk; + } + + ret =3D common_probe_check_and_setup_hw(dev); + if (ret) { + al_codec_err(dev, "Unable to setup hw"); + goto disable_clk; + } + + /* ok so request the fw */ + ret =3D common_firmware_request_nowait(dev); + if (ret) { + al_codec_err(dev, "failed to request firmware"); + goto disable_clk; + } + + return 0; + +disable_clk: + clk_disable_unprepare(dev->mcu_clk); + + return ret; +} + +int al_common_send(struct al_common_dev *dev, struct msg_itf_header *hdr) +{ + return al_codec_msg_send(&dev->mb_h2m, hdr, common_trigger_mcu_irq, + dev); +} + +int al_common_send_req_reply(struct al_codec_dev *dev, + struct list_head *cmd_list, + struct msg_itf_header *hdr, + struct al_common_mcu_req *req) +{ + struct al_codec_cmd *cmd =3D NULL; + int ret; + + hdr->drv_cmd_hdl =3D 0; + + if (req->reply_size && req->reply) { + cmd =3D al_codec_cmd_create(req->reply_size); + if (!cmd) + return -ENOMEM; + + hdr->drv_cmd_hdl =3D al_virt_to_phys(cmd); + } + + hdr->drv_ctx_hdl =3D req->pCtx; + hdr->type =3D req->req_type; + hdr->payload_len =3D req->req_size; + + /* Add the list to the cmd list */ + if (cmd) + list_add(&cmd->list, cmd_list); + + ret =3D al_common_send(&dev->common, hdr); + if (ret) + goto remove_cmd; + + al_v4l2_dbg(3, "Send req to mcu %d : %ld ", req->req_type, + req->req_size); + + if (!cmd) + return 0; + + ret =3D wait_for_completion_timeout(&cmd->done, 5 * HZ); + if (ret <=3D 0) { + al_v4l2_err(dev, "cmd %p has %d (%s)", cmd, ret, + (ret =3D=3D 0) ? "failed" : "timedout"); + ret =3D -ETIMEDOUT; + goto remove_cmd; + } + + ret =3D 0; + memcpy(req->reply, cmd->reply, req->reply_size); + +remove_cmd: + + if (cmd) { + list_del(&cmd->list); + al_codec_cmd_put(cmd); + } + return ret; +} + +bool al_common_mcu_is_alive(struct al_codec_dev *dev) +{ + static const struct msg_itf_header hdr =3D { + .type =3D MSG_ITF_TYPE_MCU_ALIVE, + .payload_len =3D 0, + }; + struct al_common_dev *cdev =3D &dev->common; + int ret; + + ret =3D al_common_send(cdev, (struct msg_itf_header *)&hdr); + if (ret) + return false; + + ret =3D wait_for_completion_timeout(&cdev->completion, 5 * HZ); + if (ret <=3D 0) + return false; + + return true; +} diff --git a/drivers/media/platform/allegro-dvt/al300/al_codec_common.h b/d= rivers/media/platform/allegro-dvt/al300/al_codec_common.h new file mode 100644 index 000000000000..201a55c753f4 --- /dev/null +++ b/drivers/media/platform/allegro-dvt/al300/al_codec_common.h @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2025 Allegro DVT. + * Author: Yassine OUAISSA + */ + +#ifndef __AL_CODEC_COMMON__ +#define __AL_CODEC_COMMON__ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "al_codec_util.h" + +#define fh_to_ctx(ptr, type) container_of(ptr, type, fh) + +enum { + MSG_ITF_TYPE_CREATE_INST_REQ =3D MSG_ITF_TYPE_NEXT_REQ, + MSG_ITF_TYPE_DESTROY_INST_REQ, + MSG_ITF_TYPE_PUSH_BITSTREAM_BUFFER_REQ, + MSG_ITF_TYPE_PUT_DISPLAY_PICTURE_REQ, + MSG_ITF_TYPE_FLUSH_REQ, + MSG_ITF_TYPE_INFO_REQ, + MSG_ITF_TYPE_CREATE_INST_REPLY =3D MSG_ITF_TYPE_NEXT_REPLY, + MSG_ITF_TYPE_DESTROY_INST_REPLY, + MSG_ITF_TYPE_PUSH_BITSTREAM_BUFFER_REPLY, + MSG_ITF_TYPE_PUT_DISPLAY_PICTURE_REPLY, + MSG_ITF_TYPE_FLUSH_REPLY, + MSG_ITF_TYPE_INFO_REPLY, + MSG_ITF_TYPE_EVT_ERROR =3D MSG_ITF_TYPE_NEXT_EVT, +}; + +struct msg_itf_write_req { + u32 fd; + u32 len; + /* payload follow */ +} __packed; +DECLARE_FULL_REQ(msg_itf_write_req); + +struct msg_itf_free_mem_req { + phys_addr_t phyAddr; +} __packed; +DECLARE_FULL_REQ(msg_itf_free_mem_req); + +struct msg_itf_alloc_mem_req { + u64 uSize; +} __packed; +DECLARE_FULL_REQ(msg_itf_alloc_mem_req); + +struct msg_itf_alloc_mem_reply { + phys_addr_t phyAddr; +} __packed; +DECLARE_FULL_REPLY(msg_itf_alloc_mem_reply); + +struct msg_itf_free_mem_reply { + s64 ret; +}; +DECLARE_FULL_REPLY(msg_itf_free_mem_reply); + +struct msg_itf_create_codec_reply { + phys_addr_t hCodec; + s32 ret; +} __packed; +DECLARE_FULL_REPLY(msg_itf_create_codec_reply); + +struct msg_itf_destroy_codec_req { + phys_addr_t hCodec; +} __packed; +DECLARE_FULL_REQ(msg_itf_destroy_codec_req); + +/* + * Note : no need to know the status of this request + * The codec should be destroyed, in case of the mcu + * hasn't received any request with the codec handler + */ +struct msg_itf_destroy_codec_reply { + u32 unused; +} __packed; +DECLARE_FULL_REPLY(msg_itf_destroy_codec_reply); + +struct al_buffer_meta { + u64 timestamp; + struct v4l2_timecode timecode; + bool last; +}; + +struct msg_itf_push_src_buf_req { + phys_addr_t hCodec; + phys_addr_t bufferHandle; + phys_addr_t phyAddr; + u64 size; + struct al_buffer_meta meta; +} __packed; +DECLARE_FULL_REQ(msg_itf_push_src_buf_req); + +struct msg_itf_push_dst_buf_req { + phys_addr_t hCodec; + phys_addr_t bufferHandle; + phys_addr_t phyAddr; + u64 size; +} __packed; +DECLARE_FULL_REQ(msg_itf_push_dst_buf_req); + +struct msg_itf_push_buffer_req { + phys_addr_t hCodec; + phys_addr_t bufferHandle; + phys_addr_t phyAddr; + u64 size; +} __packed; +DECLARE_FULL_REQ(msg_itf_push_buffer_req); + +struct msg_itf_push_buffer_reply { + s32 res; +} __packed; +DECLARE_FULL_REPLY(msg_itf_push_buffer_reply); + +struct msg_itf_info_req { + u64 unused; +} __packed; +DECLARE_FULL_REQ(msg_itf_info_req); + +struct msg_itf_flush_req { + phys_addr_t hCodec; +} __packed; +DECLARE_FULL_REQ(msg_itf_flush_req); + +struct msg_itf_flush_reply { + int32_t unused; +} __packed; +DECLARE_FULL_REPLY(msg_itf_flush_reply); + +struct msg_itf_evt_error { + uint32_t errno; +} __packed; +DECLARE_FULL_EVENT(msg_itf_evt_error); + +struct al_match_data { + const char *fw_name; +}; + +struct al_common_mcu_req { + phys_addr_t pCtx; + int req_type; + size_t req_size; + size_t reply_size; + void *reply; +} __packed; + +struct al_common_dev { + struct platform_device *pdev; + void *fw_cpu_mem; + phys_addr_t fw_phys_addr; + const char *fw_name; + size_t fw_size; + struct clk *mcu_clk; + + struct al_codec_mb mb_h2m; + struct al_codec_mb mb_m2h; + struct completion completion; + + struct resource regs_info; + struct regmap *regmap; + + struct list_head alloc_buffers; + struct mutex buf_lock; + + /* callbacks set by client before common_probe */ + void *cb_arg; + void (*process_msg_cb)(void *cb_arg, struct msg_itf_header *hdr); + void (*fw_ready_cb)(void *cb_arg); +}; + +struct al_codec_dev { + struct v4l2_device v4l2_dev; + struct v4l2_m2m_dev *m2m_dev; + struct video_device video_dev; + struct al_common_dev common; + + /* mutex protecting vb2_queue structure */ + struct mutex lock; + + /* list of ctx (aka decoder) */ + struct mutex ctx_mlock; + struct list_head ctx_q_list; + int is_video_init_done; + + struct completion res_done; + /* list of cap/out supported formats */ + struct list_head codec_q_list; + struct al_codec_cmd *codec_info_cmd; +}; + +static inline int al_common_get_header(struct al_common_dev *dev, + struct msg_itf_header *hdr) +{ + return al_codec_msg_get_header(&dev->mb_m2h, hdr); +} + +static inline int al_common_get_data(struct al_common_dev *dev, char *data, + int len) +{ + return al_codec_msg_get_data(&dev->mb_m2h, data, len); +} + +static inline int al_common_skip_data(struct al_common_dev *dev, int len) +{ + return al_common_get_data(dev, NULL, len); +} + +int al_common_send(struct al_common_dev *dev, struct msg_itf_header *hdr); +int al_common_send_req_reply(struct al_codec_dev *dev, + struct list_head *cmd_list, + struct msg_itf_header *hdr, + struct al_common_mcu_req *req); +bool al_common_mcu_is_alive(struct al_codec_dev *dev); + +int al_common_probe(struct platform_device *pdev, struct al_common_dev *de= v); +void al_common_remove(struct al_common_dev *dev); + +#endif /*__AL_CODEC_COMMON__*/ diff --git a/drivers/media/platform/allegro-dvt/al300/al_codec_util.c b/dri= vers/media/platform/allegro-dvt/al300/al_codec_util.c new file mode 100644 index 000000000000..eb468e467747 --- /dev/null +++ b/drivers/media/platform/allegro-dvt/al300/al_codec_util.c @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Mailbox communication utilities for command creation + * and message exchange with the MCU + * + * Copyright (c) 2025 Allegro DVT. + * Author: Yassine OUAISSA + */ + +#include +#include +#include +#include +#include +#include + +#include "al_codec_util.h" + +static int al_get_used_space(struct al_codec_mb *mb) +{ + u32 head =3D mb->hdr->head; + u32 tail =3D mb->hdr->tail; + + return head >=3D tail ? head - tail : mb->size - (tail - head); +} + +static int al_get_free_space(struct al_codec_mb *mb) +{ + return mb->size - al_get_used_space(mb) - 1; +} + +static int al_has_enough_space(struct al_codec_mb *mb, int len) +{ + return al_get_free_space(mb) >=3D len; +} + +static inline void al_copy_to_mb(struct al_codec_mb *mb, char *data, int l= en) +{ + u32 head =3D mb->hdr->head; + int copy_len =3D min(mb->size - head, (unsigned int)len); + int copied_len =3D len; + + memcpy(&mb->data[head], data, copy_len); + len -=3D copy_len; + if (len) + memcpy(&mb->data[0], &data[copy_len], len); + + /* Make sure that all messages are written before updating the head */ + dma_wmb(); + mb->hdr->head =3D (head + copied_len) % mb->size; + /* Make sure that the head is updated in DDR instead of cache */ + dma_wmb(); +} + +static inline void al_copy_from_mb(struct al_codec_mb *mb, char *data, int= len) +{ + u32 tail =3D mb->hdr->tail; + int copy_len =3D min(mb->size - tail, (unsigned int)len); + int copied_len =3D len; + + if (!data) + goto update_tail; + + memcpy(data, &mb->data[tail], copy_len); + len -=3D copy_len; + if (len) + memcpy(&data[copy_len], &mb->data[0], len); + +update_tail: + mb->hdr->tail =3D (tail + copied_len) % mb->size; + /* Make sure that the head is updated in DDR instead of cache */ + dma_wmb(); +} + +static int al_codec_mb_send(struct al_codec_mb *mb, char *data, int len) +{ + if (!al_has_enough_space(mb, len)) + return -ENOMEM; + + al_copy_to_mb(mb, data, len); + + return 0; +} + +static int al_codec_mb_receive(struct al_codec_mb *mb, char *data, int len) +{ + if (al_get_used_space(mb) < len) + return -ENOMEM; + + al_copy_from_mb(mb, data, len); + + return 0; +} + +void al_codec_mb_init(struct al_codec_mb *mb, char *addr, int size, u32 ma= gic) +{ + mb->hdr =3D (struct al_mb_itf *)addr; + mb->hdr->magic =3D magic; + mb->hdr->version =3D MB_IFT_VERSION; + mb->hdr->head =3D 0; + mb->hdr->tail =3D 0; + mb->data =3D addr + sizeof(struct al_mb_itf); + mb->size =3D size - sizeof(struct al_mb_itf); + mutex_init(&mb->lock); +} + +int al_codec_msg_get_header(struct al_codec_mb *mb, struct msg_itf_header = *hdr) +{ + return al_codec_mb_receive(mb, (char *)hdr, sizeof(*hdr)); +} + +int al_codec_msg_get_data(struct al_codec_mb *mb, char *data, int len) +{ + return al_codec_mb_receive(mb, data, len); +} + +int al_codec_msg_send(struct al_codec_mb *mb, struct msg_itf_header *hdr, + void (*trigger)(void *), void *trigger_arg) +{ + unsigned long timeout; + int ret; + + timeout =3D jiffies + HZ; + mutex_lock(&mb->lock); + do { + if (time_after(jiffies, timeout)) { + mutex_unlock(&mb->lock); + return -ETIMEDOUT; + } + ret =3D al_codec_mb_send(mb, (char *)hdr, + hdr->payload_len + + sizeof(struct msg_itf_header)); + + } while (ret); + mutex_unlock(&mb->lock); + + trigger(trigger_arg); + + return 0; +} + +static void al_codec_cmd_cleanup(struct kref *ref) +{ + struct al_codec_cmd *cmd =3D + container_of(ref, struct al_codec_cmd, refcount); + if (cmd) { + kfree(cmd->reply); + kfree(cmd); + } +} + +void al_codec_cmd_put(struct al_codec_cmd *cmd) +{ + if (WARN_ON(!cmd)) + return; + + kref_put(&cmd->refcount, al_codec_cmd_cleanup); +} + +struct al_codec_cmd *al_codec_cmd_create(int reply_size) +{ + struct al_codec_cmd *cmd; + + cmd =3D kmalloc(sizeof(*cmd), GFP_KERNEL); + if (!cmd) + return NULL; + + cmd->reply =3D kmalloc(reply_size, GFP_KERNEL); + if (!cmd->reply) { + kfree(cmd); + return NULL; + } + + kref_init(&cmd->refcount); + cmd->reply_size =3D reply_size; + init_completion(&cmd->done); + + return cmd; +} diff --git a/drivers/media/platform/allegro-dvt/al300/al_codec_util.h b/dri= vers/media/platform/allegro-dvt/al300/al_codec_util.h new file mode 100644 index 000000000000..6806820bdb8a --- /dev/null +++ b/drivers/media/platform/allegro-dvt/al300/al_codec_util.h @@ -0,0 +1,186 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2025 Allegro DVT. + * Author: Yassine OUAISSA + */ + +#ifndef __AL_CODEC_UTIL__ +#define __AL_CODEC_UTIL__ + +#include +#include +#include + +#include +#include + +#define MB_IFT_MAGIC_H2M 0xabcd1230 +#define MB_IFT_MAGIC_M2H 0xabcd1231 +#define MB_IFT_VERSION 0x00010000 + +#define MAJOR_SHIFT 20 +#define MAJOR_MASK 0xfff +#define MINOR_SHIFT 8 +#define MINOR_MASK 0xfff +#define PATCH_SHIFT 0 +#define PATCH_MASK 0xff + +/* + * AL_BOOT_VERSION() - Version format 32-bit, 12 bits for the major, + * the same for minor, 8bits for the patch + */ +#define AL_BOOT_VERSION(major, minor, patch) \ + ((((major) & MAJOR_MASK) << MAJOR_SHIFT) | \ + (((minor) & MINOR_MASK) << MINOR_SHIFT) | \ + (((patch) & PATCH_MASK) << PATCH_SHIFT)) + +#define al_phys_to_virt(x) ((void *)(uintptr_t)x) +#define al_virt_to_phys(x) ((phys_addr_t)(uintptr_t)x) + +#define DECLARE_FULL_REQ(s) \ + struct s##_full { \ + struct msg_itf_header hdr; \ + struct s req; \ + } __packed + +#define DECLARE_FULL_REPLY(s) \ + struct s##_full { \ + struct msg_itf_header hdr; \ + struct s reply; \ + } __packed + +#define DECLARE_FULL_EVENT(s) \ + struct s##_full { \ + struct msg_itf_header hdr; \ + struct s event; \ + } __packed + +struct al_mb_itf { + u32 magic; + u32 version; + u32 head; + u32 tail; +} __packed; + +struct al_codec_mb { + struct al_mb_itf *hdr; + struct mutex lock; + char *data; + int size; +}; + +struct al_codec_cmd { + struct kref refcount; + struct list_head list; + struct completion done; + int reply_size; + void *reply; +}; + +#if defined(DEBUG) + +extern int debug; +/* Common logs */ +#define al_codec_err(dev, fmt, args...) = \ + pr_err("[ALG_CODEC][ERROR] %s():%d: " fmt "\n", __func__, __LINE__, \ + ##args) + +#define al_codec_dbg(level, fmt, args...) = \ + do { \ + if (debug >=3D level) \ + pr_info("[ALG_CODEC] level=3D%d %s(),%d: " fmt "\n", \ + level, __func__, __LINE__, ##args); \ + } while (0) + +/* V4L2 logs */ +#define al_v4l2_err(dev, fmt, args...) = \ + pr_err("[ALG_V4L2][ERROR] %s():%d: " fmt "\n", __func__, __LINE__, \ + ##args) + +#define al_v4l2_dbg(level, fmt, args...) \ + do { \ + if (debug >=3D level) \ + pr_info("[ALG_V4L2] level=3D%d %s(),%d: " fmt "\n", \ + level, __func__, __LINE__, ##args); \ + } while (0) + +/* MCU debug */ +#define al_mcu_dbg(fmt, args...) pr_info("[ALG_MCU]: " fmt, ##args); + +#else + +#define al_codec_err(_dev, fmt, args...) \ + dev_err(&_dev->pdev->dev, fmt "\n", ##args) + +#define al_v4l2_err(_dev, fmt, args...) \ + dev_err(&_dev->common.pdev->dev, fmt "\n", ##args) + +#define al_codec_dbg(level, fmt, args...) +#define al_v4l2_dbg(level, fmt, args...) +#define al_mcu_dbg(fmt, args...) + +#endif + +#define MSG_ITF_TYPE_LIMIT BIT(10) + +/* Message types host <-> mcu */ +enum { + MSG_ITF_TYPE_MCU_ALIVE =3D 0x0, + MSG_ITF_TYPE_WRITE_REQ =3D 0x02, + MSG_ITF_TYPE_FIRST_REQ =3D 1024, + MSG_ITF_TYPE_NEXT_REQ, + MSG_ITF_TYPE_FIRST_REPLY =3D 2048, + MSG_ITF_TYPE_NEXT_REPLY, + MSG_ITF_TYPE_ALLOC_MEM_REQ =3D 3072, + MSG_ITF_TYPE_FREE_MEM_REQ, + MSG_ITF_TYPE_ALLOC_MEM_REPLY =3D 4096, + MSG_ITF_TYPE_FREE_MEM_REPLY, + MSG_ITF_TYPE_FIRST_EVT =3D 5120, + MSG_ITF_TYPE_NEXT_EVT =3D MSG_ITF_TYPE_FIRST_EVT +}; + +struct msg_itf_header { + u64 drv_ctx_hdl; + u64 drv_cmd_hdl; + u16 type; + u16 payload_len; + u16 padding[2]; +} __packed; + +void al_codec_mb_init(struct al_codec_mb *mb, char *addr, int size, u32 ma= gic); +int al_codec_msg_get_header(struct al_codec_mb *mb, struct msg_itf_header = *hdr); +int al_codec_msg_get_data(struct al_codec_mb *mb, char *data, int len); +int al_codec_msg_send(struct al_codec_mb *mb, struct msg_itf_header *hdr, + void (*trigger)(void *), void *trigger_arg); + +static inline bool is_type_reply(uint16_t type) +{ + return type >=3D MSG_ITF_TYPE_FIRST_REPLY && + type < MSG_ITF_TYPE_FIRST_REPLY + MSG_ITF_TYPE_LIMIT; +} + +static inline bool is_type_event(uint16_t type) +{ + return type >=3D MSG_ITF_TYPE_FIRST_EVT && + type < MSG_ITF_TYPE_FIRST_EVT + MSG_ITF_TYPE_LIMIT; +} + +void al_codec_cmd_put(struct al_codec_cmd *cmd); + +struct al_codec_cmd *al_codec_cmd_create(int reply_size); + +static inline struct al_codec_cmd *al_codec_cmd_get(struct list_head *cmd_= list, + uint64_t hdl) +{ + struct al_codec_cmd *cmd =3D NULL; + + list_for_each_entry(cmd, cmd_list, list) { + if (likely(cmd =3D=3D al_phys_to_virt(hdl))) { + kref_get(&cmd->refcount); + break; + } + } + return list_entry_is_head(cmd, cmd_list, list) ? NULL : cmd; +} + +#endif /* __AL_CODEC_UTIL__ */ diff --git a/drivers/media/platform/allegro-dvt/al300/al_vdec_drv.c b/drive= rs/media/platform/allegro-dvt/al300/al_vdec_drv.c new file mode 100644 index 000000000000..f7767098e844 --- /dev/null +++ b/drivers/media/platform/allegro-dvt/al300/al_vdec_drv.c @@ -0,0 +1,1533 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Allegro DVT. + * Author: Yassine OUAISSA + * + * Allegro DVT stateful video decoder driver for the IP Gen 3 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "al_codec_common.h" +#include "al_vdec_drv.h" + +#if defined(DEBUG) +/* Log level */ +int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "Debug level (0-3)"); +#endif + +/* default decoder params */ +#define DECODER_WIDTH_DEFAULT 640 +#define DECODER_HEIGHT_DEFAULT 480 +#define DECODER_WIDTH_MAX 3840 +#define DECODER_HEIGHT_MAX 2160 +#define DECODER_WIDTH_MIN 16 +#define DECODER_HEIGHT_MIN 16 +#define DEC_REQ_TIMEOUT msecs_to_jiffies(1000) +#define DEC_RES_EVT_TIMEOUT DEC_REQ_TIMEOUT + +/* Supported formats */ +static const struct al_fmt al_src_formats[] =3D { + { + .pixelformat =3D V4L2_PIX_FMT_H264, + .bpp =3D 20, + }, + { + .pixelformat =3D V4L2_PIX_FMT_HEVC, + .bpp =3D 20, + }, + { + .pixelformat =3D V4L2_PIX_FMT_JPEG, + .bpp =3D 8, + } +}; + +static const struct al_fmt al_dst_formats[] =3D { + { + .pixelformat =3D V4L2_PIX_FMT_NV12, + .bpp =3D 12, + }, + { + .pixelformat =3D V4L2_PIX_FMT_P010, + .bpp =3D 12, + }, + { + .pixelformat =3D V4L2_PIX_FMT_NV16, + .bpp =3D 16, + }, + { + .pixelformat =3D V4L2_PIX_FMT_YUV420, /* YUV 4:2:0 */ + .bpp =3D 12, + }, + { + .pixelformat =3D V4L2_PIX_FMT_YVU420, /* YVU 4:2:0 */ + .bpp =3D 12, + }, +}; + +/* Default format */ +static const struct al_frame al_default_fmt =3D { + + .width =3D DECODER_WIDTH_DEFAULT, + .height =3D DECODER_HEIGHT_DEFAULT, + .bytesperline =3D DECODER_WIDTH_MAX * 4, + .sizeimage =3D DECODER_WIDTH_DEFAULT * DECODER_HEIGHT_DEFAULT * 4, + .nbuffers =3D 1, + .fmt =3D &al_dst_formats[0], + .field =3D V4L2_FIELD_NONE, + .colorspace =3D V4L2_COLORSPACE_REC709, + .ycbcr_enc =3D V4L2_YCBCR_ENC_DEFAULT, + .quantization =3D V4L2_QUANTIZATION_DEFAULT, + .xfer_func =3D V4L2_XFER_FUNC_DEFAULT +}; + +static struct al_frame *al_get_frame(struct al_dec_ctx *ctx, + enum v4l2_buf_type type) +{ + if (WARN_ON(!ctx)) + return ERR_PTR(-EINVAL); + + if (type =3D=3D V4L2_BUF_TYPE_VIDEO_OUTPUT) + return &ctx->src; + else if (type =3D=3D V4L2_BUF_TYPE_VIDEO_CAPTURE) + return &ctx->dst; + + al_v4l2_err(ctx->dev, "Unsupported type (%d)", type); + + return ERR_PTR(-EINVAL); +} + +static const struct al_fmt *al_find_fmt(u32 pixelformat) +{ + const struct al_fmt *fmt; + unsigned int i; + + /* check if the pixelformat exist in the src formats list */ + for (i =3D 0; i < ARRAY_SIZE(al_src_formats); i++) { + fmt =3D &al_src_formats[i]; + if (fmt->pixelformat =3D=3D pixelformat) + return fmt; + } + + /* check if the pixelformat exist in the dst formats list */ + for (i =3D 0; i < ARRAY_SIZE(al_dst_formats); i++) { + fmt =3D &al_dst_formats[i]; + if (fmt->pixelformat =3D=3D pixelformat) + return fmt; + } + + return NULL; +} + +static int dec_fw_create_decoder(struct al_dec_ctx *ctx) +{ + struct msg_itf_create_decoder_req_full req; + struct msg_itf_create_codec_reply reply; + struct al_common_mcu_req mreq; + int ret; + + if (ctx->hDec) { + al_v4l2_dbg(3, "fw decoder already exist\n"); + return 0; + } + + req.req.codec =3D ctx->codec; + + mreq.pCtx =3D al_virt_to_phys(ctx); + mreq.req_type =3D MSG_ITF_TYPE_CREATE_INST_REQ; + mreq.req_size =3D sizeof(req.req); + mreq.reply_size =3D sizeof(reply); + mreq.reply =3D &reply; + + ret =3D al_common_send_req_reply(ctx->dev, &ctx->cmd_q_list, &req.hdr, + &mreq); + + if (!ret && !reply.ret) + ctx->hDec =3D reply.hCodec; + else if (reply.ret) + ret =3D -ENODEV; + + return ret; +} + +static void dec_fw_destroy_decoder(struct al_dec_ctx *ctx) +{ + struct msg_itf_destroy_codec_req_full req; + struct msg_itf_destroy_codec_reply reply; + struct al_common_mcu_req mreq; + int ret; + + if (!ctx->hDec) { + al_v4l2_dbg(3, "fw decoder doesn't exist"); + return; + } + al_v4l2_dbg(3, "Destroy decoder %lld ", ctx->hDec); + + req.req.hCodec =3D ctx->hDec; + + mreq.pCtx =3D al_virt_to_phys(ctx); + mreq.req_type =3D MSG_ITF_TYPE_DESTROY_INST_REQ; + mreq.req_size =3D sizeof(req.req); + mreq.reply_size =3D sizeof(reply); + mreq.reply =3D &reply; + + ret =3D al_common_send_req_reply(ctx->dev, &ctx->cmd_q_list, &req.hdr, + &mreq); + + if (!ret) + ctx->hDec =3D 0; +} + +static int al_dec_fw_push_frame_buf(struct al_dec_ctx *ctx, + struct vb2_v4l2_buffer *vbuf) +{ + struct msg_itf_push_dst_buf_req_full req; + struct v4l2_m2m_buffer *m2m_buf; + struct al_common_mcu_req mreq =3D { 0 }; + int ret; + + if (WARN(!vbuf, "NULL frame Buffer to push!!")) + return -EINVAL; + + req.req.hCodec =3D ctx->hDec; + m2m_buf =3D container_of(vbuf, struct v4l2_m2m_buffer, vb); + req.req.bufferHandle =3D al_virt_to_phys(m2m_buf); + req.req.phyAddr =3D vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0); + req.req.size =3D vb2_plane_size(&vbuf->vb2_buf, 0); + + mreq.pCtx =3D al_virt_to_phys(ctx); + mreq.req_type =3D MSG_ITF_TYPE_PUT_DISPLAY_PICTURE_REQ; + mreq.req_size =3D sizeof(req.req); + + ret =3D al_common_send_req_reply(ctx->dev, &ctx->cmd_q_list, &req.hdr, + &mreq); + if (ret) + al_v4l2_err(ctx->dev, "Failed to push frame buffer %p %d", + m2m_buf, ret); + + return ret; +} + +static int al_dec_fw_push_bitstream_buf(struct al_dec_ctx *ctx, + struct vb2_v4l2_buffer *vbuf) +{ + struct msg_itf_push_src_buf_req_full req; + struct v4l2_m2m_buffer *m2m_buf; + struct al_common_mcu_req mreq =3D { 0 }; + int ret; + + if (WARN(!vbuf, "NULL Buffer to push!!")) + return -EINVAL; + + req.req.hCodec =3D ctx->hDec; + m2m_buf =3D container_of(vbuf, struct v4l2_m2m_buffer, vb); + req.req.bufferHandle =3D al_virt_to_phys(m2m_buf); + req.req.phyAddr =3D vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0); + req.req.size =3D vb2_plane_size(&vbuf->vb2_buf, 0); + + /* Fill the v4l2 metadata*/ + req.req.meta.timestamp =3D vbuf->vb2_buf.timestamp; + req.req.meta.timecode =3D vbuf->timecode; + req.req.meta.last =3D vbuf->flags & V4L2_BUF_FLAG_LAST; + + mreq.pCtx =3D al_virt_to_phys(ctx); + mreq.req_type =3D MSG_ITF_TYPE_PUSH_BITSTREAM_BUFFER_REQ; + mreq.req_size =3D sizeof(req.req); + + ret =3D al_common_send_req_reply(ctx->dev, &ctx->cmd_q_list, &req.hdr, + &mreq); + if (ret) + al_v4l2_err(ctx->dev, "Failed to push bitstream buffer %p %d", + m2m_buf, ret); + + return ret; +} + +static int dec_fw_flush_req(struct al_dec_ctx *ctx) +{ + struct msg_itf_flush_req_full req; + struct msg_itf_flush_reply reply; + struct al_common_mcu_req mreq; + int ret; + + req.req.hCodec =3D ctx->hDec; + + mreq.pCtx =3D al_virt_to_phys(ctx); + mreq.req_type =3D MSG_ITF_TYPE_FLUSH_REQ; + mreq.req_size =3D sizeof(req.req); + mreq.reply_size =3D sizeof(reply); + mreq.reply =3D &reply; + + ret =3D al_common_send_req_reply(ctx->dev, &ctx->cmd_q_list, &req.hdr, + &mreq); + + if (ret) + al_v4l2_err(ctx->dev, "Failed to flush the decoder %d", ret); + + return ret; +} + +static inline struct vb2_v4l2_buffer * +al_dec_dequeue_buf(struct al_dec_ctx *ctx, uint64_t hdl, + struct list_head *buffer_list) +{ + struct v4l2_m2m_buffer *buf, *tmp; + struct vb2_v4l2_buffer *ret =3D NULL; + + mutex_lock(&ctx->buf_q_mlock); + list_for_each_entry_safe(buf, tmp, buffer_list, list) { + if (buf =3D=3D al_phys_to_virt(hdl)) { + list_del(&buf->list); + ret =3D &buf->vb; + break; + } + } + mutex_unlock(&ctx->buf_q_mlock); + + return ret; +} + +static struct vb2_v4l2_buffer *al_dec_dequeue_src_buf(struct al_dec_ctx *c= tx, + uint64_t hdl) +{ + return al_dec_dequeue_buf(ctx, hdl, &ctx->stream_q_list); +} + +static struct vb2_v4l2_buffer *al_dec_dequeue_dst_buf(struct al_dec_ctx *c= tx, + uint64_t hdl) +{ + return al_dec_dequeue_buf(ctx, hdl, &ctx->frame_q_list); +} + +static void al_ctx_cleanup(struct kref *ref) +{ + struct al_dec_ctx *ctx =3D container_of(ref, struct al_dec_ctx, refcount); + + kfree(ctx); +} + +static inline struct al_dec_ctx *al_ctx_get(struct al_codec_dev *dev, + uint64_t hdl) +{ + struct al_dec_ctx *ctx; + struct al_dec_ctx *ret =3D NULL; + + mutex_lock(&dev->ctx_mlock); + list_for_each_entry(ctx, &dev->ctx_q_list, list) { + if (ctx =3D=3D al_phys_to_virt(hdl)) { + kref_get(&ctx->refcount); + ret =3D ctx; + break; + } + } + mutex_unlock(&dev->ctx_mlock); + + return ret; +} + +static void al_ctx_put(struct al_dec_ctx *ctx) +{ + kref_put(&ctx->refcount, al_ctx_cleanup); +} + +static int al_dec_start_streaming(struct vb2_queue *q, unsigned int count) +{ + struct al_dec_ctx *ctx =3D vb2_get_drv_priv(q); + struct al_codec_dev *dev =3D ctx->dev; + + v4l2_m2m_update_start_streaming_state(ctx->fh.m2m_ctx, q); + + if (V4L2_TYPE_IS_OUTPUT(q->type)) { + struct v4l2_m2m_buffer *buf; + int ret; + + if (list_empty(&ctx->stream_q_list)) { + al_v4l2_dbg(0, "Empty stream list."); + return -EINVAL; + } + if (!al_common_mcu_is_alive(dev)) { + al_v4l2_err(dev, "Unable to ping the mcu"); + return -ENODEV; + } + + ret =3D dec_fw_create_decoder(ctx); + if (ret) { + al_v4l2_err(dev, "Unable to create the fw decoder %d", + ret); + return ret; + } + + /* Get the first vid-out queued buffer */ + buf =3D list_first_entry(&ctx->stream_q_list, + struct v4l2_m2m_buffer, list); + + if (!buf) { + al_v4l2_err( + dev, + "Unable to get the first buffer from the stream list"); + return -EINVAL; + } + + if (al_dec_fw_push_bitstream_buf(ctx, &buf->vb)) { + al_v4l2_err(ctx->dev, + "Unable to push the bitstream buffer"); + return -EINVAL; + } + + /* Wait until the mcu detect the resolution of the stream */ + ret =3D wait_for_completion_timeout(&ctx->res_done, + DEC_RES_EVT_TIMEOUT); + if (!ret) { + al_v4l2_err(ctx->dev, "unsupported stream"); + ctx->aborting =3D true; + } + + ctx->osequence =3D 0; + } else + ctx->csequence =3D 0; + + return 0; +} + +static void al_dec_stop_streaming_cap(struct al_dec_ctx *ctx) +{ + struct vb2_v4l2_buffer *vbuf; + struct v4l2_m2m_buffer *entry, *tmp; + + mutex_lock(&ctx->buf_q_mlock); + if (!list_empty(&ctx->frame_q_list)) + list_for_each_entry_safe(entry, tmp, &ctx->frame_q_list, list) { + list_del(&entry->list); + vbuf =3D &entry->vb; + vb2_set_plane_payload(&vbuf->vb2_buf, 0, 0); + v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR); + } + mutex_unlock(&ctx->buf_q_mlock); + + while (v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx)) { + vbuf =3D v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); + if (vbuf) { + vb2_set_plane_payload(&vbuf->vb2_buf, 0, 0); + v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR); + } + } + + v4l2_m2m_mark_stopped(ctx->fh.m2m_ctx); +} + +static void al_dec_stop_streaming_out(struct al_dec_ctx *ctx) +{ + struct vb2_v4l2_buffer *vbuf; + struct v4l2_m2m_buffer *entry, *tmp; + + mutex_lock(&ctx->buf_q_mlock); + if (!list_empty(&ctx->stream_q_list)) + list_for_each_entry_safe(entry, tmp, &ctx->stream_q_list, + list) { + list_del(&entry->list); + v4l2_m2m_buf_done(&entry->vb, VB2_BUF_STATE_ERROR); + } + mutex_unlock(&ctx->buf_q_mlock); + + if (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx)) { + while ((vbuf =3D v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx))) + if (vbuf->vb2_buf.state =3D=3D VB2_BUF_STATE_ACTIVE) + v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR); + } + + dec_fw_destroy_decoder(ctx); +} + +static void al_dec_stop_streaming(struct vb2_queue *q) +{ + struct al_dec_ctx *ctx =3D vb2_get_drv_priv(q); + + v4l2_m2m_update_stop_streaming_state(ctx->fh.m2m_ctx, q); + + /* Releasing the dst and src buffers */ + ctx->stopped =3D true; + + if (V4L2_TYPE_IS_OUTPUT(q->type)) + al_dec_stop_streaming_out(ctx); + else + al_dec_stop_streaming_cap(ctx); +} + +static int al_dec_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers, + unsigned int *nplanes, unsigned int sizes[], + struct device *alloc_devs[]) +{ + struct al_dec_ctx *ctx =3D vb2_get_drv_priv(vq); + struct al_frame *format =3D al_get_frame(ctx, vq->type); + + if (IS_ERR(format)) { + al_v4l2_err(ctx->dev, "Invalid format %p", format); + return PTR_ERR(format); + } + + if (*nplanes) + return ((sizes[0] < format->sizeimage) ? -EINVAL : 0); + + /* update queue num buffers */ + format->nbuffers =3D max(*nbuffers, format->nbuffers); + + *nplanes =3D 1; + sizes[0] =3D format->sizeimage; + *nbuffers =3D format->nbuffers; + + al_v4l2_dbg(2, "%s: Get %d buffers of size %d each ", + (vq->type =3D=3D V4L2_BUF_TYPE_VIDEO_OUTPUT) ? "OUT" : "CAP", + *nbuffers, sizes[0]); + + return 0; +} + +static int al_dec_buf_prepare(struct vb2_buffer *vb) +{ + struct al_dec_ctx *ctx =3D vb2_get_drv_priv(vb->vb2_queue); + struct vb2_v4l2_buffer *vbuf =3D to_vb2_v4l2_buffer(vb); + + if (ctx->aborting) + return -EINVAL; + + if (V4L2_TYPE_IS_CAPTURE(vb->type)) { + if (vbuf->field =3D=3D V4L2_FIELD_ANY) + vbuf->field =3D V4L2_FIELD_NONE; + if (vbuf->field !=3D V4L2_FIELD_NONE) + return -EINVAL; + } + + al_v4l2_dbg(3, "%s : Buffer (%p) prepared ", + (V4L2_TYPE_IS_OUTPUT(vb->type) ? "OUT" : "CAP"), vbuf); + + return 0; +} + +static inline void al_dec_fill_bitstream(struct al_dec_ctx *ctx) +{ + struct vb2_v4l2_buffer *src_buf; + struct v4l2_m2m_buffer *m2m_buf; + struct vb2_queue *src_vq; + + lockdep_assert_held(&ctx->buf_q_mlock); + + if (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) > 0) { + src_buf =3D v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); + if (!src_buf) + return; + + /* Dump empty buffers */ + if (!vb2_get_plane_payload(&src_buf->vb2_buf, 0)) { + src_buf =3D v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); + v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE); + return; + } + + src_vq =3D v4l2_m2m_get_src_vq(ctx->fh.m2m_ctx); + src_buf =3D v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); + + if (src_buf) { + src_buf->sequence =3D ctx->osequence++; + + if (vb2_is_streaming(src_vq) && + al_dec_fw_push_bitstream_buf(ctx, src_buf)) { + v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR); + return; + } + + m2m_buf =3D container_of(src_buf, struct v4l2_m2m_buffer, + vb); + list_add_tail(&m2m_buf->list, &ctx->stream_q_list); + } + } +} + +static void al_dec_buf_queue(struct vb2_buffer *vb) +{ + struct al_dec_ctx *ctx =3D vb2_get_drv_priv(vb->vb2_queue); + struct vb2_v4l2_buffer *vbuf =3D to_vb2_v4l2_buffer(vb); + + v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf); + + if (V4L2_TYPE_IS_OUTPUT(vb->type)) { + mutex_lock(&ctx->buf_q_mlock); + al_dec_fill_bitstream(ctx); + mutex_unlock(&ctx->buf_q_mlock); + } + + al_v4l2_dbg(3, "%s queued (%p) - (%d)", + V4L2_TYPE_IS_OUTPUT(vb->type) ? "OUT" : "CAP", vbuf, + vb->num_planes); +} + +static const struct vb2_ops dec_queue_ops =3D { + .queue_setup =3D al_dec_queue_setup, + .buf_prepare =3D al_dec_buf_prepare, + .buf_queue =3D al_dec_buf_queue, + .start_streaming =3D al_dec_start_streaming, + .stop_streaming =3D al_dec_stop_streaming, + .wait_prepare =3D vb2_ops_wait_prepare, + .wait_finish =3D vb2_ops_wait_finish, +}; + +static int al_dec_queue_init(void *priv, struct vb2_queue *src_vq, + struct vb2_queue *dst_vq) +{ + struct al_dec_ctx *ctx =3D priv; + int ret; + + src_vq->dev =3D &ctx->dev->common.pdev->dev; + src_vq->type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT; + src_vq->io_modes =3D VB2_MMAP | VB2_DMABUF; + src_vq->non_coherent_mem =3D false; + src_vq->dma_attrs |=3D DMA_ATTR_FORCE_CONTIGUOUS; + src_vq->mem_ops =3D &vb2_dma_contig_memops; + src_vq->drv_priv =3D ctx; + src_vq->timestamp_flags =3D V4L2_BUF_FLAG_TIMESTAMP_COPY; + src_vq->ops =3D &dec_queue_ops; + src_vq->buf_struct_size =3D sizeof(struct v4l2_m2m_buffer); + src_vq->lock =3D &ctx->dev->lock; + ret =3D vb2_queue_init(src_vq); + if (ret) + return ret; + + dst_vq->dev =3D &ctx->dev->common.pdev->dev; + dst_vq->type =3D V4L2_BUF_TYPE_VIDEO_CAPTURE; + dst_vq->io_modes =3D VB2_MMAP | VB2_DMABUF; + dst_vq->non_coherent_mem =3D false; + dst_vq->dma_attrs |=3D DMA_ATTR_FORCE_CONTIGUOUS; + dst_vq->mem_ops =3D &vb2_dma_contig_memops; + dst_vq->drv_priv =3D ctx; + dst_vq->timestamp_flags =3D V4L2_BUF_FLAG_TIMESTAMP_COPY; + dst_vq->ops =3D &dec_queue_ops; + dst_vq->buf_struct_size =3D sizeof(struct v4l2_m2m_buffer); + dst_vq->lock =3D &ctx->dev->lock; + ret =3D vb2_queue_init(dst_vq); + if (ret) { + vb2_queue_release(src_vq); + return ret; + } + + return 0; +} + +static int al_dec_querycap(struct file *file, void *fh, + struct v4l2_capability *cap) +{ + struct al_codec_dev *dev =3D video_drvdata(file); + + strscpy(cap->driver, KBUILD_MODNAME, sizeof(cap->driver)); + strscpy(cap->card, "Allegro DVT Video Decoder", sizeof(cap->card)); + snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", + dev_name(&dev->common.pdev->dev)); + + return 0; +} + +static int al_dec_enum_fmt(struct file *file, void *fh, struct v4l2_fmtdes= c *f) +{ + const struct al_fmt *fmt; + + if (f->type !=3D V4L2_BUF_TYPE_VIDEO_OUTPUT && + f->type !=3D V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + if (V4L2_TYPE_IS_OUTPUT(f->type)) { + if (f->index >=3D ARRAY_SIZE(al_src_formats)) + return -EINVAL; + + fmt =3D &al_src_formats[f->index]; + } else { + if (f->index >=3D ARRAY_SIZE(al_dst_formats)) + return -EINVAL; + + fmt =3D &al_dst_formats[f->index]; + } + + f->pixelformat =3D fmt->pixelformat; + return 0; +} + +static int al_dec_try_fmt(struct file *file, void *fh, struct v4l2_format = *f) +{ + struct al_dec_ctx *ctx =3D fh_to_ctx(fh, struct al_dec_ctx); + struct v4l2_pix_format *pix =3D &f->fmt.pix; + struct al_frame *pix_fmt; + + pix_fmt =3D al_get_frame(ctx, f->type); + if (IS_ERR(pix_fmt)) { + al_v4l2_err(ctx->dev, "Invalid frame (%p)", pix_fmt); + return PTR_ERR(pix_fmt); + } + + pix_fmt->fmt =3D al_find_fmt(pix->pixelformat); + if (!pix_fmt->fmt) { + al_v4l2_err(ctx->dev, "Unknown format 0x%x", pix->pixelformat); + return -EINVAL; + } + pix->field =3D V4L2_FIELD_NONE; + pix->width =3D clamp_t(__u32, pix->width, DECODER_WIDTH_MIN, + DECODER_WIDTH_MAX); + pix->height =3D clamp_t(__u32, pix->height, DECODER_HEIGHT_MIN, + DECODER_HEIGHT_MAX); + + pix->bytesperline =3D pix->width; + pix->sizeimage =3D (pix->width * pix->height * pix_fmt->fmt->bpp) / 8; + + if (V4L2_TYPE_IS_CAPTURE(f->type)) + if (pix->sizeimage < pix_fmt->sizeimage) + pix->sizeimage =3D pix_fmt->sizeimage; + + al_v4l2_dbg( + 3, + "%s : width (%d) , height (%d), bytesperline (%d), sizeimage (%d) ", + (f->type =3D=3D V4L2_BUF_TYPE_VIDEO_CAPTURE) ? "CAP" : "OUT", + pix->width, pix->height, pix->bytesperline, pix->sizeimage); + + return 0; +} + +static int al_dec_g_fmt(struct file *file, void *fh, struct v4l2_format *f) +{ + struct al_dec_ctx *ctx =3D fh_to_ctx(fh, struct al_dec_ctx); + struct al_frame *pix_fmt =3D al_get_frame(ctx, f->type); + struct v4l2_pix_format *pix; + + if (IS_ERR(pix_fmt)) { + al_v4l2_err(ctx->dev, "Invalid pixel format %p", pix_fmt); + return PTR_ERR(pix_fmt); + } + + if (!pix_fmt->fmt) { + al_v4l2_err(ctx->dev, "Unknown format for %d", f->type); + return -EINVAL; + } + + pix =3D &f->fmt.pix; + pix->width =3D pix_fmt->width; + pix->height =3D pix_fmt->height; + pix->bytesperline =3D pix_fmt->bytesperline; + pix->sizeimage =3D pix_fmt->sizeimage; + pix->pixelformat =3D pix_fmt->fmt->pixelformat; + pix->field =3D V4L2_FIELD_NONE; + + if (f->type =3D=3D V4L2_BUF_TYPE_VIDEO_OUTPUT) { + pix->bytesperline =3D 0; + pix->pixelformat =3D ctx->codec; + } + + pix->ycbcr_enc =3D pix_fmt->ycbcr_enc; + pix->quantization =3D pix_fmt->quantization; + pix->xfer_func =3D pix_fmt->xfer_func; + pix->colorspace =3D pix_fmt->colorspace; + + al_v4l2_dbg( + 3, + "%s : width (%d) , height (%d), bytesperline (%d) , sizeimage (%d)", + (f->type =3D=3D V4L2_BUF_TYPE_VIDEO_CAPTURE) ? "CAP" : "OUT", + pix->width, pix->height, pix->bytesperline, pix->sizeimage); + + return 0; +} + +static int al_dec_s_fmt(struct file *file, void *fh, struct v4l2_format *f) +{ + struct al_dec_ctx *ctx =3D fh_to_ctx(fh, struct al_dec_ctx); + struct v4l2_pix_format *pix; + struct al_frame *frame; + struct vb2_queue *vq; + int ret; + + ret =3D al_dec_try_fmt(file, fh, f); + if (ret) { + al_v4l2_err(ctx->dev, "Cannot set format (%d)", f->type); + return ret; + } + + frame =3D (f->type =3D=3D V4L2_BUF_TYPE_VIDEO_OUTPUT) ? &ctx->src : &ctx-= >dst; + + pix =3D &f->fmt.pix; + frame->fmt =3D al_find_fmt(pix->pixelformat); + if (!frame->fmt) { + al_v4l2_err(ctx->dev, "Unknown format for %d", + pix->pixelformat); + return -EINVAL; + } + + vq =3D v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); + if (vb2_is_streaming(vq)) { + al_v4l2_err(ctx->dev, "queue %d busy", f->type); + return -EBUSY; + } + + frame->width =3D pix->width; + frame->height =3D pix->height; + frame->bytesperline =3D pix->bytesperline; + frame->sizeimage =3D pix->sizeimage; + frame->field =3D pix->field; + + frame->ycbcr_enc =3D pix->ycbcr_enc; + frame->quantization =3D pix->quantization; + frame->xfer_func =3D pix->xfer_func; + frame->colorspace =3D pix->colorspace; + + /* Set decoder pixelformat */ + if (f->type =3D=3D V4L2_BUF_TYPE_VIDEO_OUTPUT) + ctx->codec =3D pix->pixelformat; + + al_v4l2_dbg( + 3, + " %s : width (%d) , height (%d), bytesperline (%d), sizeimage (%d)", + (f->type =3D=3D V4L2_BUF_TYPE_VIDEO_CAPTURE) ? "CAP" : "OUT", + pix->width, pix->height, pix->bytesperline, pix->sizeimage); + + return 0; +} + +static void al_queue_eos_event(struct al_dec_ctx *ctx) +{ + const struct v4l2_event eos_event =3D { + .id =3D 0, + .type =3D V4L2_EVENT_EOS, + }; + + v4l2_event_queue_fh(&ctx->fh, &eos_event); +} + +static void al_queue_res_chg_event(struct al_dec_ctx *ctx) +{ + static const struct v4l2_event ev_src_ch =3D { + .id =3D 0, + .type =3D V4L2_EVENT_SOURCE_CHANGE, + .u.src_change.changes =3D V4L2_EVENT_SRC_CH_RESOLUTION, + }; + + v4l2_event_queue_fh(&ctx->fh, &ev_src_ch); +} + +static int al_dec_decoder_cmd(struct file *file, void *fh, + struct v4l2_decoder_cmd *dcmd) +{ + struct al_dec_ctx *ctx =3D fh_to_ctx(fh, struct al_dec_ctx); + struct v4l2_m2m_ctx *m2m_ctx =3D ctx->fh.m2m_ctx; + struct vb2_v4l2_buffer *vbuf; + struct vb2_queue *dst_vq; + int ret; + + ret =3D v4l2_m2m_ioctl_try_decoder_cmd(file, fh, dcmd); + if (ret) + return ret; + + /* Get the vb2 queue for the Capture */ + dst_vq =3D v4l2_m2m_get_dst_vq(m2m_ctx); + + switch (dcmd->cmd) { + case V4L2_DEC_CMD_START: + vb2_clear_last_buffer_dequeued(dst_vq); + break; + case V4L2_DEC_CMD_STOP: + vbuf =3D v4l2_m2m_last_src_buf(m2m_ctx); + if (vbuf) { + al_v4l2_dbg(1, "marking last pending buffer"); + + vbuf->flags |=3D V4L2_BUF_FLAG_LAST; + if (v4l2_m2m_num_src_bufs_ready(m2m_ctx) =3D=3D 0) { + al_v4l2_dbg(1, "all remaining buffers queued"); + v4l2_m2m_try_schedule(m2m_ctx); + } + } + dec_fw_flush_req(ctx); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int al_dec_enum_framesizes(struct file *file, void *fh, + struct v4l2_frmsizeenum *fsize) +{ + if (!al_find_fmt(fsize->pixel_format)) + return -EINVAL; + + /* FIXME : check step size */ + fsize->type =3D V4L2_FRMSIZE_TYPE_STEPWISE; + fsize->stepwise.min_width =3D DECODER_WIDTH_MIN; + fsize->stepwise.max_width =3D DECODER_WIDTH_MAX; + fsize->stepwise.step_width =3D 8; + fsize->stepwise.min_height =3D DECODER_HEIGHT_MIN; + fsize->stepwise.max_height =3D DECODER_HEIGHT_MAX; + fsize->stepwise.step_height =3D 8; + + return 0; +} + +static int al_dec_subscribe_event(struct v4l2_fh *fh, + const struct v4l2_event_subscription *sub) +{ + switch (sub->type) { + case V4L2_EVENT_EOS: + return v4l2_event_subscribe(fh, sub, 0, NULL); + case V4L2_EVENT_SOURCE_CHANGE: + return v4l2_src_change_event_subscribe(fh, sub); + default: + return -EINVAL; + } + + return 0; +} + +static int al_dec_log_status(struct file *file, void *fh) +{ + struct al_codec_dev *al_dev =3D video_drvdata(file); + + v4l2_device_call_all(&al_dev->v4l2_dev, 0, core, log_status); + return 0; +} + +static const struct v4l2_ioctl_ops al_dec_ioctl_ops =3D { + .vidioc_querycap =3D al_dec_querycap, + .vidioc_enum_fmt_vid_cap =3D al_dec_enum_fmt, + .vidioc_enum_fmt_vid_out =3D al_dec_enum_fmt, + .vidioc_g_fmt_vid_cap =3D al_dec_g_fmt, + .vidioc_g_fmt_vid_out =3D al_dec_g_fmt, + .vidioc_try_fmt_vid_cap =3D al_dec_try_fmt, + .vidioc_try_fmt_vid_out =3D al_dec_try_fmt, + .vidioc_s_fmt_vid_cap =3D al_dec_s_fmt, + .vidioc_s_fmt_vid_out =3D al_dec_s_fmt, + + .vidioc_create_bufs =3D v4l2_m2m_ioctl_create_bufs, + .vidioc_reqbufs =3D v4l2_m2m_ioctl_reqbufs, + + .vidioc_expbuf =3D v4l2_m2m_ioctl_expbuf, + .vidioc_querybuf =3D v4l2_m2m_ioctl_querybuf, + .vidioc_qbuf =3D v4l2_m2m_ioctl_qbuf, + .vidioc_dqbuf =3D v4l2_m2m_ioctl_dqbuf, + .vidioc_prepare_buf =3D v4l2_m2m_ioctl_prepare_buf, + + .vidioc_streamon =3D v4l2_m2m_ioctl_streamon, + .vidioc_streamoff =3D v4l2_m2m_ioctl_streamoff, + .vidioc_log_status =3D al_dec_log_status, + + .vidioc_try_decoder_cmd =3D v4l2_m2m_ioctl_try_decoder_cmd, + .vidioc_decoder_cmd =3D al_dec_decoder_cmd, + .vidioc_enum_framesizes =3D al_dec_enum_framesizes, + + .vidioc_subscribe_event =3D al_dec_subscribe_event, + .vidioc_unsubscribe_event =3D v4l2_event_unsubscribe, +}; + +static void al_device_run(void *priv) +{ + struct al_dec_ctx *ctx =3D priv; + struct vb2_v4l2_buffer *dst_buf; + struct v4l2_m2m_buffer *m2m_buf; + + if (unlikely(!ctx)) + return; + + if (ctx->aborting) { + vb2_queue_error(v4l2_m2m_get_src_vq(ctx->fh.m2m_ctx)); + vb2_queue_error(v4l2_m2m_get_dst_vq(ctx->fh.m2m_ctx)); + return; + } + + if (!v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx)) + goto job_finish; + + dst_buf =3D v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); + if (!dst_buf) + goto job_finish; + + if (!al_common_mcu_is_alive(ctx->dev) || + al_dec_fw_push_frame_buf(ctx, dst_buf)) { + vb2_set_plane_payload(&dst_buf->vb2_buf, 0, 0); + v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_ERROR); + goto job_finish; + } + + mutex_lock(&ctx->buf_q_mlock); + m2m_buf =3D container_of(dst_buf, struct v4l2_m2m_buffer, vb); + list_add_tail(&m2m_buf->list, &ctx->frame_q_list); + mutex_unlock(&ctx->buf_q_mlock); + +job_finish: + v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx); +} + +static const struct v4l2_m2m_ops al_dec_m2m_ops =3D { + .device_run =3D al_device_run, +}; + +static int al_dec_open(struct file *file) +{ + struct video_device *vdev =3D video_devdata(file); + struct al_codec_dev *dev =3D video_get_drvdata(vdev); + struct al_dec_ctx *ctx =3D NULL; + int ret; + + if (mutex_lock_interruptible(&dev->ctx_mlock)) + return -ERESTARTSYS; + + /* Aloocate memory for the dec ctx */ + ctx =3D kzalloc(sizeof(*ctx), GFP_KERNEL); + if (!ctx) { + ret =3D -ENOMEM; + goto unlock; + } + + ctx->dev =3D dev; + /* Init ctx mutex */ + mutex_init(&ctx->buf_q_mlock); + /* Init ctx LISTHEADs*/ + INIT_LIST_HEAD(&ctx->cmd_q_list); + INIT_LIST_HEAD(&ctx->frame_q_list); + INIT_LIST_HEAD(&ctx->stream_q_list); + + /* Init the irq queue */ + init_completion(&ctx->res_done); + + v4l2_fh_init(&ctx->fh, vdev); + + v4l2_ctrl_handler_init(&ctx->ctrl_handler, 0); + if (ctx->ctrl_handler.error) { + ret =3D ctx->ctrl_handler.error; + al_v4l2_err(dev, "Failed to create control %d", ret); + goto handler_error; + } + + ctx->fh.ctrl_handler =3D &ctx->ctrl_handler; + v4l2_ctrl_handler_setup(&ctx->ctrl_handler); + + file->private_data =3D &ctx->fh; + v4l2_fh_add(&ctx->fh); + + /* Set default formats */ + ctx->src =3D ctx->dst =3D al_default_fmt; + + ctx->codec =3D V4L2_PIX_FMT_H264; + ctx->stopped =3D false; + ctx->aborting =3D false; + + /* Setup the ctx for m2m mode */ + ctx->fh.m2m_ctx =3D + v4l2_m2m_ctx_init(dev->m2m_dev, ctx, al_dec_queue_init); + if (IS_ERR(ctx->fh.m2m_ctx)) { + ret =3D PTR_ERR(ctx->fh.m2m_ctx); + al_v4l2_err(dev, "Failed to initialize m2m mode %d", ret); + goto error_ctrls; + } + + v4l2_m2m_set_src_buffered(ctx->fh.m2m_ctx, true); + /* v4l2_m2m_set_dst_buffered(ctx->fh.m2m_ctx, true); */ + + /* Add ctx to the LIST */ + kref_init(&ctx->refcount); + list_add(&ctx->list, &dev->ctx_q_list); + + mutex_unlock(&dev->ctx_mlock); + + return 0; + +error_ctrls: + v4l2_fh_del(&ctx->fh); +handler_error: + v4l2_ctrl_handler_free(&ctx->ctrl_handler); + v4l2_fh_exit(&ctx->fh); + kfree(ctx); + +unlock: + mutex_unlock(&dev->ctx_mlock); + return ret; +} + +static int al_dec_release(struct file *file) +{ + struct al_dec_ctx *ctx =3D + fh_to_ctx(file->private_data, struct al_dec_ctx); + struct al_codec_dev *dev =3D ctx->dev; + + mutex_lock(&dev->ctx_mlock); + + /* It is important to do this before removing ctx from dev list. + * Those commands will trigger some traffic towards fw and so we + * need completion to avoid deadlock if cmds can't find ctx. + */ + v4l2_m2m_ctx_release(ctx->fh.m2m_ctx); + v4l2_ctrl_handler_free(&ctx->ctrl_handler); + v4l2_fh_del(&ctx->fh); + v4l2_fh_exit(&ctx->fh); + + list_del(&ctx->list); + al_ctx_put(ctx); + mutex_unlock(&dev->ctx_mlock); + + return 0; +} + +static inline bool al_mark_last_dst_buf(struct al_dec_ctx *ctx) +{ + struct vb2_v4l2_buffer *buf; + struct vb2_buffer *dst_vb; + struct vb2_queue *dst_vq; + unsigned long flags; + + al_v4l2_dbg(1, "marking last capture buffer"); + + dst_vq =3D v4l2_m2m_get_vq(ctx->fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE); + spin_lock_irqsave(&dst_vq->done_lock, flags); + if (list_empty(&dst_vq->done_list)) { + spin_unlock_irqrestore(&dst_vq->done_lock, flags); + return false; + } + + dst_vb =3D list_last_entry(&dst_vq->done_list, struct vb2_buffer, + done_entry); + buf =3D to_vb2_v4l2_buffer(dst_vb); + buf->flags |=3D V4L2_BUF_FLAG_LAST; + + spin_unlock_irqrestore(&dst_vq->done_lock, flags); + return true; +} + +static const struct v4l2_file_operations al_dec_file_ops =3D { + .owner =3D THIS_MODULE, + .open =3D al_dec_open, + .release =3D al_dec_release, + .poll =3D v4l2_m2m_fop_poll, + .unlocked_ioctl =3D video_ioctl2, + .mmap =3D v4l2_m2m_fop_mmap, +}; + +static void handle_error_evt(struct al_dec_ctx *ctx, struct msg_itf_header= *hdr) +{ + struct al_codec_dev *dev =3D ctx->dev; + struct msg_itf_evt_error evt; + struct v4l2_m2m_buffer *vbuf; + + if (al_common_get_data(&dev->common, (char *)&evt, hdr->payload_len)) { + al_v4l2_err(dev, "Unable to get resolution found event"); + return; + } + + al_v4l2_err(dev, "Decoding error %d", evt.errno); + + mutex_lock(&ctx->buf_q_mlock); + if (!list_empty(&ctx->stream_q_list)) { + vbuf =3D list_last_entry(&ctx->frame_q_list, + struct v4l2_m2m_buffer, list); + list_del(&vbuf->list); + v4l2_m2m_buf_done(&vbuf->vb, VB2_BUF_STATE_ERROR); + } + mutex_unlock(&ctx->buf_q_mlock); +} + +static void handle_resolution_found_evt(struct al_dec_ctx *ctx, + struct msg_itf_header *hdr) +{ + struct msg_itf_evt_resolution_found evt; + struct al_codec_dev *dev =3D ctx->dev; + struct al_frame *frame; + struct vb2_queue *dst_vq; + + if (al_common_get_data(&dev->common, (char *)&evt, hdr->payload_len)) { + al_v4l2_err(dev, "Unable to get resolution found event"); + return; + } + + frame =3D &ctx->dst; + + if (frame->width !=3D evt.width || frame->height !=3D evt.height || + frame->nbuffers < evt.buffer_nb) { + /* Update frame properties */ + frame->width =3D evt.width; + frame->height =3D evt.height; + frame->bytesperline =3D evt.bytesperline; + frame->sizeimage =3D evt.sizeimage; + frame->nbuffers =3D evt.buffer_nb; + frame->fmt =3D al_find_fmt(evt.pixelformat); + + /* This has to be changed */ + if (!frame->fmt) + return; + + al_queue_res_chg_event(ctx); + } + + dst_vq =3D v4l2_m2m_get_dst_vq(ctx->fh.m2m_ctx); + if (!vb2_is_streaming(dst_vq)) + complete(&ctx->res_done); + + al_v4l2_dbg( + 3, + "width(%d) , height(%d), bytesperline(%d), sizeimage(%d), n_bufs(%d)", + frame->width, frame->height, frame->bytesperline, + frame->sizeimage, frame->nbuffers); +} + +static void handle_bitstream_buffer_release_evt(struct al_dec_ctx *ctx, + struct msg_itf_header *hdr) +{ + struct msg_itf_evt_bitstream_buffer_release evt; + struct al_codec_dev *dev =3D ctx->dev; + struct vb2_v4l2_buffer *vbuf; + + if (al_common_get_data(&dev->common, (char *)&evt, hdr->payload_len)) { + al_v4l2_err(dev, "Unable to get buffer release event"); + return; + } + + if (ctx->stopped) + return; + + vbuf =3D al_dec_dequeue_src_buf(ctx, evt.bufferHandle); + if (!vbuf) { + al_v4l2_err(dev, "Unable to find bitsream buffer 0x%llx", + evt.bufferHandle); + return; + } + + al_v4l2_dbg(3, "Release bitstream buffer %p", vbuf); + v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_DONE); +} + +static void handle_eos_evt(struct al_dec_ctx *ctx, struct msg_itf_header *= hdr) +{ + struct msg_itf_evt_frame_buffer_decode evt; + struct al_codec_dev *dev =3D ctx->dev; + + if (al_common_get_data(&dev->common, (char *)&evt, hdr->payload_len)) { + al_v4l2_err(dev, "Unable to get frame buffer event"); + return; + } + + /* set LAST_FLAG to the last done CAPTURE buffer*/ + al_mark_last_dst_buf(ctx); + /* Set eos event */ + al_queue_eos_event(ctx); +} + +static void handle_frame_buffer_decode_evt(struct al_dec_ctx *ctx, + struct msg_itf_header *hdr) +{ + struct msg_itf_evt_frame_buffer_decode evt; + struct al_codec_dev *dev =3D ctx->dev; + struct vb2_v4l2_buffer *vbuf; + struct al_buffer_meta *meta; + + if (al_common_get_data(&dev->common, (char *)&evt, hdr->payload_len)) { + al_v4l2_err(dev, "Unable to get frame buffer event"); + return; + } + + vbuf =3D al_dec_dequeue_dst_buf(ctx, evt.bufferHandle); + if (!vbuf) { + al_v4l2_err(dev, "Unable to find frame buffer 0x%llx", + evt.bufferHandle); + return; + } + + meta =3D &evt.meta; + al_v4l2_dbg(3, "Decoded frame done for buffer %p (%d) (%lld)", vbuf, + meta->last, evt.size); + + vb2_set_plane_payload(&vbuf->vb2_buf, 0, evt.size); + vbuf->field =3D V4L2_FIELD_NONE; + vbuf->sequence =3D ctx->csequence++; + vbuf->timecode =3D meta->timecode; + vbuf->vb2_buf.timestamp =3D meta->timestamp; + + if (meta->last || (vbuf->flags & V4L2_BUF_FLAG_LAST)) { + vbuf->flags |=3D V4L2_BUF_FLAG_LAST; + v4l2_m2m_mark_stopped(ctx->fh.m2m_ctx); + } + + v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_DONE); +} + +static int al_handle_cmd_reply(struct al_codec_dev *dev, + struct msg_itf_header *hdr) +{ + struct al_dec_ctx *ctx; + struct al_codec_cmd *cmd =3D NULL; + int ret =3D 0; + + ctx =3D al_ctx_get(dev, hdr->drv_ctx_hdl); + if (IS_ERR_OR_NULL(ctx)) { + al_v4l2_err(dev, "Unable to find ctx %p for reply %d", + al_phys_to_virt(hdr->drv_ctx_hdl), hdr->type); + return -EINVAL; + } + + cmd =3D al_codec_cmd_get(&ctx->cmd_q_list, hdr->drv_cmd_hdl); + if (!cmd) { + al_v4l2_err(dev, "Unable to find command %p for reply %d", + al_phys_to_virt(hdr->drv_cmd_hdl), hdr->type); + ret =3D -EINVAL; + goto ctx_put; + } + + if (cmd->reply_size !=3D hdr->payload_len) { + al_v4l2_err(dev, "mismatch size %d %d", cmd->reply_size, + hdr->payload_len); + ret =3D -EINVAL; + goto cmd_put; + } + + ret =3D al_common_get_data(&dev->common, cmd->reply, hdr->payload_len); + if (ret) + al_v4l2_err(dev, "Unable to copy reply"); + + complete(&cmd->done); + ret =3D 0; + +cmd_put: + al_codec_cmd_put(cmd); +ctx_put: + al_ctx_put(ctx); + + return ret; +} + +static int al_handle_cmd_evt(struct al_codec_dev *dev, + struct msg_itf_header *hdr, int type) +{ + static u32 evt_sizes[] =3D { + sizeof(struct msg_itf_evt_error), + sizeof(struct msg_itf_evt_resolution_found), + sizeof(struct msg_itf_evt_bitstream_buffer_release), + sizeof(struct msg_itf_evt_frame_buffer_decode), + sizeof(struct msg_itf_evt_eos), + }; + + u32 evt_size; + struct al_dec_ctx *ctx =3D NULL; + int ret =3D 0; + + if (type < MSG_ITF_TYPE_NEXT_EVT || type > MSG_ITF_TYPE_END_EVT) { + al_v4l2_err(dev, "Unsupporting event type %d", type); + return -EINVAL; + } + + ctx =3D al_ctx_get(dev, hdr->drv_ctx_hdl); + if (!ctx) { + al_v4l2_err(dev, "Unable to find ctx %p for evt %d", + al_phys_to_virt(hdr->drv_ctx_hdl), type); + return -EINVAL; + } + + // Check the received event size and the expected one + evt_size =3D evt_sizes[type - MSG_ITF_TYPE_NEXT_EVT]; + if (hdr->payload_len !=3D evt_size) { + al_v4l2_err( + dev, + "Invalid event size for client (%p) for evt (%d) : Got (%d), expected (= %d)", + al_phys_to_virt(hdr->drv_ctx_hdl), type, + hdr->payload_len, evt_size); + ret =3D -EINVAL; + goto clean_ctx; + } + + al_v4l2_dbg(3, "Event received from MCU (%d)", type); + + switch (type) { + case MSG_ITF_TYPE_EVT_ERROR: + handle_error_evt(ctx, hdr); + break; + case MSG_ITF_TYPE_EVT_RESOLUTION_FOUND: + handle_resolution_found_evt(ctx, hdr); + break; + case MSG_ITF_TYPE_EVT_BITSTREAM_BUFFER_RELEASE: + handle_bitstream_buffer_release_evt(ctx, hdr); + break; + case MSG_ITF_TYPE_EVT_FRAME_BUFFER_DECODE: + handle_frame_buffer_decode_evt(ctx, hdr); + break; + case MSG_ITF_TYPE_EVT_EOS: + handle_eos_evt(ctx, hdr); + break; + default: + break; + } + +clean_ctx: + al_ctx_put(ctx); + return ret; +} + +static void al_dec_process_msg(void *cb_arg, struct msg_itf_header *hdr) +{ + struct al_codec_dev *dev =3D cb_arg; + int ret; + + if (is_type_reply(hdr->type)) + ret =3D al_handle_cmd_reply(dev, hdr); + else if (is_type_event(hdr->type)) + ret =3D al_handle_cmd_evt(dev, hdr, hdr->type); + else { + al_v4l2_err(dev, "Unsupported message type %d", hdr->type); + ret =3D -EINVAL; + } + + if (ret) { + al_v4l2_err(dev, "Skip received data"); + al_common_skip_data(&dev->common, hdr->payload_len); + } +} + +static const struct video_device al_videodev =3D { + .name =3D "allegro-decoder", + .fops =3D &al_dec_file_ops, + .ioctl_ops =3D &al_dec_ioctl_ops, + .minor =3D -1, + .release =3D video_device_release_empty, + .vfl_dir =3D VFL_DIR_M2M, + .device_caps =3D V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING, +}; + +static void al_dec_register_v4l2(void *cb_arg) +{ + struct al_codec_dev *dev =3D cb_arg; + struct video_device *video_dev =3D NULL; + int ret; + + ret =3D v4l2_device_register(&dev->common.pdev->dev, &dev->v4l2_dev); + if (ret) { + al_v4l2_err(dev, "Unable to register v4l2 device %d", ret); + return; + } + + dev->m2m_dev =3D v4l2_m2m_init(&al_dec_m2m_ops); + if (IS_ERR(dev->m2m_dev)) { + ret =3D PTR_ERR(dev->m2m_dev); + al_v4l2_err(dev, "failed to init mem2mem device %d", ret); + goto v4l2_m2m_init_error; + } + + video_dev =3D &dev->video_dev; + *video_dev =3D al_videodev; + + video_dev->lock =3D &dev->lock; + video_dev->v4l2_dev =3D &dev->v4l2_dev; + + video_set_drvdata(video_dev, dev); + ret =3D video_register_device(video_dev, VFL_TYPE_VIDEO, -1); + if (ret) { + al_v4l2_err(dev, "failed to register video device %d", ret); + goto video_register_device_error; + } + + v4l2_info(&dev->v4l2_dev, "registered as /dev/video%d\n", + dev->video_dev.num); + + dev->is_video_init_done =3D 1; + + return; + +video_register_device_error: + v4l2_m2m_release(dev->m2m_dev); +v4l2_m2m_init_error: + v4l2_device_unregister(&dev->v4l2_dev); +} + +static int al_dec_probe(struct platform_device *pdev) +{ + struct al_codec_dev *al_dev; + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev->of_node; + const struct al_match_data *match_data; + int ret; + + dev_info(dev, "Probing ...\n"); + + match_data =3D device_get_match_data(dev); + if (!match_data) { + dev_err(dev, "Missing device match data\n"); + return -EINVAL; + } + + al_dev =3D devm_kzalloc(dev, sizeof(*al_dev), GFP_KERNEL); + if (!al_dev) + return -ENOMEM; + + al_dev->is_video_init_done =3D 0; + mutex_init(&al_dev->lock); + mutex_init(&al_dev->ctx_mlock); + INIT_LIST_HEAD(&al_dev->ctx_q_list); + + al_dev->common.cb_arg =3D al_dev; + al_dev->common.process_msg_cb =3D al_dec_process_msg; + al_dev->common.fw_ready_cb =3D al_dec_register_v4l2; + + /* firmware-name is optional in DT */ + of_property_read_string(np, "firmware-name", &al_dev->common.fw_name); + if (!al_dev->common.fw_name) + al_dev->common.fw_name =3D match_data->fw_name; + + ret =3D al_common_probe(pdev, &al_dev->common); + if (ret) + return ret; + + platform_set_drvdata(pdev, al_dev); + dev_info(dev, "Probing done successfully %p\n", al_dev); + + return 0; +} + +static void al_dec_remove(struct platform_device *pdev) +{ + struct al_codec_dev *dev =3D platform_get_drvdata(pdev); + + dev_info(&pdev->dev, "remove %p\n", dev); + + if (dev->is_video_init_done) { + video_unregister_device(&dev->video_dev); + if (dev->m2m_dev) + v4l2_m2m_release(dev->m2m_dev); + v4l2_device_unregister(&dev->v4l2_dev); + } + + al_common_remove(&dev->common); +} + +static const struct al_match_data ald300_data =3D { + .fw_name =3D "al300-vdec.fw", +}; + +static const struct of_device_id v4l2_al_dec_dt_match[] =3D { + { .compatible =3D "allegrodvt,al300-vdec", .data =3D &ald300_data }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, v4l2_al_dec_dt_match); + +static struct platform_driver al300_vdec_drv =3D { + .probe =3D al_dec_probe, + .remove =3D al_dec_remove, + .driver =3D { + .name =3D "al300_vdec", + .of_match_table =3D of_match_ptr(v4l2_al_dec_dt_match), + }, +}; + +module_platform_driver(al300_vdec_drv); + +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:al300-vdec"); +MODULE_AUTHOR("Yassine OUAISSA "); +MODULE_DESCRIPTION("Allegro DVT V4l2 decoder driver gen 3"); diff --git a/drivers/media/platform/allegro-dvt/al300/al_vdec_drv.h b/drive= rs/media/platform/allegro-dvt/al300/al_vdec_drv.h new file mode 100644 index 000000000000..ec1a7c450300 --- /dev/null +++ b/drivers/media/platform/allegro-dvt/al300/al_vdec_drv.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2025 Allegro DVT. + * Author: Yassine OUAISSA + */ + +#ifndef __AL_VDEC_DRV__ +#define __AL_VDEC_DRV__ + +#include "al_codec_util.h" + +enum { + MSG_ITF_TYPE_EVT_RESOLUTION_FOUND =3D MSG_ITF_TYPE_NEXT_EVT + 1, + MSG_ITF_TYPE_EVT_BITSTREAM_BUFFER_RELEASE, + MSG_ITF_TYPE_EVT_FRAME_BUFFER_DECODE, + MSG_ITF_TYPE_EVT_EOS, + /* Mark the end of the events list.*/ + MSG_ITF_TYPE_END_EVT, +}; + +struct msg_itf_create_decoder_req { + unsigned int codec; +} __packed; +DECLARE_FULL_REQ(msg_itf_create_decoder_req); + +struct msg_itf_evt_resolution_found { + u16 buffer_nb; + u16 width; + u16 height; + u32 pixelformat; + u32 sizeimage; + u32 bytesperline; +} __packed; +DECLARE_FULL_EVENT(msg_itf_evt_resolution_found); + +struct msg_itf_evt_bitstream_buffer_release { + u64 bufferHandle; +} __packed; +DECLARE_FULL_EVENT(msg_itf_evt_bitstream_buffer_release); + +struct msg_itf_evt_frame_buffer_decode { + u64 bufferHandle; + u64 size; + struct al_buffer_meta meta; +} __packed; +DECLARE_FULL_EVENT(msg_itf_evt_frame_buffer_decode); + +struct msg_itf_evt_eos { + u32 unused; +} __packed; +DECLARE_FULL_EVENT(msg_itf_evt_eos); + +struct al_fmt { + u32 pixelformat; + u8 bpp; +}; + +struct al_frame { + u32 width; + u32 height; + u32 bytesperline; + u32 sizeimage; + u32 nbuffers; + const struct al_fmt *fmt; + enum v4l2_field field; + enum v4l2_colorspace colorspace; + enum v4l2_ycbcr_encoding ycbcr_enc; + enum v4l2_quantization quantization; + enum v4l2_xfer_func xfer_func; +}; + +struct al_dec_ctx { + struct al_codec_dev *dev; + struct v4l2_fh fh; + struct v4l2_ctrl_handler ctrl_handler; + struct kref refcount; + struct list_head list; + /* CAP and OUT frames */ + struct al_frame src; + struct al_frame dst; + struct completion res_done; /* Resolution found event */ + u32 codec; + u64 hDec; + struct list_head cmd_q_list; /* Store active commands */ + struct mutex buf_q_mlock; + struct list_head frame_q_list; + struct list_head stream_q_list; + u32 csequence; + u32 osequence; + bool stopped; + bool aborting; +}; + +#endif /*__AL_VDEC_DRV__*/ --=20 2.30.2