From nobody Sun Feb 8 04:30:11 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E17D1DDC1D for ; Tue, 13 May 2025 03:06:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747105620; cv=none; b=JM7lqbl0pg9sY+DbgQAdgy/+XsUiOMPOHr8x5ZUTUrkiHD6mDJxPslwyiqBb2BrFtKFH9u4i+VNwQmUz3J9yt+sckPims4yRlVGgAoxXng2Ez4U0ImzzeCHhfFodrzjH1UA0xAznSp31dz1+ajhdih2IpIEuY14cKSMlWMGw+w8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747105620; c=relaxed/simple; bh=dkEzf3fERGNelIlwIbaM/aGOYl9K+/v/DBApTCPauF8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QiCkrhG3FZpEgMPwyiCLD+m2l/utSSJHnCjpaWRJpa1aR6E2gA1pxlZcyFOsCHFVvjbRULjI73drbIVmayIs9TIMJ+hafC8cNKEH2CvggiAXoH9YSBI1/XWOg1FLRog9bTqHOLUh84mPAbAjQA+p6o85AlqyhF91cVZOxfVPJX0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=WC7yq1Vv; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="WC7yq1Vv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1747105618; x=1778641618; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dkEzf3fERGNelIlwIbaM/aGOYl9K+/v/DBApTCPauF8=; b=WC7yq1VvclIcJh+qjZ55kGfqHT9kJh7qhdNC3ePiWmChCgLNO4r4sSwJ aFb70lLibzv9YFe1FfJhckcj48os0Ev0m3eG1r2/R4tYz0yp/wva9JqPP wSZpx0OQ382w8fiDcF15x11eX8a5t7Pi1BCoxpA5UxRxcVX0XtRzotdcV Vs6xwy6X8fw8kEVKPrip4cQPeyVT5+/RAWXq4jQx6iH3Qd3O3CZlpjRF2 26v4h/7qqDqTLc9NvFwpbRn9IkTSv2mMXS6Scd4PWd6jkV38uKRdfTcjp kvoxg7H1FwP2irPWSeF7MZ4PhjBTR2sE8UhQFktqQq9b2/8yI7EmBAdLf A==; X-CSE-ConnectionGUID: fTQPhc8aQtueWMbcSAjM4A== X-CSE-MsgGUID: X5soquF8TcagEsEzfcb+CQ== X-IronPort-AV: E=McAfee;i="6700,10204,11431"; a="52735273" X-IronPort-AV: E=Sophos;i="6.15,284,1739865600"; d="scan'208";a="52735273" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2025 20:06:57 -0700 X-CSE-ConnectionGUID: Pw5tydATR82L6wqop+5lhg== X-CSE-MsgGUID: ylizIxMRTCC+mvAibLR/Ug== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,284,1739865600"; d="scan'208";a="138522216" Received: from allen-box.sh.intel.com ([10.239.159.52]) by fmviesa009.fm.intel.com with ESMTP; 12 May 2025 20:06:57 -0700 From: Lu Baolu To: Joerg Roedel Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 1/5] iommu/vt-d: Restore WO permissions on second-level paging entries Date: Tue, 13 May 2025 11:07:35 +0800 Message-ID: <20250513030739.2718555-2-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513030739.2718555-1-baolu.lu@linux.intel.com> References: <20250513030739.2718555-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jason Gunthorpe VT-D HW can do WO permissions on the second-stage but not the first-stage page table formats. The commit eea53c581688 ("iommu/vt-d: Remove WO permissions on second-level paging entries") wanted to make this uniform for VT-D by disabling the support for WO permissions in the second-stage. This isn't consistent with how other drivers are working. Instead if the underlying HW can support WO, it should. For instance AMD already supports WO on its second stage (v1) format and not its first (v2). If WO support needs to be discoverable it should be done through an iommu_domain capability flag. Signed-off-by: Jason Gunthorpe Reviewed-by: Kevin Tian Link: https://lore.kernel.org/r/0-v1-c26553717e90+65f-iommu_vtd_ss_wo_jgg@n= vidia.com Signed-off-by: Lu Baolu --- drivers/iommu/intel/iommu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index cb0b993bebb4..67c6ea1d8d44 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -1681,9 +1681,8 @@ __domain_mapping(struct dmar_domain *domain, unsigned= long iov_pfn, } =20 attr =3D prot & (DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP); - attr |=3D DMA_FL_PTE_PRESENT; if (domain->use_first_level) { - attr |=3D DMA_FL_PTE_US | DMA_FL_PTE_ACCESS; + attr |=3D DMA_FL_PTE_PRESENT | DMA_FL_PTE_US | DMA_FL_PTE_ACCESS; if (prot & DMA_PTE_WRITE) attr |=3D DMA_FL_PTE_DIRTY; } --=20 2.43.0 From nobody Sun Feb 8 04:30:11 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1CCD1D6DB4 for ; Tue, 13 May 2025 03:06:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747105621; cv=none; b=D6k9J/pY+qLIRtSw4WeI3wL0XvqxK5sqT60R/QmMnd+YgsLcAOR9+tyAfRN4Ulue+qvIQuwDlp76Xi5bxYOuSSO1aiArh98wo9gTxJDDIRVXNKmcZeXZf3eQT1srOJ+e78SbgD4Zc7ryZLunxUlYdre9xEjF4C/Fxz29r6fR7aI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747105621; c=relaxed/simple; bh=gkabQMWS1jUb5adlyFWFdTaBwWerIYg1lXMMuQ9p+WE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kWj52c37t7E94Idi0nnA6bpTt3nbQmjOtvtkwfY6fMc8qDVa39txbT79K9BJ3Lbfw4MWDNqZqNinvTfPQ2QmGm3vv65bam6tpie6wXZLv0gItzblYx4IMRoxdJPZKbXz6keKQnJI6gUCAmP83EG6YBzl6AqAZAoQqTP3AY945Vs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=VEOpEAGI; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="VEOpEAGI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1747105619; x=1778641619; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gkabQMWS1jUb5adlyFWFdTaBwWerIYg1lXMMuQ9p+WE=; b=VEOpEAGIJajdpFg4PJEp7j/NmaqjyL0QrVgNdGKuK5Cp5OOP93GiEN3T wRoGM2jNK4S16OHAbnppM7/OCd4KEhbuyCy1UnwwbJJLPk6VUSPYGjJik tb90SYZXJGL6x0r2zBusbzuChDGMB7NI5/zT7UqkqmGBw3l8oRu35Hv8K Q2Q1+YJdGO0fzKcBSNG4MmINAOrcswr2akC+ddBItb9BMSWN7JNDyb3wu xyo1FcvUGApWuteygKgKGB8BTEo8B3GjLmTKzoS47t1Xv/g/aHMi7xdm/ oB9603/0pfegwwYXeGnFamQieqsOs6EGNbk6YzShPweaofInSkWiX96Pm w==; X-CSE-ConnectionGUID: kjc2vjkpQMu9IdPH2TEfTw== X-CSE-MsgGUID: vTBdLYVTSZS3+1smewcfMg== X-IronPort-AV: E=McAfee;i="6700,10204,11431"; a="52735276" X-IronPort-AV: E=Sophos;i="6.15,284,1739865600"; d="scan'208";a="52735276" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2025 20:06:59 -0700 X-CSE-ConnectionGUID: cvW6KDV7RcqIEJzFaZz2+w== X-CSE-MsgGUID: RMHKh5WKQMCSyxeo28DqZQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,284,1739865600"; d="scan'208";a="138522217" Received: from allen-box.sh.intel.com ([10.239.159.52]) by fmviesa009.fm.intel.com with ESMTP; 12 May 2025 20:06:58 -0700 From: Lu Baolu To: Joerg Roedel Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 2/5] iommu/vt-d: Use ida to manage domain id Date: Tue, 13 May 2025 11:07:36 +0800 Message-ID: <20250513030739.2718555-3-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513030739.2718555-1-baolu.lu@linux.intel.com> References: <20250513030739.2718555-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Switch the intel iommu driver to use the ida mechanism for managing domain IDs, replacing the previous fixed-size bitmap. The previous approach allocated a bitmap large enough to cover the maximum number of domain IDs supported by the hardware, regardless of the actual number of domains in use. This led to unnecessary memory consumption, especially on systems supporting a large number of iommu units but only utilizing a small number of domain IDs. The ida allocator dynamically manages the allocation and freeing of integer IDs, only consuming memory for the IDs that are currently in use. This significantly optimizes memory usage compared to the fixed-size bitmap. Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian Reviewed-by: Jason Gunthorpe Link: https://lore.kernel.org/r/20250430021135.2370244-2-baolu.lu@linux.int= el.com --- drivers/iommu/intel/dmar.c | 3 ++ drivers/iommu/intel/iommu.c | 80 ++++++++----------------------------- drivers/iommu/intel/iommu.h | 19 +++++++-- 3 files changed, 34 insertions(+), 68 deletions(-) diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c index e540092d664d..0e35969c026b 100644 --- a/drivers/iommu/intel/dmar.c +++ b/drivers/iommu/intel/dmar.c @@ -1099,6 +1099,8 @@ static int alloc_iommu(struct dmar_drhd_unit *drhd) spin_lock_init(&iommu->device_rbtree_lock); mutex_init(&iommu->iopf_lock); iommu->node =3D NUMA_NO_NODE; + spin_lock_init(&iommu->lock); + ida_init(&iommu->domain_ida); =20 ver =3D readl(iommu->reg + DMAR_VER_REG); pr_info("%s: reg_base_addr %llx ver %d:%d cap %llx ecap %llx\n", @@ -1195,6 +1197,7 @@ static void free_iommu(struct intel_iommu *iommu) if (iommu->reg) unmap_iommu(iommu); =20 + ida_destroy(&iommu->domain_ida); ida_free(&dmar_seq_ids, iommu->seq_id); kfree(iommu); } diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 67c6ea1d8d44..0cac6b00adb0 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -1289,52 +1289,13 @@ static void iommu_disable_translation(struct intel_= iommu *iommu) raw_spin_unlock_irqrestore(&iommu->register_lock, flag); } =20 -static int iommu_init_domains(struct intel_iommu *iommu) -{ - u32 ndomains; - - ndomains =3D cap_ndoms(iommu->cap); - pr_debug("%s: Number of Domains supported <%d>\n", - iommu->name, ndomains); - - spin_lock_init(&iommu->lock); - - iommu->domain_ids =3D bitmap_zalloc(ndomains, GFP_KERNEL); - if (!iommu->domain_ids) - return -ENOMEM; - - /* - * If Caching mode is set, then invalid translations are tagged - * with domain-id 0, hence we need to pre-allocate it. We also - * use domain-id 0 as a marker for non-allocated domain-id, so - * make sure it is not used for a real domain. - */ - set_bit(0, iommu->domain_ids); - - /* - * Vt-d spec rev3.0 (section 6.2.3.1) requires that each pasid - * entry for first-level or pass-through translation modes should - * be programmed with a domain id different from those used for - * second-level or nested translation. We reserve a domain id for - * this purpose. This domain id is also used for identity domain - * in legacy mode. - */ - set_bit(FLPT_DEFAULT_DID, iommu->domain_ids); - - return 0; -} - static void disable_dmar_iommu(struct intel_iommu *iommu) { - if (!iommu->domain_ids) - return; - /* * All iommu domains must have been detached from the devices, * hence there should be no domain IDs in use. */ - if (WARN_ON(bitmap_weight(iommu->domain_ids, cap_ndoms(iommu->cap)) - > NUM_RESERVED_DID)) + if (WARN_ON(!ida_is_empty(&iommu->domain_ida))) return; =20 if (iommu->gcmd & DMA_GCMD_TE) @@ -1343,11 +1304,6 @@ static void disable_dmar_iommu(struct intel_iommu *i= ommu) =20 static void free_dmar_iommu(struct intel_iommu *iommu) { - if (iommu->domain_ids) { - bitmap_free(iommu->domain_ids); - iommu->domain_ids =3D NULL; - } - if (iommu->copied_tables) { bitmap_free(iommu->copied_tables); iommu->copied_tables =3D NULL; @@ -1380,7 +1336,6 @@ static bool first_level_by_default(struct intel_iommu= *iommu) int domain_attach_iommu(struct dmar_domain *domain, struct intel_iommu *io= mmu) { struct iommu_domain_info *info, *curr; - unsigned long ndomains; int num, ret =3D -ENOSPC; =20 if (domain->domain.type =3D=3D IOMMU_DOMAIN_SVA) @@ -1399,14 +1354,13 @@ int domain_attach_iommu(struct dmar_domain *domain,= struct intel_iommu *iommu) return 0; } =20 - ndomains =3D cap_ndoms(iommu->cap); - num =3D find_first_zero_bit(iommu->domain_ids, ndomains); - if (num >=3D ndomains) { + num =3D ida_alloc_range(&iommu->domain_ida, IDA_START_DID, + cap_ndoms(iommu->cap) - 1, GFP_ATOMIC); + if (num < 0) { pr_err("%s: No free domain ids\n", iommu->name); goto err_unlock; } =20 - set_bit(num, iommu->domain_ids); info->refcnt =3D 1; info->did =3D num; info->iommu =3D iommu; @@ -1421,7 +1375,7 @@ int domain_attach_iommu(struct dmar_domain *domain, s= truct intel_iommu *iommu) return 0; =20 err_clear: - clear_bit(info->did, iommu->domain_ids); + ida_free(&iommu->domain_ida, info->did); err_unlock: spin_unlock(&iommu->lock); kfree(info); @@ -1438,7 +1392,7 @@ void domain_detach_iommu(struct dmar_domain *domain, = struct intel_iommu *iommu) spin_lock(&iommu->lock); info =3D xa_load(&domain->iommu_array, iommu->seq_id); if (--info->refcnt =3D=3D 0) { - clear_bit(info->did, iommu->domain_ids); + ida_free(&iommu->domain_ida, info->did); xa_erase(&domain->iommu_array, iommu->seq_id); domain->nid =3D NUMA_NO_NODE; kfree(info); @@ -2041,7 +1995,7 @@ static int copy_context_table(struct intel_iommu *iom= mu, =20 did =3D context_domain_id(&ce); if (did >=3D 0 && did < cap_ndoms(iommu->cap)) - set_bit(did, iommu->domain_ids); + ida_alloc_range(&iommu->domain_ida, did, did, GFP_KERNEL); =20 set_context_copied(iommu, bus, devfn); new_ce[idx] =3D ce; @@ -2168,11 +2122,6 @@ static int __init init_dmars(void) } =20 intel_iommu_init_qi(iommu); - - ret =3D iommu_init_domains(iommu); - if (ret) - goto free_iommu; - init_translation_status(iommu); =20 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) { @@ -2650,9 +2599,7 @@ static int intel_iommu_add(struct dmar_drhd_unit *dma= ru) if (iommu->gcmd & DMA_GCMD_TE) iommu_disable_translation(iommu); =20 - ret =3D iommu_init_domains(iommu); - if (ret =3D=3D 0) - ret =3D iommu_alloc_root_entry(iommu); + ret =3D iommu_alloc_root_entry(iommu); if (ret) goto out; =20 @@ -2971,9 +2918,14 @@ static ssize_t domains_used_show(struct device *dev, struct device_attribute *attr, char *buf) { struct intel_iommu *iommu =3D dev_to_intel_iommu(dev); - return sysfs_emit(buf, "%d\n", - bitmap_weight(iommu->domain_ids, - cap_ndoms(iommu->cap))); + unsigned int count =3D 0; + int id; + + for (id =3D 0; id < cap_ndoms(iommu->cap); id++) + if (ida_exists(&iommu->domain_ida, id)) + count++; + + return sysfs_emit(buf, "%d\n", count); } static DEVICE_ATTR_RO(domains_used); =20 diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index c4916886da5a..25faf3aadd24 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -722,7 +722,7 @@ struct intel_iommu { unsigned char name[16]; /* Device Name */ =20 #ifdef CONFIG_INTEL_IOMMU - unsigned long *domain_ids; /* bitmap of domains */ + struct ida domain_ida; /* domain id allocator */ unsigned long *copied_tables; /* bitmap of copied tables */ spinlock_t lock; /* protect context, domain ids */ struct root_entry *root_entry; /* virtual address */ @@ -809,11 +809,22 @@ static inline struct dmar_domain *to_dmar_domain(stru= ct iommu_domain *dom) } =20 /* - * Domain ID reserved for pasid entries programmed for first-level - * only and pass-through transfer modes. + * Domain ID 0 and 1 are reserved: + * + * If Caching mode is set, then invalid translations are tagged + * with domain-id 0, hence we need to pre-allocate it. We also + * use domain-id 0 as a marker for non-allocated domain-id, so + * make sure it is not used for a real domain. + * + * Vt-d spec rev3.0 (section 6.2.3.1) requires that each pasid + * entry for first-level or pass-through translation modes should + * be programmed with a domain id different from those used for + * second-level or nested translation. We reserve a domain id for + * this purpose. This domain id is also used for identity domain + * in legacy mode. */ #define FLPT_DEFAULT_DID 1 -#define NUM_RESERVED_DID 2 +#define IDA_START_DID 2 =20 /* Retrieve the domain ID which has allocated to the domain */ static inline u16 --=20 2.43.0 From nobody Sun Feb 8 04:30:11 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 945BB1DF263 for ; Tue, 13 May 2025 03:07:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747105623; cv=none; b=JGW3WyyPr35HBJbou0F0YMuyEVtc4jRHLb77qtfgUBD9aYooDoK9hVewAZgFmgU1CgJhqBXIN5ZRQMPA9AcIdmLYQSguepbvvAhZgKTOiDuoVg0JNd7168CobFrnATJueoHe4N4aDKoKkFYqtMKFg8U7g8G44ooEv851pd6gWUY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747105623; c=relaxed/simple; bh=1xqhyyEGB53nQW/bS56g7TAle2WNHptoTEpXYCvotC8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BSdMxr9rYxk3y+OSk7QDVpKjKxJsye3SwqeP7HzEP9BtvaxiyG6UnHpZlBK1W3yammupN9zpDSja9BVt4JQcCE5ZxsmgXLioFdBI3Q+pxdylUvPIYlJDw12J5Z3s2/5+wqkumskH5YnCNeDGeWb4rhRNdhl2myURNYK+/5RreqE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=TZzYfn8R; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="TZzYfn8R" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1747105621; x=1778641621; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1xqhyyEGB53nQW/bS56g7TAle2WNHptoTEpXYCvotC8=; b=TZzYfn8RSP00giIEZ4UInoyqQ8cMblxCEQJOz0RBfqdr6DFS7GV/MuLN z5QP3zM+9RoJpArdgOr//ConMp5jX1wZiNnhoDMAeLayQGAn86MnNHeci 0EjLJxnzuysHMwhCxnqYAps5C5JFFA01BxoZue8xctNWF6X+KtopyZWrh cN2LKWmywwwfeMjpgt1mu095QO9EecM2b0E8y7T3xqGXs/NKBTB8XaW6y wM8xqmMHPszPW5tCWCfjcLZQWi+BCGFBDifV94ohs21DzTDNR3XGHC8Fs 2nbvZEVVAN9EVvsDgrzTudRZ5odTF3Obyv9KptFTJ1vlpQSUuiK7gaNzH A==; X-CSE-ConnectionGUID: VOjDNsQISSKh2PH6t6ojaA== X-CSE-MsgGUID: dtSXfC3sTVa1xg9VZCQmhQ== X-IronPort-AV: E=McAfee;i="6700,10204,11431"; a="52735281" X-IronPort-AV: E=Sophos;i="6.15,284,1739865600"; d="scan'208";a="52735281" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2025 20:07:00 -0700 X-CSE-ConnectionGUID: VpcD5qYlSm2DiIDxaL8qww== X-CSE-MsgGUID: 3ZaxEgWET7GjIMwTrdIRpQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,284,1739865600"; d="scan'208";a="138522218" Received: from allen-box.sh.intel.com ([10.239.159.52]) by fmviesa009.fm.intel.com with ESMTP; 12 May 2025 20:06:59 -0700 From: Lu Baolu To: Joerg Roedel Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 3/5] iommu/vt-d: Replace spin_lock with mutex to protect domain ida Date: Tue, 13 May 2025 11:07:37 +0800 Message-ID: <20250513030739.2718555-4-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513030739.2718555-1-baolu.lu@linux.intel.com> References: <20250513030739.2718555-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The domain ID allocator is currently protected by a spin_lock. However, ida_alloc_range can potentially block if it needs to allocate memory to grow its internal structures. Replace the spin_lock with a mutex which allows sleep on block. Thus, the memory allocation flags can be updated from GFP_ATOMIC to GFP_KERNEL to allow blocking memory allocations if necessary. Introduce a new mutex, did_lock, specifically for protecting the domain ida. The existing spinlock will remain for protecting other intel_iommu fields. Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian Reviewed-by: Jason Gunthorpe Link: https://lore.kernel.org/r/20250430021135.2370244-3-baolu.lu@linux.int= el.com --- drivers/iommu/intel/dmar.c | 1 + drivers/iommu/intel/iommu.c | 12 ++++-------- drivers/iommu/intel/iommu.h | 2 ++ 3 files changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c index 0e35969c026b..9e17e8e56308 100644 --- a/drivers/iommu/intel/dmar.c +++ b/drivers/iommu/intel/dmar.c @@ -1101,6 +1101,7 @@ static int alloc_iommu(struct dmar_drhd_unit *drhd) iommu->node =3D NUMA_NO_NODE; spin_lock_init(&iommu->lock); ida_init(&iommu->domain_ida); + mutex_init(&iommu->did_lock); =20 ver =3D readl(iommu->reg + DMAR_VER_REG); pr_info("%s: reg_base_addr %llx ver %d:%d cap %llx ecap %llx\n", diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 0cac6b00adb0..8c405532ddbf 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -1345,17 +1345,16 @@ int domain_attach_iommu(struct dmar_domain *domain,= struct intel_iommu *iommu) if (!info) return -ENOMEM; =20 - spin_lock(&iommu->lock); + guard(mutex)(&iommu->did_lock); curr =3D xa_load(&domain->iommu_array, iommu->seq_id); if (curr) { curr->refcnt++; - spin_unlock(&iommu->lock); kfree(info); return 0; } =20 num =3D ida_alloc_range(&iommu->domain_ida, IDA_START_DID, - cap_ndoms(iommu->cap) - 1, GFP_ATOMIC); + cap_ndoms(iommu->cap) - 1, GFP_KERNEL); if (num < 0) { pr_err("%s: No free domain ids\n", iommu->name); goto err_unlock; @@ -1365,19 +1364,17 @@ int domain_attach_iommu(struct dmar_domain *domain,= struct intel_iommu *iommu) info->did =3D num; info->iommu =3D iommu; curr =3D xa_cmpxchg(&domain->iommu_array, iommu->seq_id, - NULL, info, GFP_ATOMIC); + NULL, info, GFP_KERNEL); if (curr) { ret =3D xa_err(curr) ? : -EBUSY; goto err_clear; } =20 - spin_unlock(&iommu->lock); return 0; =20 err_clear: ida_free(&iommu->domain_ida, info->did); err_unlock: - spin_unlock(&iommu->lock); kfree(info); return ret; } @@ -1389,7 +1386,7 @@ void domain_detach_iommu(struct dmar_domain *domain, = struct intel_iommu *iommu) if (domain->domain.type =3D=3D IOMMU_DOMAIN_SVA) return; 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X-CSE-ConnectionGUID: Rgx/9A+WTfWCEP2Mk9rQxQ== X-CSE-MsgGUID: UhtHfKCFSiqhGp98pXGiGQ== X-IronPort-AV: E=McAfee;i="6700,10204,11431"; a="52735284" X-IronPort-AV: E=Sophos;i="6.15,284,1739865600"; d="scan'208";a="52735284" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2025 20:07:01 -0700 X-CSE-ConnectionGUID: M/0IBQ0gRXODSBlz2H35Lg== X-CSE-MsgGUID: UNaDqK3bRbOLCbD8DKAYGQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,284,1739865600"; d="scan'208";a="138522221" Received: from allen-box.sh.intel.com ([10.239.159.52]) by fmviesa009.fm.intel.com with ESMTP; 12 May 2025 20:07:00 -0700 From: Lu Baolu To: Joerg Roedel Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 4/5] iommu/vt-d: Eliminate pci_physfn() in dmar_find_matched_satc_unit() Date: Tue, 13 May 2025 11:07:38 +0800 Message-ID: <20250513030739.2718555-5-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513030739.2718555-1-baolu.lu@linux.intel.com> References: <20250513030739.2718555-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Wei Wang The function dmar_find_matched_satc_unit() contains a duplicate call to pci_physfn(). This call is unnecessary as pci_physfn() has already been invoked by the caller. Removing the redundant call simplifies the code and improves efficiency a bit. Signed-off-by: Wei Wang Link: https://lore.kernel.org/r/20250509140021.4029303-2-wei.w.wang@intel.c= om Signed-off-by: Lu Baolu --- drivers/iommu/intel/iommu.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 8c405532ddbf..2258814ffc70 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -2686,7 +2686,6 @@ static struct dmar_satc_unit *dmar_find_matched_satc_= unit(struct pci_dev *dev) struct device *tmp; int i; =20 - dev =3D pci_physfn(dev); rcu_read_lock(); =20 list_for_each_entry_rcu(satcu, &dmar_satc_units, list) { --=20 2.43.0 From nobody Sun Feb 8 04:30:11 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 389111E376C for ; Tue, 13 May 2025 03:07:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747105624; cv=none; b=fcZtkhNRBuvUFFqb14YvVzwop+yQxv3BlEDAK46msKDfr8PxVJ6k2e/IPlnBDVz8GHQPV9jrDP1JcGfru8DZTy6zBXLlR9WCHW4HFLJ3arpvT1VffvVuJQa4C/sIRr8/gE+fBJ7LDiJ+8B5+7XZkgOyJH0ArAFgbKL7CHeX00aI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747105624; c=relaxed/simple; bh=GnPsA1x6WcR5RqgSCerE1Dq6vGOAihMYVqG+yIbsoLs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Jt+VwAOwSD2bi7CDeXodWkN29qRv9hYNFKqOWI43Ht2HHKIGdiIzj7YcWPSFj7elNpnvXzXfTkzdE95a8Ba+FkdMnuFh7aQAFzfwzOFe2qDmSZ3tM4jpH1Vd4GTdfuA+AfMgKmsk6YjWaiX5uhyRzHLa0DqoSPiY9Q6+ZOB5kDg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=HgomjRPJ; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="HgomjRPJ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1747105623; x=1778641623; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GnPsA1x6WcR5RqgSCerE1Dq6vGOAihMYVqG+yIbsoLs=; b=HgomjRPJh7lTArkLG6eClZm7LjVfrjaoqpEUuC1kaGfv0cYGbm+LQ7ji r0iAdser8UCkcP7Sg6rCP7JSq7SdkpKYXN38bPHAVALz56LncgoI0CA7P JQrweEqx4hwaTLJK+HOWuJNlw/cI0wonyNoPqgO//9wV5Z3vHZ6GwJrVc fL3Aq1lFzLv3I0YvnqR+N2KbVGd4XvPgJPJHV1ojW4tUlUD8UxVLXOrUY +qcbEQXcKn3D7m0fFK7oLpsWtqi9v9bA/IEFbbVLJH4UgcmeQxXaVNonf 0W4ULOj6Dw1z6igRhU2Hw0qLTUc5v3oMimyBKCQzifAHtd9u5zSAD3WU6 A==; X-CSE-ConnectionGUID: Jf/v8cUnSBedqaw9iZKqJQ== X-CSE-MsgGUID: DKJGFlw1R6KwvMB5/VwsMA== X-IronPort-AV: E=McAfee;i="6700,10204,11431"; a="52735289" X-IronPort-AV: E=Sophos;i="6.15,284,1739865600"; d="scan'208";a="52735289" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2025 20:07:02 -0700 X-CSE-ConnectionGUID: xugzxBpOTeqqt6Kr4BIn2A== X-CSE-MsgGUID: w93EyBDgScKO94TVoR6FUw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,284,1739865600"; d="scan'208";a="138522224" Received: from allen-box.sh.intel.com ([10.239.159.52]) by fmviesa009.fm.intel.com with ESMTP; 12 May 2025 20:07:01 -0700 From: Lu Baolu To: Joerg Roedel Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 5/5] iommu/vt-d: Change dmar_ats_supported() to return boolean Date: Tue, 13 May 2025 11:07:39 +0800 Message-ID: <20250513030739.2718555-6-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250513030739.2718555-1-baolu.lu@linux.intel.com> References: <20250513030739.2718555-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Wei Wang According to "Function return values and names" in coding-style.rst, the dmar_ats_supported() function should return a boolean instead of an integer. Also, rename "ret" to "supported" to be more straightforward. Signed-off-by: Wei Wang Reviewed-by: Yi Liu Link: https://lore.kernel.org/r/20250509140021.4029303-3-wei.w.wang@intel.c= om Signed-off-by: Lu Baolu --- drivers/iommu/intel/iommu.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 2258814ffc70..7f2d68103b3c 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -2702,15 +2702,16 @@ static struct dmar_satc_unit *dmar_find_matched_sat= c_unit(struct pci_dev *dev) return satcu; } =20 -static int dmar_ats_supported(struct pci_dev *dev, struct intel_iommu *iom= mu) +static bool dmar_ats_supported(struct pci_dev *dev, struct intel_iommu *io= mmu) { - int i, ret =3D 1; - struct pci_bus *bus; struct pci_dev *bridge =3D NULL; - struct device *tmp; - struct acpi_dmar_atsr *atsr; struct dmar_atsr_unit *atsru; struct dmar_satc_unit *satcu; + struct acpi_dmar_atsr *atsr; + bool supported =3D true; + struct pci_bus *bus; + struct device *tmp; + int i; =20 dev =3D pci_physfn(dev); satcu =3D dmar_find_matched_satc_unit(dev); @@ -2728,11 +2729,11 @@ static int dmar_ats_supported(struct pci_dev *dev, = struct intel_iommu *iommu) bridge =3D bus->self; /* If it's an integrated device, allow ATS */ if (!bridge) - return 1; + return true; /* Connected via non-PCIe: no ATS */ if (!pci_is_pcie(bridge) || pci_pcie_type(bridge) =3D=3D PCI_EXP_TYPE_PCI_BRIDGE) - return 0; + return false; /* If we found the root port, look it up in the ATSR */ if (pci_pcie_type(bridge) =3D=3D PCI_EXP_TYPE_ROOT_PORT) break; @@ -2751,11 +2752,11 @@ static int dmar_ats_supported(struct pci_dev *dev, = struct intel_iommu *iommu) if (atsru->include_all) goto out; } - ret =3D 0; + supported =3D false; out: rcu_read_unlock(); =20 - return ret; + return supported; } =20 int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info) --=20 2.43.0