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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-4fa22496e9fsm1740333173.11.2025.05.12.11.32.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 May 2025 11:32:22 -0700 (PDT) From: Alex Elder To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, dlan@gentoo.org Cc: heylenay@4d2.org, inochiama@outlook.com, guodong@riscstar.com, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, spacemit@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v9 5/6] reset: spacemit: define three more CCUs Date: Mon, 12 May 2025 13:32:10 -0500 Message-ID: <20250512183212.3465963-6-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250512183212.3465963-1-elder@riscstar.com> References: <20250512183212.3465963-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Three more CCUs on the SpacemiT K1 SoC implement only resets, not clocks. Define these resets so they can be used. Signed-off-by: Alex Elder Reviewed-by: Philipp Zabel --- drivers/clk/spacemit/ccu-k1.c | 24 +++++++++++++++ drivers/reset/reset-spacemit.c | 51 ++++++++++++++++++++++++++++++++ include/soc/spacemit/k1-syscon.h | 30 +++++++++++++++++++ 3 files changed, 105 insertions(+) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index 1c9ed434ae93e..f9e2200d1fd04 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -943,6 +943,18 @@ static const struct spacemit_ccu_data k1_ccu_apmu_data= =3D { .num =3D ARRAY_SIZE(k1_ccu_apmu_hws), }; =20 +static const struct spacemit_ccu_data k1_ccu_rcpu_data =3D { + .reset_name =3D "rcpu-reset", +}; + +static const struct spacemit_ccu_data k1_ccu_rcpu2_data =3D { + .reset_name =3D "rcpu2-reset", +}; + +static const struct spacemit_ccu_data k1_ccu_apbc2_data =3D { + .reset_name =3D "apbc2-reset", +}; + static int spacemit_ccu_register(struct device *dev, struct regmap *regmap, struct regmap *lock_regmap, @@ -1121,6 +1133,18 @@ static const struct of_device_id of_k1_ccu_match[] = =3D { .compatible =3D "spacemit,k1-syscon-apmu", .data =3D &k1_ccu_apmu_data, }, + { + .compatible =3D "spacemit,k1-syscon-rcpu", + .data =3D &k1_ccu_rcpu_data, + }, + { + .compatible =3D "spacemit,k1-syscon-rcpu2", + .data =3D &k1_ccu_rcpu2_data, + }, + { + .compatible =3D "spacemit,k1-syscon-apbc2", + .data =3D &k1_ccu_apbc2_data, + }, { } }; MODULE_DEVICE_TABLE(of, of_k1_ccu_match); diff --git a/drivers/reset/reset-spacemit.c b/drivers/reset/reset-spacemit.c index eff67bdc8adba..4137f4f8352d3 100644 --- a/drivers/reset/reset-spacemit.c +++ b/drivers/reset/reset-spacemit.c @@ -158,6 +158,54 @@ static const struct ccu_reset_controller_data k1_apmu_= reset_data =3D { .count =3D ARRAY_SIZE(k1_apmu_resets), }; =20 +static const struct ccu_reset_data k1_rcpu_resets[] =3D { + [RESET_RCPU_SSP0] =3D RESET_DATA(RCPU_SSP0_CLK_RST, 0, BIT(0)), + [RESET_RCPU_I2C0] =3D RESET_DATA(RCPU_I2C0_CLK_RST, 0, BIT(0)), + [RESET_RCPU_UART1] =3D RESET_DATA(RCPU_UART1_CLK_RST, 0, BIT(0)), + [RESET_RCPU_IR] =3D RESET_DATA(RCPU_CAN_CLK_RST, 0, BIT(0)), + [RESET_RCPU_CAN] =3D RESET_DATA(RCPU_IR_CLK_RST, 0, BIT(0)), + [RESET_RCPU_UART0] =3D RESET_DATA(RCPU_UART0_CLK_RST, 0, BIT(0)), + [RESET_RCPU_HDMI_AUDIO] =3D RESET_DATA(AUDIO_HDMI_CLK_CTRL, 0, BIT(0)), +}; + +static const struct ccu_reset_controller_data k1_rcpu_reset_data =3D { + .reset_data =3D k1_rcpu_resets, + .count =3D ARRAY_SIZE(k1_rcpu_resets), +}; + +static const struct ccu_reset_data k1_rcpu2_resets[] =3D { + [RESET_RCPU2_PWM0] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM1] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM2] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM3] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM4] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM5] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM6] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM7] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM8] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM9] =3D RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), +}; + +static const struct ccu_reset_controller_data k1_rcpu2_reset_data =3D { + .reset_data =3D k1_rcpu2_resets, + .count =3D ARRAY_SIZE(k1_rcpu2_resets), +}; + +static const struct ccu_reset_data k1_apbc2_resets[] =3D { + [RESET_APBC2_UART1] =3D RESET_DATA(APBC2_UART1_CLK_RST, BIT(2), 0), + [RESET_APBC2_SSP2] =3D RESET_DATA(APBC2_SSP2_CLK_RST, BIT(2), 0), + [RESET_APBC2_TWSI3] =3D RESET_DATA(APBC2_TWSI3_CLK_RST, BIT(2), 0), + [RESET_APBC2_RTC] =3D RESET_DATA(APBC2_RTC_CLK_RST, BIT(2), 0), + [RESET_APBC2_TIMERS0] =3D RESET_DATA(APBC2_TIMERS0_CLK_RST, BIT(2), 0), + [RESET_APBC2_KPC] =3D RESET_DATA(APBC2_KPC_CLK_RST, BIT(2), 0), + [RESET_APBC2_GPIO] =3D RESET_DATA(APBC2_GPIO_CLK_RST, BIT(2), 0), +}; + +static const struct ccu_reset_controller_data k1_apbc2_reset_data =3D { + .reset_data =3D k1_apbc2_resets, + .count =3D ARRAY_SIZE(k1_apbc2_resets), +}; + static int spacemit_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) { @@ -231,6 +279,9 @@ static const struct auxiliary_device_id spacemit_reset_= ids[] =3D { K1_AUX_DEV_ID(mpmu), K1_AUX_DEV_ID(apbc), K1_AUX_DEV_ID(apmu), + K1_AUX_DEV_ID(rcpu), + K1_AUX_DEV_ID(rcpu2), + K1_AUX_DEV_ID(apbc2), { }, }; MODULE_DEVICE_TABLE(auxiliary, spacemit_reset_ids); diff --git a/include/soc/spacemit/k1-syscon.h b/include/soc/spacemit/k1-sys= con.h index 53eff7691f33d..c59bd7a38e5b4 100644 --- a/include/soc/spacemit/k1-syscon.h +++ b/include/soc/spacemit/k1-syscon.h @@ -127,4 +127,34 @@ to_spacemit_ccu_adev(struct auxiliary_device *adev) #define APMU_EMAC0_CLK_RES_CTRL 0x3e4 #define APMU_EMAC1_CLK_RES_CTRL 0x3ec =20 +/* RCPU register offsets */ +#define RCPU_SSP0_CLK_RST 0x0028 +#define RCPU_I2C0_CLK_RST 0x0030 +#define RCPU_UART1_CLK_RST 0x003c +#define RCPU_CAN_CLK_RST 0x0048 +#define RCPU_IR_CLK_RST 0x004c +#define RCPU_UART0_CLK_RST 0x00d8 +#define AUDIO_HDMI_CLK_CTRL 0x2044 + +/* RCPU2 register offsets */ +#define RCPU2_PWM0_CLK_RST 0x0000 +#define RCPU2_PWM1_CLK_RST 0x0004 +#define RCPU2_PWM2_CLK_RST 0x0008 +#define RCPU2_PWM3_CLK_RST 0x000c +#define RCPU2_PWM4_CLK_RST 0x0010 +#define RCPU2_PWM5_CLK_RST 0x0014 +#define RCPU2_PWM6_CLK_RST 0x0018 +#define RCPU2_PWM7_CLK_RST 0x001c +#define RCPU2_PWM8_CLK_RST 0x0020 +#define RCPU2_PWM9_CLK_RST 0x0024 + +/* APBC2 register offsets */ +#define APBC2_UART1_CLK_RST 0x0000 +#define APBC2_SSP2_CLK_RST 0x0004 +#define APBC2_TWSI3_CLK_RST 0x0008 +#define APBC2_RTC_CLK_RST 0x000c +#define APBC2_TIMERS0_CLK_RST 0x0010 +#define APBC2_KPC_CLK_RST 0x0014 +#define APBC2_GPIO_CLK_RST 0x001c + #endif /* __SOC_K1_SYSCON_H__ */ --=20 2.45.2