From nobody Mon Feb 9 15:25:58 2026 Received: from mail-il1-f180.google.com (mail-il1-f180.google.com [209.85.166.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EED4B297A54 for ; Mon, 12 May 2025 18:32:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.166.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747074745; cv=none; b=sfAftPwq+79M2R2NYQmQvjQbVpRyqhmnXiAyGL4SwFI5E4hzhYFxlFtA/0WrkOo+JHlPrRm8bwnfYYB7nCQjyl1Z2HpTa1kImrq1LcX0Syt9SIN5F+g7YIVbpwc0AVDo2vJk0lr8oMmypLtmxsqL/FC3bVQMNl2JyxAhqcRm4fA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747074745; c=relaxed/simple; bh=mLs0fxNowr0COgkr82fEpqkOf+JG1y/e9MDEoWE3mQA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hB1pnqadmkruKx924huChVZtvfq5+2Azf1DGnKNoCdM2x9yTM4hqVHcMZQpZFaN4V/fPRJQD99Pa7zM7PQCY9BrFVMWVQppaBqC3Qj92DUfTj8ZQuGHzIrhvYnpabqVWAGljCKLoBjf04gbam8Xxw5Veb4V3DS0RM2lQenvKr4A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riscstar.com; spf=pass smtp.mailfrom=riscstar.com; dkim=pass (2048-bit key) header.d=riscstar-com.20230601.gappssmtp.com header.i=@riscstar-com.20230601.gappssmtp.com header.b=wT74+H+7; arc=none smtp.client-ip=209.85.166.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riscstar.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=riscstar.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=riscstar-com.20230601.gappssmtp.com header.i=@riscstar-com.20230601.gappssmtp.com header.b="wT74+H+7" Received: by mail-il1-f180.google.com with SMTP id e9e14a558f8ab-3d8e9f26b96so45463095ab.1 for ; Mon, 12 May 2025 11:32:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=riscstar-com.20230601.gappssmtp.com; s=20230601; t=1747074742; x=1747679542; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Hembn1ZHHPDkNP/mH4YRUnbmiUBes0gARU1fynTJWJs=; b=wT74+H+7A8If2LmyOV3LbCt7NTUdtII/HeQdavIGhnjxkbh9D8M0lsuHyq0OiCRRu5 YPyDPNW6W/SU2iuqQ4Dums3spb2cg1UC9DAilwmq/ranHHfhxvK4d+wohMmChBiOZJLt 5EHtEZNse30qb56kLI+bNXV2qoTUrP4bBJTJk0IGrH+iuqYVqsc+zti+ZnCMUo7gdi/K Ytqkc49f+jPybKN6PkraGjEIQFtphIELziEgAFjbKerYR0hAVxhs3d0OvlJqZQTT7k8Z NvJIQhoHMnoccbMYd3tC1XDZ4Uc8SOYRYUdh28ir6vngYqR9B9KBYj6Uj82ivrmvGC6D gn3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747074742; x=1747679542; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hembn1ZHHPDkNP/mH4YRUnbmiUBes0gARU1fynTJWJs=; b=ImzwynvuqzQJz4EmMYgYw6w+tGZrcTtxZKi0iNBYWRY54fzwihfmq35uWKRWljH2vR ZWeyZDLF4NPXr/QaK4wM4YhsRBRdCpW+gYrDL2kR1rgODoR0WE4LXxNYnwj1thvM7zeS q7DM1Z4Wx7QBya1KTXrNVQObFf7U0Vk8G1Z9lORlWB4HtlT8yA9nBbb8h4XLkL1cfOH8 dp/vnRfbNO5734OBLVdnaMJ/YsAA3JAirdsCZ1B5yk5t1pnUc5ayLwvX8PFp8oVlC0IF /eBaS5Zr1K7WaGpoyS1oPy+amrB1CZbKXZHLWBUJe/Fj7XVmyQv/dAfmz1u7PqlEiGI3 BxPA== X-Forwarded-Encrypted: i=1; AJvYcCVI/Mpl14P2kXRVscizoqUC6vpiAGTv7zwKfsV9J37MFSsWdR8njaPmvE3IGxL592e4NJPRq2aD0+FFmwM=@vger.kernel.org X-Gm-Message-State: AOJu0YyqnofQZy8n4KTMPTMSvLde4zv9sxrkHCizaNSkUF+F3U+mpWgJ EwfInvDf9EtlCqFLub+VLlxhLoJOuvW8EQ90g+2ECIQCHDZRwg14m82Wk7mBsVE= X-Gm-Gg: ASbGncvaVqt4XiKOjUTQOnidgaAEOyyx6vfrQNq1+RumieTb38cCn6DMQWLiI3zbAip e81ns/OdFG8fIaDvXHq+kD7bWcMnIFPFkqTZT8Ct+8dp1Xki+I3eKsFtVyTlowVrpCooPzRQ+mW 70ZnDzdwzfXWMuHW/XIriYJiTdDkXaCRjoYgd0dO0KvKikjGTBsRG4gy4gM7zEy/mJFlB/aqR3s 6hotZFACJNWwmxfMkcCkFujA1OpKE8dpMbbDUbarwTL8bIkRnIvyjmcmboPLzBwcYk9zc6pmvY6 4QaAsoUgEyAdGZZdIv+CISdkZa3FEwxShj4ZDisQAIM/ysJc6DZ+2h4TF70+eloG2W8SB2cM3lW 3Mby3ikzJzFxMVs4h3dk6Xt6b X-Google-Smtp-Source: AGHT+IHQDjNO9OkW9DD+zDdHjn8UmnS7urWAyq8k+vW5sHj7pJyrWvCR3rBMBczzchiDerVf0q080w== X-Received: by 2002:a05:6e02:1544:b0:3da:7cbe:f47b with SMTP id e9e14a558f8ab-3da7e211dd9mr180142515ab.21.1747074741903; Mon, 12 May 2025 11:32:21 -0700 (PDT) Received: from localhost.localdomain (c-73-228-159-35.hsd1.mn.comcast.net. [73.228.159.35]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-4fa22496e9fsm1740333173.11.2025.05.12.11.32.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 May 2025 11:32:21 -0700 (PDT) From: Alex Elder To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, dlan@gentoo.org Cc: heylenay@4d2.org, inochiama@outlook.com, guodong@riscstar.com, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, spacemit@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v9 4/6] reset: spacemit: add support for SpacemiT CCU resets Date: Mon, 12 May 2025 13:32:09 -0500 Message-ID: <20250512183212.3465963-5-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250512183212.3465963-1-elder@riscstar.com> References: <20250512183212.3465963-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Implement reset support for SpacemiT CCUs. A SpacemiT reset controller device is an auxiliary device associated with a clock controller (CCU). This initial patch defines the reset controllers for the MPMU, APBC, and MPMU CCUs, which already define clock controllers. Signed-off-by: Alex Elder Reviewed-by: Philipp Zabel --- drivers/reset/Kconfig | 9 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-spacemit.c | 246 +++++++++++++++++++++++++++++++++ 3 files changed, 256 insertions(+) create mode 100644 drivers/reset/reset-spacemit.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 99f6f9784e686..28fa84ea4dbcc 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -263,6 +263,15 @@ config RESET_SOCFPGA This enables the reset driver for the SoCFPGA ARMv7 platforms. This driver gets initialized early during platform init calls. =20 +config RESET_SPACEMIT + tristate "SpacemiT reset driver" + depends on ARCH_SPACEMIT || COMPILE_TEST + select AUXILIARY_BUS + default ARCH_SPACEMIT + help + This enables the reset controller driver for SpacemiT SoCs, + including the K1. + config RESET_SUNPLUS bool "Sunplus SoCs Reset Driver" if COMPILE_TEST default ARCH_SUNPLUS diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 31f9904d13f9c..84f90abf96846 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_RESET_RASPBERRYPI) +=3D reset-raspberrypi.o obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) +=3D reset-rzg2l-usbphy-ctrl.o obj-$(CONFIG_RESET_SCMI) +=3D reset-scmi.o obj-$(CONFIG_RESET_SIMPLE) +=3D reset-simple.o +obj-$(CONFIG_RESET_SPACEMIT) +=3D reset-spacemit.o obj-$(CONFIG_RESET_SOCFPGA) +=3D reset-socfpga.o obj-$(CONFIG_RESET_SUNPLUS) +=3D reset-sunplus.o obj-$(CONFIG_RESET_SUNXI) +=3D reset-sunxi.o diff --git a/drivers/reset/reset-spacemit.c b/drivers/reset/reset-spacemit.c new file mode 100644 index 0000000000000..eff67bdc8adba --- /dev/null +++ b/drivers/reset/reset-spacemit.c @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/* SpacemiT reset controller driver */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +struct ccu_reset_data { + u32 offset; + u32 assert_mask; + u32 deassert_mask; +}; + +struct ccu_reset_controller_data { + const struct ccu_reset_data *reset_data; /* array */ + size_t count; +}; + +struct ccu_reset_controller { + struct reset_controller_dev rcdev; + const struct ccu_reset_controller_data *data; + struct regmap *regmap; +}; + +#define RESET_DATA(_offset, _assert_mask, _deassert_mask) \ + { \ + .offset =3D (_offset), \ + .assert_mask =3D (_assert_mask), \ + .deassert_mask =3D (_deassert_mask), \ + } + +static const struct ccu_reset_data k1_mpmu_resets[] =3D { + [RESET_WDT] =3D RESET_DATA(MPMU_WDTPCR, BIT(2), 0), +}; + +static const struct ccu_reset_controller_data k1_mpmu_reset_data =3D { + .reset_data =3D k1_mpmu_resets, + .count =3D ARRAY_SIZE(k1_mpmu_resets), +}; + +static const struct ccu_reset_data k1_apbc_resets[] =3D { + [RESET_UART0] =3D RESET_DATA(APBC_UART1_CLK_RST, BIT(2), 0), + [RESET_UART2] =3D RESET_DATA(APBC_UART2_CLK_RST, BIT(2), 0), + [RESET_GPIO] =3D RESET_DATA(APBC_GPIO_CLK_RST, BIT(2), 0), + [RESET_PWM0] =3D RESET_DATA(APBC_PWM0_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM1] =3D RESET_DATA(APBC_PWM1_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM2] =3D RESET_DATA(APBC_PWM2_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM3] =3D RESET_DATA(APBC_PWM3_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM4] =3D RESET_DATA(APBC_PWM4_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM5] =3D RESET_DATA(APBC_PWM5_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM6] =3D RESET_DATA(APBC_PWM6_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM7] =3D RESET_DATA(APBC_PWM7_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM8] =3D RESET_DATA(APBC_PWM8_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM9] =3D RESET_DATA(APBC_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM10] =3D RESET_DATA(APBC_PWM10_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM11] =3D RESET_DATA(APBC_PWM11_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM12] =3D RESET_DATA(APBC_PWM12_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM13] =3D RESET_DATA(APBC_PWM13_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM14] =3D RESET_DATA(APBC_PWM14_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM15] =3D RESET_DATA(APBC_PWM15_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM16] =3D RESET_DATA(APBC_PWM16_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM17] =3D RESET_DATA(APBC_PWM17_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM18] =3D RESET_DATA(APBC_PWM18_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM19] =3D RESET_DATA(APBC_PWM19_CLK_RST, BIT(2), BIT(0)), + [RESET_SSP3] =3D RESET_DATA(APBC_SSP3_CLK_RST, BIT(2), 0), + [RESET_UART3] =3D RESET_DATA(APBC_UART3_CLK_RST, BIT(2), 0), + [RESET_RTC] =3D RESET_DATA(APBC_RTC_CLK_RST, BIT(2), 0), + [RESET_TWSI0] =3D RESET_DATA(APBC_TWSI0_CLK_RST, BIT(2), 0), + [RESET_TIMERS1] =3D RESET_DATA(APBC_TIMERS1_CLK_RST, BIT(2), 0), + [RESET_AIB] =3D RESET_DATA(APBC_AIB_CLK_RST, BIT(2), 0), + [RESET_TIMERS2] =3D RESET_DATA(APBC_TIMERS2_CLK_RST, BIT(2), 0), + [RESET_ONEWIRE] =3D RESET_DATA(APBC_ONEWIRE_CLK_RST, BIT(2), 0), + [RESET_SSPA0] =3D RESET_DATA(APBC_SSPA0_CLK_RST, BIT(2), 0), + [RESET_SSPA1] =3D RESET_DATA(APBC_SSPA1_CLK_RST, BIT(2), 0), + [RESET_DRO] =3D RESET_DATA(APBC_DRO_CLK_RST, BIT(2), 0), + [RESET_IR] =3D RESET_DATA(APBC_IR_CLK_RST, BIT(2), 0), + [RESET_TWSI1] =3D RESET_DATA(APBC_TWSI1_CLK_RST, BIT(2), 0), + [RESET_TSEN] =3D RESET_DATA(APBC_TSEN_CLK_RST, BIT(2), 0), + [RESET_TWSI2] =3D RESET_DATA(APBC_TWSI2_CLK_RST, BIT(2), 0), + [RESET_TWSI4] =3D RESET_DATA(APBC_TWSI4_CLK_RST, BIT(2), 0), + [RESET_TWSI5] =3D RESET_DATA(APBC_TWSI5_CLK_RST, BIT(2), 0), + [RESET_TWSI6] =3D RESET_DATA(APBC_TWSI6_CLK_RST, BIT(2), 0), + [RESET_TWSI7] =3D RESET_DATA(APBC_TWSI7_CLK_RST, BIT(2), 0), + [RESET_TWSI8] =3D RESET_DATA(APBC_TWSI8_CLK_RST, BIT(2), 0), + [RESET_IPC_AP2AUD] =3D RESET_DATA(APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0), + [RESET_UART4] =3D RESET_DATA(APBC_UART4_CLK_RST, BIT(2), 0), + [RESET_UART5] =3D RESET_DATA(APBC_UART5_CLK_RST, BIT(2), 0), + [RESET_UART6] =3D RESET_DATA(APBC_UART6_CLK_RST, BIT(2), 0), + [RESET_UART7] =3D RESET_DATA(APBC_UART7_CLK_RST, BIT(2), 0), + [RESET_UART8] =3D RESET_DATA(APBC_UART8_CLK_RST, BIT(2), 0), + [RESET_UART9] =3D RESET_DATA(APBC_UART9_CLK_RST, BIT(2), 0), + [RESET_CAN0] =3D RESET_DATA(APBC_CAN0_CLK_RST, BIT(2), 0), +}; + +static const struct ccu_reset_controller_data k1_apbc_reset_data =3D { + .reset_data =3D k1_apbc_resets, + .count =3D ARRAY_SIZE(k1_apbc_resets), +}; + +static const struct ccu_reset_data k1_apmu_resets[] =3D { + [RESET_CCIC_4X] =3D RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(1)), + [RESET_CCIC1_PHY] =3D RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(2)), + [RESET_SDH_AXI] =3D RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(0)), + [RESET_SDH0] =3D RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)), + [RESET_SDH1] =3D RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)), + [RESET_SDH2] =3D RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)), + [RESET_USBP1_AXI] =3D RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(4)), + [RESET_USB_AXI] =3D RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(0)), + [RESET_USB3_0] =3D RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, + BIT(11) | BIT(10) | BIT(9)), + [RESET_QSPI] =3D RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)), + [RESET_QSPI_BUS] =3D RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)), + [RESET_DMA] =3D RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)), + [RESET_AES] =3D RESET_DATA(APMU_AES_CLK_RES_CTRL, 0, BIT(4)), + [RESET_VPU] =3D RESET_DATA(APMU_VPU_CLK_RES_CTRL, 0, BIT(0)), + [RESET_GPU] =3D RESET_DATA(APMU_GPU_CLK_RES_CTRL, 0, BIT(1)), + [RESET_EMMC] =3D RESET_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(1)), + [RESET_EMMC_X] =3D RESET_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(0)), + [RESET_AUDIO] =3D RESET_DATA(APMU_AUDIO_CLK_RES_CTRL, 0, + BIT(3) | BIT(2) | BIT(0)), + [RESET_HDMI] =3D RESET_DATA(APMU_HDMI_CLK_RES_CTRL, 0, BIT(9)), + [RESET_PCIE0] =3D RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, BIT(8), + BIT(5) | BIT(4) | BIT(3)), + [RESET_PCIE1] =3D RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, BIT(8), + BIT(5) | BIT(4) | BIT(3)), + [RESET_PCIE2] =3D RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, BIT(8), + BIT(5) | BIT(4) | BIT(3)), + [RESET_EMAC0] =3D RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)), + [RESET_EMAC1] =3D RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)), + [RESET_JPG] =3D RESET_DATA(APMU_JPG_CLK_RES_CTRL, 0, BIT(0)), + [RESET_CCIC2PHY] =3D RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(2)), + [RESET_CCIC3PHY] =3D RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(29)), + [RESET_CSI] =3D RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(1)), + [RESET_ISP] =3D RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(0)), + [RESET_ISP_CPP] =3D RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(27)), + [RESET_ISP_BUS] =3D RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(3)), + [RESET_ISP_CI] =3D RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(16)), + [RESET_DPU_MCLK] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(9)), + [RESET_DPU_ESC] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(3)), + [RESET_DPU_HCLK] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(4)), + [RESET_DPU_SPIBUS] =3D RESET_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(4)), + [RESET_DPU_SPI_HBUS] =3D RESET_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(2)), + [RESET_V2D] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(27)), + [RESET_MIPI] =3D RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(15)), + [RESET_MC] =3D RESET_DATA(APMU_PMUA_MC_CTRL, 0, BIT(0)), +}; + +static const struct ccu_reset_controller_data k1_apmu_reset_data =3D { + .reset_data =3D k1_apmu_resets, + .count =3D ARRAY_SIZE(k1_apmu_resets), +}; + +static int spacemit_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct ccu_reset_controller *controller; + const struct ccu_reset_data *data; + u32 mask; + u32 val; + + controller =3D container_of(rcdev, struct ccu_reset_controller, rcdev); + data =3D &controller->data->reset_data[id]; + mask =3D data->assert_mask | data->deassert_mask; + val =3D assert ? data->assert_mask : data->deassert_mask; + + return regmap_update_bits(controller->regmap, data->offset, mask, val); +} + +static int spacemit_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return spacemit_reset_update(rcdev, id, true); +} + +static int spacemit_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return spacemit_reset_update(rcdev, id, false); +} + +static const struct reset_control_ops spacemit_reset_control_ops =3D { + .assert =3D spacemit_reset_assert, + .deassert =3D spacemit_reset_deassert, +}; + +static int spacemit_reset_controller_register(struct device *dev, + struct ccu_reset_controller *controller) +{ + struct reset_controller_dev *rcdev =3D &controller->rcdev; + + rcdev->ops =3D &spacemit_reset_control_ops; + rcdev->owner =3D THIS_MODULE; + rcdev->of_node =3D dev->of_node; + rcdev->nr_resets =3D controller->data->count; + + return devm_reset_controller_register(dev, &controller->rcdev); +} + +static int spacemit_reset_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct spacemit_ccu_adev *rdev =3D to_spacemit_ccu_adev(adev); + const void *data =3D (void *)id->driver_data; + struct ccu_reset_controller *controller; + struct device *dev =3D &adev->dev; + + controller =3D devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL); + if (!controller) + return -ENOMEM; + controller->data =3D data; + controller->regmap =3D rdev->regmap; + + return spacemit_reset_controller_register(dev, controller); +} + +#define K1_AUX_DEV_ID(_unit) \ + { \ + .name =3D "spacemit_ccu_k1." #_unit "-reset", \ + .driver_data =3D (kernel_ulong_t)&k1_ ## _unit ## _reset_data, \ + } + +static const struct auxiliary_device_id spacemit_reset_ids[] =3D { + K1_AUX_DEV_ID(mpmu), + K1_AUX_DEV_ID(apbc), + K1_AUX_DEV_ID(apmu), + { }, +}; +MODULE_DEVICE_TABLE(auxiliary, spacemit_reset_ids); + +static struct auxiliary_driver spacemit_k1_reset_driver =3D { + .probe =3D spacemit_reset_probe, + .id_table =3D spacemit_reset_ids, +}; +module_auxiliary_driver(spacemit_k1_reset_driver); + +MODULE_AUTHOR("Alex Elder "); +MODULE_DESCRIPTION("SpacemiT reset controller driver"); +MODULE_LICENSE("GPL"); --=20 2.45.2