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Mon, 12 May 2025 11:23:52 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Biju Das , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , Laurent Pinchart , dri-devel@lists.freedesktop.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v5 05/12] drm: renesas: rz-du: mipi_dsi: Use VCLK for HSFREQ calculation Date: Mon, 12 May 2025 19:23:23 +0100 Message-ID: <20250512182330.238259-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250512182330.238259-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250512182330.238259-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Update the RZ/G2L MIPI DSI driver to calculate HSFREQ using the actual VCLK rate instead of the mode clock. The relationship between HSCLK and VCLK is: vclk * bpp <=3D hsclk * 8 * lanes Retrieve the VCLK rate using `clk_get_rate(dsi->vclk)`, ensuring that HSFREQ accurately reflects the clock rate set in hardware, leading to better precision in data transmission. Additionally, use `DIV_ROUND_CLOSEST_ULL` for a more precise division when computing `hsfreq`. Also, update unit conversions to use correct scaling factors for better clarity and correctness. Since `clk_get_rate()` returns the clock rate in Hz, update the HSFREQ threshold comparisons to use Hz instead of kHz to ensure correct behavior. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das --- v4->v5: - Added dev_info() to print the VCLK rate if it doesn't match the requested rate. - Added Reviewed-by tag from Biju v3->v4: - Used MILLI instead of KILO v2->v3: - No changes v1->v2: - No changes --- .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 30 +++++++++++-------- 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/d= rm/renesas/rz-du/rzg2l_mipi_dsi.c index c5f698cd74f1..3f6988303e63 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -15,6 +16,7 @@ #include #include #include +#include =20 #include #include @@ -199,7 +201,7 @@ static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_d= si *dsi, /* All DSI global operation timings are set with recommended setting */ for (i =3D 0; i < ARRAY_SIZE(rzg2l_mipi_dsi_global_timings); ++i) { dphy_timings =3D &rzg2l_mipi_dsi_global_timings[i]; - if (hsfreq <=3D dphy_timings->hsfreq_max) + if (hsfreq <=3D (dphy_timings->hsfreq_max * MILLI)) break; } =20 @@ -258,7 +260,7 @@ static void rzg2l_mipi_dsi_dphy_exit(struct rzg2l_mipi_= dsi *dsi) static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, const struct drm_display_mode *mode) { - unsigned long hsfreq; + unsigned long hsfreq, vclk_rate; unsigned int bpp; u32 txsetr; u32 clstptsetr; @@ -269,6 +271,12 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_ds= i *dsi, u32 golpbkt; int ret; =20 + ret =3D pm_runtime_resume_and_get(dsi->dev); + if (ret < 0) + return ret; + + clk_set_rate(dsi->vclk, mode->clock * MILLI); + /* * Relationship between hsclk and vclk must follow * vclk * bpp =3D hsclk * 8 * lanes @@ -280,13 +288,11 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_d= si *dsi, * hsclk(bit) =3D hsclk(byte) * 8 =3D hsfreq */ bpp =3D mipi_dsi_pixel_format_to_bpp(dsi->format); - hsfreq =3D (mode->clock * bpp) / dsi->lanes; - - ret =3D pm_runtime_resume_and_get(dsi->dev); - if (ret < 0) - return ret; - - clk_set_rate(dsi->vclk, mode->clock * 1000); + vclk_rate =3D clk_get_rate(dsi->vclk); + if (vclk_rate !=3D mode->clock * MILLI) + dev_info(dsi->dev, "Requested vclk rate %lu, actual %lu mismatch\n", + mode->clock * MILLI, vclk_rate); + hsfreq =3D DIV_ROUND_CLOSEST_ULL(vclk_rate * bpp, dsi->lanes); =20 ret =3D rzg2l_mipi_dsi_dphy_init(dsi, hsfreq); if (ret < 0) @@ -304,12 +310,12 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_d= si *dsi, * - data lanes: maximum 4 lanes * Therefore maximum hsclk will be 891 Mbps. */ - if (hsfreq > 445500) { + if (hsfreq > 445500000) { clkkpt =3D 12; clkbfht =3D 15; clkstpt =3D 48; golpbkt =3D 75; - } else if (hsfreq > 250000) { + } else if (hsfreq > 250000000) { clkkpt =3D 7; clkbfht =3D 8; clkstpt =3D 27; @@ -753,7 +759,7 @@ static int rzg2l_mipi_dsi_probe(struct platform_device = *pdev) * mode->clock and format are not available. So initialize DPHY with * timing parameters for 80Mbps. */ - ret =3D rzg2l_mipi_dsi_dphy_init(dsi, 80000); + ret =3D rzg2l_mipi_dsi_dphy_init(dsi, 80000000); if (ret < 0) goto err_phy; =20 --=20 2.49.0