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Mon, 12 May 2025 11:23:46 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Biju Das , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , Laurent Pinchart , dri-devel@lists.freedesktop.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar , Krzysztof Kozlowski Subject: [PATCH v5 01/12] dt-bindings: display: renesas,rzg2l-du: Add support for RZ/V2H(P) SoC Date: Mon, 12 May 2025 19:23:19 +0100 Message-ID: <20250512182330.238259-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250512182330.238259-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250512182330.238259-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar The DU block on the RZ/V2H(P) SoC is identical to the one found on the RZ/G2L SoC. However, it only supports the DSI interface, whereas the RZ/G2L supports both DSI and DPI interfaces. Due to this difference, a SoC-specific compatible string 'renesas,r9a09g057-du' is added for the RZ/V2H(P) SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Krzysztof Kozlowski Reviewed-by: Biju Das Reviewed-by: Laurent Pinchart --- v4->v5: - Added reviewed tag from Biju v3->v4: - No changes v2->v3: - Collected reviewed tag from Krzysztof v1->v2: - Kept the sort order for schema validation - Added `port@1: false` for RZ/V2H(P) SoC --- .../bindings/display/renesas,rzg2l-du.yaml | 23 ++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yam= l b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml index 95e3d5e74b87..1e32d14b6edb 100644 --- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml @@ -20,6 +20,7 @@ properties: - enum: - renesas,r9a07g043u-du # RZ/G2UL - renesas,r9a07g044-du # RZ/G2{L,LC} + - renesas,r9a09g057-du # RZ/V2H(P) - items: - enum: - renesas,r9a07g054-du # RZ/V2L @@ -101,7 +102,12 @@ allOf: =20 required: - port@0 - else: + - if: + properties: + compatible: + contains: + const: renesas,r9a07g044-du + then: properties: ports: properties: @@ -113,6 +119,21 @@ allOf: required: - port@0 - port@1 + - if: + properties: + compatible: + contains: + const: renesas,r9a09g057-du + then: + properties: + ports: + properties: + port@0: + description: DSI + port@1: false + + required: + - port@0 =20 examples: # RZ/G2L DU --=20 2.49.0 From nobody Mon Feb 9 19:11:08 2026 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABC53296FB8; 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Mon, 12 May 2025 11:23:48 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:581b:951a:bc46:a124]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f5a4c5f6sm13175497f8f.86.2025.05.12.11.23.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 May 2025 11:23:47 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Biju Das , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , Laurent Pinchart , dri-devel@lists.freedesktop.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v5 02/12] drm: renesas: rz-du: Add support for RZ/V2H(P) SoC Date: Mon, 12 May 2025 19:23:20 +0100 Message-ID: <20250512182330.238259-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250512182330.238259-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250512182330.238259-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar The LCD controller (LCDC) on the RZ/V2H(P) SoC is composed of Frame Compression Processor (FCPVD), Video Signal Processor (VSPD), and Display Unit (DU). There is one LCDC unit available on the RZ/V2H(P) SoC which is connected to the DSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Reviewed-by: Laurent Pinchart --- v4->v5: - Added reviewed tag from Biju v3->v4: - No changes v2->v3: - No changes v1->v2: - No changes --- drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c b/drivers/gpu/drm= /renesas/rz-du/rzg2l_du_drv.c index 5e40f0c1e7b0..e1aa6a719529 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c @@ -50,9 +50,20 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07g= 044_info =3D { } }; =20 +static const struct rzg2l_du_device_info rzg2l_du_r9a09g057_info =3D { + .channels_mask =3D BIT(0), + .routes =3D { + [RZG2L_DU_OUTPUT_DSI0] =3D { + .possible_outputs =3D BIT(0), + .port =3D 0, + }, + }, +}; + static const struct of_device_id rzg2l_du_of_table[] =3D { { .compatible =3D "renesas,r9a07g043u-du", .data =3D &rzg2l_du_r9a07g043u= _info }, { .compatible =3D "renesas,r9a07g044-du", .data =3D &rzg2l_du_r9a07g044_i= nfo }, + { .compatible =3D "renesas,r9a09g057-du", .data =3D &rzg2l_du_r9a09g057_i= nfo }, { /* sentinel */ } }; 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Mon, 12 May 2025 11:23:49 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Biju Das , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , Laurent Pinchart , dri-devel@lists.freedesktop.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v5 03/12] drm: renesas: rz-du: mipi_dsi: Add min check for VCLK range Date: Mon, 12 May 2025 19:23:21 +0100 Message-ID: <20250512182330.238259-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250512182330.238259-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250512182330.238259-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar The VCLK range for Renesas RZ/G2L SoC is 148.5 MHz to 5.803 MHz. Add a minimum clock check in the mode_valid callback to ensure that the clock value does not fall below the valid range. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Reviewed-by: Laurent Pinchart --- v4->v5: - No changes v3->v4: - No changes v2->v3: - No changes v1->v2: - Added reviewed tag from Biju=20 --- drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/d= rm/renesas/rz-du/rzg2l_mipi_dsi.c index 4550c6d84796..ec8baecb9ba5 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -584,6 +584,9 @@ rzg2l_mipi_dsi_bridge_mode_valid(struct drm_bridge *bri= dge, if (mode->clock > 148500) return MODE_CLOCK_HIGH; =20 + if (mode->clock < 5803) + return MODE_CLOCK_LOW; + return MODE_OK; } =20 --=20 2.49.0 From nobody Mon Feb 9 19:11:08 2026 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 852912980AF; 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charset="utf-8" From: Lad Prabhakar Simplify the high-speed clock frequency (HSFREQ) calculation by removing the redundant multiplication and division by 8. The updated equation: hsfreq =3D (mode->clock * bpp) / (dsi->lanes); produces the same result while improving readability and clarity. Additionally, update the comment to clarify the relationship between HS clock bit frequency, HS byte clock frequency, and HSFREQ. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Reviewed-by: Laurent Pinchart --- v4->v5: - No changes v3->v4: - No changes v2->v3: - No changes v1->v2: - Added Reviewed-by tag from Biju --- drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/d= rm/renesas/rz-du/rzg2l_mipi_dsi.c index ec8baecb9ba5..c5f698cd74f1 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -277,10 +277,10 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_d= si *dsi, * hsclk: DSI HS Byte clock frequency (Hz) * lanes: number of data lanes * - * hsclk(bit) =3D hsclk(byte) * 8 + * hsclk(bit) =3D hsclk(byte) * 8 =3D hsfreq */ bpp =3D mipi_dsi_pixel_format_to_bpp(dsi->format); - hsfreq =3D (mode->clock * bpp * 8) / (8 * dsi->lanes); + hsfreq =3D (mode->clock * bpp) / dsi->lanes; =20 ret =3D pm_runtime_resume_and_get(dsi->dev); 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Mon, 12 May 2025 11:23:52 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Biju Das , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , Laurent Pinchart , dri-devel@lists.freedesktop.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v5 05/12] drm: renesas: rz-du: mipi_dsi: Use VCLK for HSFREQ calculation Date: Mon, 12 May 2025 19:23:23 +0100 Message-ID: <20250512182330.238259-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250512182330.238259-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250512182330.238259-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Update the RZ/G2L MIPI DSI driver to calculate HSFREQ using the actual VCLK rate instead of the mode clock. The relationship between HSCLK and VCLK is: vclk * bpp <=3D hsclk * 8 * lanes Retrieve the VCLK rate using `clk_get_rate(dsi->vclk)`, ensuring that HSFREQ accurately reflects the clock rate set in hardware, leading to better precision in data transmission. Additionally, use `DIV_ROUND_CLOSEST_ULL` for a more precise division when computing `hsfreq`. Also, update unit conversions to use correct scaling factors for better clarity and correctness. Since `clk_get_rate()` returns the clock rate in Hz, update the HSFREQ threshold comparisons to use Hz instead of kHz to ensure correct behavior. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das --- v4->v5: - Added dev_info() to print the VCLK rate if it doesn't match the requested rate. - Added Reviewed-by tag from Biju v3->v4: - Used MILLI instead of KILO v2->v3: - No changes v1->v2: - No changes --- .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 30 +++++++++++-------- 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/d= rm/renesas/rz-du/rzg2l_mipi_dsi.c index c5f698cd74f1..3f6988303e63 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -15,6 +16,7 @@ #include #include #include +#include =20 #include #include @@ -199,7 +201,7 @@ static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_d= si *dsi, /* All DSI global operation timings are set with recommended setting */ for (i =3D 0; i < ARRAY_SIZE(rzg2l_mipi_dsi_global_timings); ++i) { dphy_timings =3D &rzg2l_mipi_dsi_global_timings[i]; - if (hsfreq <=3D dphy_timings->hsfreq_max) + if (hsfreq <=3D (dphy_timings->hsfreq_max * MILLI)) break; } =20 @@ -258,7 +260,7 @@ static void rzg2l_mipi_dsi_dphy_exit(struct rzg2l_mipi_= dsi *dsi) static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, const struct drm_display_mode *mode) { - unsigned long hsfreq; + unsigned long hsfreq, vclk_rate; unsigned int bpp; u32 txsetr; u32 clstptsetr; @@ -269,6 +271,12 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_ds= i *dsi, u32 golpbkt; int ret; =20 + ret =3D pm_runtime_resume_and_get(dsi->dev); + if (ret < 0) + return ret; + + clk_set_rate(dsi->vclk, mode->clock * MILLI); + /* * Relationship between hsclk and vclk must follow * vclk * bpp =3D hsclk * 8 * lanes @@ -280,13 +288,11 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_d= si *dsi, * hsclk(bit) =3D hsclk(byte) * 8 =3D hsfreq */ bpp =3D mipi_dsi_pixel_format_to_bpp(dsi->format); - hsfreq =3D (mode->clock * bpp) / dsi->lanes; - - ret =3D pm_runtime_resume_and_get(dsi->dev); - if (ret < 0) - return ret; - - clk_set_rate(dsi->vclk, mode->clock * 1000); + vclk_rate =3D clk_get_rate(dsi->vclk); + if (vclk_rate !=3D mode->clock * MILLI) + dev_info(dsi->dev, "Requested vclk rate %lu, actual %lu mismatch\n", + mode->clock * MILLI, vclk_rate); + hsfreq =3D DIV_ROUND_CLOSEST_ULL(vclk_rate * bpp, dsi->lanes); =20 ret =3D rzg2l_mipi_dsi_dphy_init(dsi, hsfreq); if (ret < 0) @@ -304,12 +310,12 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_d= si *dsi, * - data lanes: maximum 4 lanes * Therefore maximum hsclk will be 891 Mbps. */ - if (hsfreq > 445500) { + if (hsfreq > 445500000) { clkkpt =3D 12; clkbfht =3D 15; clkstpt =3D 48; golpbkt =3D 75; - } else if (hsfreq > 250000) { + } else if (hsfreq > 250000000) { clkkpt =3D 7; clkbfht =3D 8; clkstpt =3D 27; @@ -753,7 +759,7 @@ static int rzg2l_mipi_dsi_probe(struct platform_device = *pdev) * mode->clock and format are not available. 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Mon, 12 May 2025 11:23:53 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Biju Das , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , Laurent Pinchart , dri-devel@lists.freedesktop.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v5 06/12] drm: renesas: rz-du: mipi_dsi: Add OF data support Date: Mon, 12 May 2025 19:23:24 +0100 Message-ID: <20250512182330.238259-7-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250512182330.238259-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250512182330.238259-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar In preparation for adding support for the Renesas RZ/V2H(P) SoC, this patch introduces a mechanism to pass SoC-specific information via OF data in the DSI driver. This enables the driver to adapt dynamically to various SoC-specific requirements without hardcoding configurations. The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical to the one on the RZ/G2L SoC. While the LINK registers are shared between the two SoCs, the D-PHY registers differ. Also the VCLK range differs on both these SoCs. To accommodate these differences `struct rzg2l_mipi_dsi_hw_info` is introduced and as now passed as OF data. These changes lay the groundwork for the upcoming RZ/V2H(P) SoC support by allowing SoC-specific data to be passed through OF. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Reviewed-by: Laurent Pinchart --- v4->v5: - Dropped RZ_MIPI_DSI_FEATURE_DPHY_RST feature flag - Added Reviewed tag from Biju v3->v4: - No changes v2->v3: - Dropped !dsi->info check in rzg2l_mipi_dsi_probe() as it is not needed. v1->v2: - Added DPHY_RST as feature flag --- .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 51 ++++++++++++++----- .../drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h | 2 - 2 files changed, 38 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/d= rm/renesas/rz-du/rzg2l_mipi_dsi.c index 3f6988303e63..00c2bc6e9d6c 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -28,10 +28,23 @@ =20 #include "rzg2l_mipi_dsi_regs.h" =20 +struct rzg2l_mipi_dsi; + +struct rzg2l_mipi_dsi_hw_info { + int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, unsigned long hsfreq); + void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi); + u32 phy_reg_offset; + u32 link_reg_offset; + unsigned long max_dclk; + unsigned long min_dclk; +}; + struct rzg2l_mipi_dsi { struct device *dev; void __iomem *mmio; =20 + const struct rzg2l_mipi_dsi_hw_info *info; + struct reset_control *rstc; struct reset_control *arstc; struct reset_control *prstc; @@ -164,22 +177,22 @@ static const struct rzg2l_mipi_dsi_timings rzg2l_mipi= _dsi_global_timings[] =3D { =20 static void rzg2l_mipi_dsi_phy_write(struct rzg2l_mipi_dsi *dsi, u32 reg, = u32 data) { - iowrite32(data, dsi->mmio + reg); + iowrite32(data, dsi->mmio + dsi->info->phy_reg_offset + reg); } =20 static void rzg2l_mipi_dsi_link_write(struct rzg2l_mipi_dsi *dsi, u32 reg,= u32 data) { - iowrite32(data, dsi->mmio + LINK_REG_OFFSET + reg); + iowrite32(data, dsi->mmio + dsi->info->link_reg_offset + reg); } =20 static u32 rzg2l_mipi_dsi_phy_read(struct rzg2l_mipi_dsi *dsi, u32 reg) { - return ioread32(dsi->mmio + reg); + return ioread32(dsi->mmio + dsi->info->phy_reg_offset + reg); } =20 static u32 rzg2l_mipi_dsi_link_read(struct rzg2l_mipi_dsi *dsi, u32 reg) { - return ioread32(dsi->mmio + LINK_REG_OFFSET + reg); + return ioread32(dsi->mmio + dsi->info->link_reg_offset + reg); } =20 /* -----------------------------------------------------------------------= ------ @@ -294,7 +307,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi= *dsi, mode->clock * MILLI, vclk_rate); hsfreq =3D DIV_ROUND_CLOSEST_ULL(vclk_rate * bpp, dsi->lanes); =20 - ret =3D rzg2l_mipi_dsi_dphy_init(dsi, hsfreq); + ret =3D dsi->info->dphy_init(dsi, hsfreq); if (ret < 0) goto err_phy; =20 @@ -337,7 +350,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi= *dsi, return 0; =20 err_phy: - rzg2l_mipi_dsi_dphy_exit(dsi); + dsi->info->dphy_exit(dsi); pm_runtime_put(dsi->dev); =20 return ret; @@ -345,7 +358,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi= *dsi, =20 static void rzg2l_mipi_dsi_stop(struct rzg2l_mipi_dsi *dsi) { - rzg2l_mipi_dsi_dphy_exit(dsi); + dsi->info->dphy_exit(dsi); pm_runtime_put(dsi->dev); } =20 @@ -587,10 +600,12 @@ rzg2l_mipi_dsi_bridge_mode_valid(struct drm_bridge *b= ridge, const struct drm_display_info *info, const struct drm_display_mode *mode) { - if (mode->clock > 148500) + struct rzg2l_mipi_dsi *dsi =3D bridge_to_rzg2l_mipi_dsi(bridge); + + if (mode->clock > dsi->info->max_dclk) return MODE_CLOCK_HIGH; =20 - if (mode->clock < 5803) + if (mode->clock < dsi->info->min_dclk) return MODE_CLOCK_LOW; =20 return MODE_OK; @@ -716,6 +731,8 @@ static int rzg2l_mipi_dsi_probe(struct platform_device = *pdev) platform_set_drvdata(pdev, dsi); dsi->dev =3D &pdev->dev; =20 + dsi->info =3D of_device_get_match_data(&pdev->dev); + ret =3D drm_of_get_data_lanes_count_ep(dsi->dev->of_node, 1, 0, 1, 4); if (ret < 0) return dev_err_probe(dsi->dev, ret, @@ -759,13 +776,13 @@ static int rzg2l_mipi_dsi_probe(struct platform_devic= e *pdev) * mode->clock and format are not available. So initialize DPHY with * timing parameters for 80Mbps. */ - ret =3D rzg2l_mipi_dsi_dphy_init(dsi, 80000000); + ret =3D dsi->info->dphy_init(dsi, 80000000); if (ret < 0) goto err_phy; =20 txsetr =3D rzg2l_mipi_dsi_link_read(dsi, TXSETR); dsi->num_data_lanes =3D min(((txsetr >> 16) & 3) + 1, num_data_lanes); - rzg2l_mipi_dsi_dphy_exit(dsi); + dsi->info->dphy_exit(dsi); pm_runtime_put(dsi->dev); =20 /* Initialize the DRM bridge. */ @@ -782,7 +799,7 @@ static int rzg2l_mipi_dsi_probe(struct platform_device = *pdev) return 0; =20 err_phy: - rzg2l_mipi_dsi_dphy_exit(dsi); + dsi->info->dphy_exit(dsi); pm_runtime_put(dsi->dev); err_pm_disable: pm_runtime_disable(dsi->dev); @@ -797,8 +814,16 @@ static void rzg2l_mipi_dsi_remove(struct platform_devi= ce *pdev) pm_runtime_disable(&pdev->dev); } =20 +static const struct rzg2l_mipi_dsi_hw_info rzg2l_mipi_dsi_info =3D { + .dphy_init =3D rzg2l_mipi_dsi_dphy_init, + .dphy_exit =3D rzg2l_mipi_dsi_dphy_exit, + .link_reg_offset =3D 0x10000, + .max_dclk =3D 148500, + .min_dclk =3D 5803, +}; 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Mon, 12 May 2025 11:23:55 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:581b:951a:bc46:a124]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f5a4c5f6sm13175497f8f.86.2025.05.12.11.23.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 May 2025 11:23:55 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Biju Das , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , Laurent Pinchart , dri-devel@lists.freedesktop.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v5 07/12] drm: renesas: rz-du: mipi_dsi: Make "rst" reset control optional for RZ/V2H(P) Date: Mon, 12 May 2025 19:23:25 +0100 Message-ID: <20250512182330.238259-8-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250512182330.238259-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250512182330.238259-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar In preparation for adding support for the Renesas RZ/V2H(P) SoC, make the "rst" reset control optional in the MIPI DSI driver. The RZ/V2H(P) SoC does not provide this reset line, and attempting to acquire it using the mandatory API causes probe failure. Switching to devm_reset_control_get_optional_exclusive() ensures compatibility with both SoCs that provide this reset line and those that do not, such as RZ/V2H(P). Signed-off-by: Lad Prabhakar Reviewed-by: Laurent Pinchart --- v4->v5: - New patch --- drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/d= rm/renesas/rz-du/rzg2l_mipi_dsi.c index 00c2bc6e9d6c..5fc607be0c46 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -748,7 +748,7 @@ static int rzg2l_mipi_dsi_probe(struct platform_device = *pdev) if (IS_ERR(dsi->vclk)) return PTR_ERR(dsi->vclk); =20 - dsi->rstc =3D devm_reset_control_get_exclusive(dsi->dev, "rst"); + dsi->rstc =3D devm_reset_control_get_optional_exclusive(dsi->dev, "rst"); if (IS_ERR(dsi->rstc)) return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc), "failed to get rst\n"); --=20 2.49.0 From nobody Mon Feb 9 19:11:09 2026 Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5365F29C33A; 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Mon, 12 May 2025 11:23:57 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:581b:951a:bc46:a124]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f5a4c5f6sm13175497f8f.86.2025.05.12.11.23.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 May 2025 11:23:56 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Biju Das , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , Laurent Pinchart , dri-devel@lists.freedesktop.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v5 08/12] drm: renesas: rz-du: mipi_dsi: Use mHz for D-PHY frequency calculations Date: Mon, 12 May 2025 19:23:26 +0100 Message-ID: <20250512182330.238259-9-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250512182330.238259-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250512182330.238259-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Pass the HSFREQ in milli-Hz to the `dphy_init()` callback to improve precision, especially for the RZ/V2H(P) SoC, where PLL dividers require high accuracy. These changes prepare the driver for upcoming RZ/V2H(P) SoC support. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das --- v4->v5: - Added Reviewed tag from Biju v3->v4: - Used MILLI instead of KILO - Made use of mul_u32_u32() for multiplication v2->v3: - Replaced `unsigned long long` with `u64` - Replaced *_mhz with *_millihz` in functions v1->v2: - No changes --- drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/d= rm/renesas/rz-du/rzg2l_mipi_dsi.c index 5fc607be0c46..f93519613662 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -31,7 +31,7 @@ struct rzg2l_mipi_dsi; =20 struct rzg2l_mipi_dsi_hw_info { - int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, unsigned long hsfreq); + int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, u64 hsfreq_millihz); void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi); u32 phy_reg_offset; u32 link_reg_offset; @@ -200,8 +200,9 @@ static u32 rzg2l_mipi_dsi_link_read(struct rzg2l_mipi_d= si *dsi, u32 reg) */ =20 static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi, - unsigned long hsfreq) + u64 hsfreq_millihz) { + unsigned long hsfreq =3D DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, MILLI); const struct rzg2l_mipi_dsi_timings *dphy_timings; unsigned int i; u32 dphyctrl0; @@ -274,6 +275,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi= *dsi, const struct drm_display_mode *mode) { unsigned long hsfreq, vclk_rate; + u64 hsfreq_millihz; unsigned int bpp; u32 txsetr; u32 clstptsetr; @@ -305,9 +307,9 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi= *dsi, if (vclk_rate !=3D mode->clock * MILLI) dev_info(dsi->dev, "Requested vclk rate %lu, actual %lu mismatch\n", mode->clock * MILLI, vclk_rate); - hsfreq =3D DIV_ROUND_CLOSEST_ULL(vclk_rate * bpp, dsi->lanes); + hsfreq_millihz =3D DIV_ROUND_CLOSEST_ULL(mul_u32_u32(vclk_rate, bpp * MIL= LI), dsi->lanes); =20 - ret =3D dsi->info->dphy_init(dsi, hsfreq); + ret =3D dsi->info->dphy_init(dsi, hsfreq_millihz); if (ret < 0) goto err_phy; =20 @@ -315,6 +317,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi= *dsi, txsetr =3D TXSETR_DLEN | TXSETR_NUMLANEUSE(dsi->lanes - 1) | TXSETR_CLEN; rzg2l_mipi_dsi_link_write(dsi, TXSETR, txsetr); =20 + hsfreq =3D DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, MILLI); /* * Global timings characteristic depends on high speed Clock Frequency * Currently MIPI DSI-IF just supports maximum FHD@60 with: @@ -776,7 +779,7 @@ static int rzg2l_mipi_dsi_probe(struct platform_device = *pdev) * mode->clock and format are not available. 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Mon, 12 May 2025 11:23:57 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Biju Das , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , Laurent Pinchart , dri-devel@lists.freedesktop.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v5 09/12] drm: renesas: rz-du: mipi_dsi: Add feature flag for 16BPP support Date: Mon, 12 May 2025 19:23:27 +0100 Message-ID: <20250512182330.238259-10-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250512182330.238259-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250512182330.238259-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Introduce the `RZ_MIPI_DSI_FEATURE_16BPP` flag in `rzg2l_mipi_dsi_hw_info` to indicate support for 16BPP pixel formats. The RZ/V2H(P) SoC supports 16BPP, whereas this feature is missing on the RZ/G2L SoC. Update the `mipi_dsi_host_attach()` function to check this flag before allowing 16BPP formats. If the SoC does not support 16BPP, return an error to prevent incorrect format selection. This change enables finer-grained format support control for different SoC variants. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Reviewed-by: Laurent Pinchart --- v4->v5: - Updated RZ_MIPI_DSI_FEATURE_16BPP macro to use BIT(0) - Added Reviewed tag from Biju v3->v4: - No changes v2->v3: - No changes v1->v2: - Renamed RZ_MIPI_DSI_FEATURE_16BPP --- drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/d= rm/renesas/rz-du/rzg2l_mipi_dsi.c index f93519613662..55a1c1b043c8 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -28,6 +28,8 @@ =20 #include "rzg2l_mipi_dsi_regs.h" =20 +#define RZ_MIPI_DSI_FEATURE_16BPP BIT(0) + struct rzg2l_mipi_dsi; =20 struct rzg2l_mipi_dsi_hw_info { @@ -37,6 +39,7 @@ struct rzg2l_mipi_dsi_hw_info { u32 link_reg_offset; unsigned long max_dclk; unsigned long min_dclk; + u8 features; }; =20 struct rzg2l_mipi_dsi { @@ -643,8 +646,16 @@ static int rzg2l_mipi_dsi_host_attach(struct mipi_dsi_= host *host, =20 switch (mipi_dsi_pixel_format_to_bpp(device->format)) { case 24: + break; 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charset="utf-8" From: Lad Prabhakar Introduce the `dphy_late_init` callback in `rzg2l_mipi_dsi_hw_info` to allow additional D-PHY register configurations after enabling data and clock lanes. This is required for the RZ/V2H(P) SoC but not for the RZ/G2L SoC. Modify `rzg2l_mipi_dsi_startup()` to invoke `dphy_late_init` if defined, ensuring SoC-specific initialization is performed only when necessary. This change prepares for RZ/V2H(P) SoC support while maintaining compatibility with existing platforms. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Reviewed-by: Laurent Pinchart --- v4->v5: - Added Reviewed tag from Biju v3->v4: - No changes v2->v3: - No changes v1->v2: - No changes --- drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/d= rm/renesas/rz-du/rzg2l_mipi_dsi.c index 55a1c1b043c8..e1ce21a9ddb3 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -34,6 +34,7 @@ struct rzg2l_mipi_dsi; =20 struct rzg2l_mipi_dsi_hw_info { int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, u64 hsfreq_millihz); + void (*dphy_late_init)(struct rzg2l_mipi_dsi *dsi); void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi); u32 phy_reg_offset; u32 link_reg_offset; @@ -320,6 +321,9 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi= *dsi, txsetr =3D TXSETR_DLEN | TXSETR_NUMLANEUSE(dsi->lanes - 1) | TXSETR_CLEN; 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Mon, 12 May 2025 11:24:00 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:581b:951a:bc46:a124]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f5a4c5f6sm13175497f8f.86.2025.05.12.11.23.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 May 2025 11:24:00 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Biju Das , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , Laurent Pinchart , dri-devel@lists.freedesktop.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v5 11/12] drm: renesas: rz-du: mipi_dsi: Add function pointers for configuring VCLK and mode validation Date: Mon, 12 May 2025 19:23:29 +0100 Message-ID: <20250512182330.238259-12-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250512182330.238259-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250512182330.238259-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Introduce `dphy_conf_clks` and `dphy_mode_clk_check` callbacks in `rzg2l_mipi_dsi_hw_info` to configure the VCLK and validate supported display modes. On the RZ/V2H(P) SoC, the DSI PLL dividers need to be as accurate as possible. To ensure compatibility with both RZ/G2L and RZ/V2H(P) SoCs, function pointers are introduced. Modify `rzg2l_mipi_dsi_startup()` to use `dphy_conf_clks` for clock configuration and `rzg2l_mipi_dsi_bridge_mode_valid()` to invoke `dphy_mode_clk_check` for mode validation. This change ensures proper operation across different SoC variants by allowing fine-grained control over clock configuration and mode validation. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das --- v4->v5: - Added Reviewed tag from Biju v3->v4: - Replaced KILO with MILLI v2->v3: - Replaced unsigned long long with u64 v1->v2: - No changes --- .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 65 +++++++++++++------ 1 file changed, 45 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/d= rm/renesas/rz-du/rzg2l_mipi_dsi.c index e1ce21a9ddb3..35f0bceac055 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -36,6 +36,10 @@ struct rzg2l_mipi_dsi_hw_info { int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, u64 hsfreq_millihz); void (*dphy_late_init)(struct rzg2l_mipi_dsi *dsi); void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi); + int (*dphy_conf_clks)(struct rzg2l_mipi_dsi *dsi, unsigned long mode_freq, + u64 *hsfreq_millihz); + unsigned int (*dphy_mode_clk_check)(struct rzg2l_mipi_dsi *dsi, + unsigned long mode_freq); u32 phy_reg_offset; u32 link_reg_offset; unsigned long max_dclk; @@ -275,12 +279,39 @@ static void rzg2l_mipi_dsi_dphy_exit(struct rzg2l_mip= i_dsi *dsi) reset_control_assert(dsi->rstc); } =20 +static int rzg2l_dphy_conf_clks(struct rzg2l_mipi_dsi *dsi, unsigned long = mode_freq, + u64 *hsfreq_millihz) +{ + unsigned long vclk_rate; + unsigned int bpp; + + clk_set_rate(dsi->vclk, mode_freq * MILLI); + /* + * Relationship between hsclk and vclk must follow + * vclk * bpp =3D hsclk * 8 * lanes + * where vclk: video clock (Hz) + * bpp: video pixel bit depth + * hsclk: DSI HS Byte clock frequency (Hz) + * lanes: number of data lanes + * + * hsclk(bit) =3D hsclk(byte) * 8 =3D hsfreq + */ + bpp =3D mipi_dsi_pixel_format_to_bpp(dsi->format); + vclk_rate =3D clk_get_rate(dsi->vclk); + if (vclk_rate !=3D mode_freq * MILLI) + dev_info(dsi->dev, "Requested vclk rate %lu, actual %lu mismatch\n", + mode_freq * MILLI, vclk_rate); + *hsfreq_millihz =3D DIV_ROUND_CLOSEST_ULL(mul_u32_u32(vclk_rate, bpp * MI= LLI), + dsi->lanes); + + return 0; +} + static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, const struct drm_display_mode *mode) { - unsigned long hsfreq, vclk_rate; + unsigned long hsfreq; u64 hsfreq_millihz; - unsigned int bpp; u32 txsetr; u32 clstptsetr; u32 lptrnstsetr; @@ -294,24 +325,9 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_ds= i *dsi, if (ret < 0) return ret; =20 - clk_set_rate(dsi->vclk, mode->clock * MILLI); - - /* - * Relationship between hsclk and vclk must follow - * vclk * bpp =3D hsclk * 8 * lanes - * where vclk: video clock (Hz) - * bpp: video pixel bit depth - * hsclk: DSI HS Byte clock frequency (Hz) - * lanes: number of data lanes - * - * hsclk(bit) =3D hsclk(byte) * 8 =3D hsfreq - */ - bpp =3D mipi_dsi_pixel_format_to_bpp(dsi->format); - vclk_rate =3D clk_get_rate(dsi->vclk); - if (vclk_rate !=3D mode->clock * MILLI) - dev_info(dsi->dev, "Requested vclk rate %lu, actual %lu mismatch\n", - mode->clock * MILLI, vclk_rate); - hsfreq_millihz =3D DIV_ROUND_CLOSEST_ULL(mul_u32_u32(vclk_rate, bpp * MIL= LI), dsi->lanes); + ret =3D dsi->info->dphy_conf_clks(dsi, mode->clock, &hsfreq_millihz); + if (ret < 0) + goto err_phy; =20 ret =3D dsi->info->dphy_init(dsi, hsfreq_millihz); if (ret < 0) @@ -618,6 +634,14 @@ rzg2l_mipi_dsi_bridge_mode_valid(struct drm_bridge *br= idge, if (mode->clock < dsi->info->min_dclk) return MODE_CLOCK_LOW; =20 + if (dsi->info->dphy_mode_clk_check) { + enum drm_mode_status status; + + status =3D dsi->info->dphy_mode_clk_check(dsi, mode->clock); + if (status !=3D MODE_OK) + return status; + } + return MODE_OK; } =20 @@ -835,6 +859,7 @@ static void rzg2l_mipi_dsi_remove(struct platform_devic= e *pdev) static const struct rzg2l_mipi_dsi_hw_info rzg2l_mipi_dsi_info =3D { .dphy_init =3D rzg2l_mipi_dsi_dphy_init, .dphy_exit =3D rzg2l_mipi_dsi_dphy_exit, + .dphy_conf_clks =3D rzg2l_dphy_conf_clks, .link_reg_offset =3D 0x10000, .max_dclk =3D 148500, .min_dclk =3D 5803, --=20 2.49.0 From nobody Mon Feb 9 19:11:09 2026 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6E4229826B; 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Mon, 12 May 2025 11:24:01 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:581b:951a:bc46:a124]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f5a4c5f6sm13175497f8f.86.2025.05.12.11.24.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 May 2025 11:24:01 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Biju Das , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , Laurent Pinchart , dri-devel@lists.freedesktop.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v5 12/12] drm: renesas: rz-du: mipi_dsi: Add support for LPCLK clock handling Date: Mon, 12 May 2025 19:23:30 +0100 Message-ID: <20250512182330.238259-13-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250512182330.238259-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250512182330.238259-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add LPCLK clock support in the RZ/G2L MIPI DSI driver via the optional clock API. This clock is required by some SoCs like RZ/V2H(P) for proper DPHY configuration, whereas it is absent on others like RZ/G2L. Introduce a new `lpclk` field in the `rzg2l_mipi_dsi` structure and conditionally acquire the "lpclk" clock using `devm_clk_get_optional()` during probe. This allows LPCLK-aware SoCs to pass the clock via device tree without impacting existing platforms. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das --- v4->v5: - Made use of devm_clk_get_optional() for lpclk - Added Reviewed tag from Biju v3->v4 - No changes v2->v3: - No changes v1->v2: - Added LPCLK as feature flag --- drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/d= rm/renesas/rz-du/rzg2l_mipi_dsi.c index 35f0bceac055..98d2f30ae79d 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -62,6 +62,7 @@ struct rzg2l_mipi_dsi { struct drm_bridge *next_bridge; =20 struct clk *vclk; + struct clk *lpclk; =20 enum mipi_dsi_pixel_format format; unsigned int num_data_lanes; @@ -790,6 +791,10 @@ static int rzg2l_mipi_dsi_probe(struct platform_device= *pdev) if (IS_ERR(dsi->vclk)) return PTR_ERR(dsi->vclk); =20 + dsi->lpclk =3D devm_clk_get_optional(dsi->dev, "lpclk"); + if (IS_ERR(dsi->lpclk)) + return PTR_ERR(dsi->lpclk); + dsi->rstc =3D devm_reset_control_get_optional_exclusive(dsi->dev, "rst"); if (IS_ERR(dsi->rstc)) return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc), --=20 2.49.0