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[2a02:9142:4580:400::8]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f57dde27sm13228032f8f.17.2025.05.12.09.22.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 May 2025 09:22:33 -0700 (PDT) From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= To: linux-mtd@lists.infradead.org, dregan@broadcom.com, miquel.raynal@bootlin.com, bcm-kernel-feedback-list@broadcom.com, florian.fainelli@broadcom.com, rafal@milecki.pl, computersforpeace@gmail.com, kamal.dasu@broadcom.com, dan.beygelman@broadcom.com, william.zhang@broadcom.com, frieder.schrempf@kontron.de, linux-kernel@vger.kernel.org, vigneshr@ti.com, richard@nod.at, bbrezillon@kernel.org, kdasu.kdev@gmail.com, jaimeliao.tw@gmail.com, kilobyte@angband.pl, jonas.gorski@gmail.com, dgcbueu@gmail.com Cc: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Subject: [PATCH] mtd: rawnand: brcmnand: legacy exec_op implementation Date: Mon, 12 May 2025 18:22:26 +0200 Message-Id: <20250512162226.415154-1-noltari@gmail.com> X-Mailer: git-send-email 2.39.5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Commit 3c8260ce7663 ("mtd: rawnand: brcmnand: exec_op implementation") removed legacy interface functions, breaking < v5.0 controllers support. In order to fix older controllers we need to add an alternative exec_op implementation which doesn't rely on low level registers. Fixes: 3c8260ce7663 ("mtd: rawnand: brcmnand: exec_op implementation") Signed-off-by: =C3=81lvaro Fern=C3=A1ndez Rojas --- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 174 ++++++++++++++++++++++- 1 file changed, 168 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/ra= w/brcmnand/brcmnand.c index 17f6d9723df9..919e322189d5 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -2490,14 +2490,177 @@ static int brcmnand_op_is_reset(const struct nand_= operation *op) return 0; } =20 +static int brcmnand_exec_instructions(struct nand_chip *chip, + const struct nand_operation *op) +{ + struct brcmnand_host *host =3D nand_get_controller_data(chip); + unsigned int i; + int ret =3D 0; + + for (i =3D 0; i < op->ninstrs; i++) { + ret =3D brcmnand_exec_instr(host, i, op); + if (ret) + break; + } + + return ret; +} + +static int brcmnand_exec_instructions_legacy(struct nand_chip *chip, + const struct nand_operation *op) +{ + struct mtd_info *mtd =3D nand_to_mtd(chip); + struct brcmnand_host *host =3D nand_get_controller_data(chip); + struct brcmnand_controller *ctrl =3D host->ctrl; + const struct nand_op_instr *instr; + unsigned int i, j; + int cmd =3D CMD_NULL, last_cmd =3D CMD_NULL; + int ret =3D 0; + + for (i =3D 0; i < op->ninstrs; i++) { + instr =3D &op->instrs[i]; + + if (instr->type =3D=3D NAND_OP_CMD_INSTR) { + if (instr->ctx.cmd.opcode =3D=3D NAND_CMD_READID) { + cmd =3D CMD_DEVICE_ID_READ; + } else if (instr->ctx.cmd.opcode =3D=3D NAND_CMD_READOOB) { + cmd =3D CMD_SPARE_AREA_READ; + } else if (instr->ctx.cmd.opcode =3D=3D NAND_CMD_ERASE1) { + cmd =3D CMD_BLOCK_ERASE; + brcmnand_wp(mtd, 0); + } else if (instr->ctx.cmd.opcode =3D=3D NAND_CMD_ERASE2) { + cmd =3D CMD_NULL; + } else if (instr->ctx.cmd.opcode =3D=3D NAND_CMD_PARAM) { + cmd =3D CMD_PARAMETER_READ; + } else if (instr->ctx.cmd.opcode =3D=3D NAND_CMD_RNDOUT) { + cmd =3D CMD_PARAMETER_CHANGE_COL; + } else if (instr->ctx.cmd.opcode =3D=3D NAND_CMD_RNDOUTSTART) { + cmd =3D CMD_NULL; + } else { + dev_err(ctrl->dev, "unsupported cmd=3D%d\n", + instr->ctx.cmd.opcode); + ret =3D -EOPNOTSUPP; + break; + } + } else if (instr->type =3D=3D NAND_OP_ADDR_INSTR) { + u64 addr =3D 0; + + if (cmd =3D=3D CMD_NULL) + continue; + + if (instr->ctx.addr.naddrs > 8) { + dev_err(ctrl->dev, "unsupported naddrs=3D%u\n", + instr->ctx.addr.naddrs); + ret =3D -EOPNOTSUPP; + break; + } + + for (j =3D 0; j < instr->ctx.addr.naddrs; j++) + addr |=3D (instr->ctx.addr.addrs[j]) << (j << 3); + + if (cmd =3D=3D CMD_PARAMETER_CHANGE_COL) { + addr &=3D ~((u64)(FC_BYTES - 1)); + + if (brcmnand_get_sector_size_1k(host)) { + host->hwcfg.sector_size_1k =3D + brcmnand_get_sector_size_1k(host); + brcmnand_set_sector_size_1k(host, 0); + } + } + + host->last_addr =3D addr; + + brcmnand_set_cmd_addr(mtd, addr); + brcmnand_send_cmd(host, cmd); + last_cmd =3D cmd; + cmd =3D CMD_NULL; + brcmnand_waitfunc(chip); + + if (last_cmd =3D=3D CMD_PARAMETER_READ || + last_cmd =3D=3D CMD_PARAMETER_CHANGE_COL) { + /* Copy flash cache word-wise */ + u32 *flash_cache =3D (u32 *)ctrl->flash_cache; + + brcmnand_soc_data_bus_prepare(ctrl->soc, true); + + /* + * Must cache the FLASH_CACHE now, since changes in + * SECTOR_SIZE_1K may invalidate it + */ + for (i =3D 0; i < FC_WORDS; i++) + /* + * Flash cache is big endian for parameter pages, at + * least on STB SoCs + */ + flash_cache[i] =3D be32_to_cpu(brcmnand_read_fc(ctrl, i)); + + brcmnand_soc_data_bus_unprepare(ctrl->soc, true); + + /* Cleanup from HW quirk: restore SECTOR_SIZE_1K */ + if (host->hwcfg.sector_size_1k) + brcmnand_set_sector_size_1k(host, + host->hwcfg.sector_size_1k); + } else if (last_cmd =3D=3D NAND_CMD_ERASE1) { + brcmnand_wp(mtd, 1); + } + } else if (instr->type =3D=3D NAND_OP_DATA_IN_INSTR) { + u8 *in =3D instr->ctx.data.buf.in; + + if (last_cmd =3D=3D CMD_DEVICE_ID_READ) { + u32 val; + + if (instr->ctx.data.len > 8) { + dev_err(ctrl->dev, "unsupported len=3D%u\n", + instr->ctx.data.len); + ret =3D -EOPNOTSUPP; + break; + } + + for (j =3D 0; j < instr->ctx.data.len; j++) { + if (j =3D=3D 0) + val =3D brcmnand_read_reg(ctrl, BRCMNAND_ID); + else if (j =3D=3D 4) + val =3D brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT); + + in[j] =3D (val >> (24 - ((j % 4) << 3))) & 0xff; + } + } else if (last_cmd =3D=3D CMD_SPARE_AREA_READ) { + for (j =3D 0; j < instr->ctx.data.len; j++) + in[j] =3D oob_reg_read(ctrl, j); + } else if (last_cmd =3D=3D NAND_CMD_PARAM || last_cmd =3D=3D NAND_CMD_R= NDOUT) { + u64 addr; + u32 offs; + + for (j =3D 0; j < instr->ctx.data.len; j++) { + addr =3D host->last_addr =3D j; + offs =3D addr & (FC_BYTES - 1); + + if (j > 0 && offs =3D=3D 0) + nand_change_read_column_op(chip, addr, NULL, 0, + false); + + in[j] =3D ctrl->flash_cache[offs]; + } + } + } else if (instr->type =3D=3D NAND_OP_WAITRDY_INSTR) { + ret =3D bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY, NAND_CTRL_RDY, 0); + } else { + dev_err(ctrl->dev, "unsupported instruction type: %d\n", instr->type); + ret =3D -EINVAL; + } + } + + return ret; +} + static int brcmnand_exec_op(struct nand_chip *chip, const struct nand_operation *op, bool check_only) { struct brcmnand_host *host =3D nand_get_controller_data(chip); + struct brcmnand_controller *ctrl =3D host->ctrl; struct mtd_info *mtd =3D nand_to_mtd(chip); u8 *status; - unsigned int i; int ret =3D 0; =20 if (check_only) @@ -2525,11 +2688,10 @@ static int brcmnand_exec_op(struct nand_chip *chip, if (op->deassert_wp) brcmnand_wp(mtd, 0); =20 - for (i =3D 0; i < op->ninstrs; i++) { - ret =3D brcmnand_exec_instr(host, i, op); - if (ret) - break; - } + if (ctrl->nand_version >=3D 0x500) + brcmnand_exec_instructions(chip, op); + else + brcmnand_exec_instructions_legacy(chip, op); =20 if (op->deassert_wp) brcmnand_wp(mtd, 1); --=20 2.39.5