From nobody Sat Feb 7 18:15:08 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2DC342571C1; Mon, 12 May 2025 09:39:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747042789; cv=none; b=sdzb/lDInuF43KO3FySTClFQhkbf7PttrWEAbNkx6a1UYQuSxPmwsKB82/RnnTOv9zhMwMYBF14Wt8DUAm29ws0jV+Pfk/5qV3HwArmHfO/gf7zwpNXqbace3V5GzkeCgBZ8BLPot6CHHZtJiWKSc8zoUn4ADgr/4Smjb6VXvb4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747042789; c=relaxed/simple; bh=eEsJfpXhhFEznIeL9s5dBzJb2o4yce1yvI0AwzyhvH4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YdTsrZIwW3faK35veyiv0V9qiQ32EJjmchb9aJjQhgp/TMpuoAsWdaT8ST246wRX6fDN3PyeB5z4/NsRHNA+kx7+AH758Xp6rbTFAM8R47wuDZLAuk9uvB93J/oYXbFMAM2aTQqq7b5Ga6dkmtvZGhSvS4ClNDSL+zr9c2ATQQo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=FBtv97dg; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="FBtv97dg" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1747042787; x=1778578787; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eEsJfpXhhFEznIeL9s5dBzJb2o4yce1yvI0AwzyhvH4=; b=FBtv97dgPnubQ9Ew5lterl++4ucVoPY6A89KTwQHc8kOpOZwr1mH1ogM S3T0QiMpEMI7h6IGrEG75Umx9JMvrMhAh/7NLsWXleG505q9u+4kLuQl0 RWEv7EzYlBj75s21aabroH79Llw4D+A2vgiKhEuJXtxK1ceNjCx3PTxbP Cqv1i1RW8XB7P0S6ajW4twB0iUmToNgHxHoxYMfr1gP4eVwwIjuJNjvyp PrXaxBY6n95CU2nY8FVIyNcZWJ73DQErt8u/GNqb9qSMLw6ioDfkf7hqN intoy75dGdmrLQyTKsK50LenntK9gSOOLG5aBwrAFNiSwemhfYAa0fgQR w==; X-CSE-ConnectionGUID: SePu6qAUTwOroCJYjeR9+w== X-CSE-MsgGUID: jk0v7fcFRXG+6im9io6sPQ== X-IronPort-AV: E=McAfee;i="6700,10204,11430"; a="36457524" X-IronPort-AV: E=Sophos;i="6.15,281,1739865600"; d="scan'208";a="36457524" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2025 02:39:46 -0700 X-CSE-ConnectionGUID: nJwKMXrLTJq9EhbVJQU5/A== X-CSE-MsgGUID: Rfq6piiaQ2qC4mtGzhMEZw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,281,1739865600"; d="scan'208";a="142214289" Received: from bvivekan-mobl1.gar.corp.intel.com (HELO localhost.localdomain) ([10.245.245.139]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2025 02:39:44 -0700 From: Adrian Hunter To: Arnaldo Carvalho de Melo , Jiri Olsa , Namhyung Kim Cc: Alexander Shishkin , Ian Rogers , Kan Liang , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Subject: [PATCH 1/3] perf intel-pt: Fix PEBS-via-PT data_src Date: Mon, 12 May 2025 12:39:30 +0300 Message-ID: <20250512093932.79854-2-adrian.hunter@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250512093932.79854-1-adrian.hunter@intel.com> References: <20250512093932.79854-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Fixes commit did not add support for decoding PEBS-via-PT data_src. Fix by adding support. PEBS-via-PT is a feature of some E-core processors, starting with processors based on Tremont microarchitecture. Because the kernel only supports Intel PT features that are on all processors, there is no support for PEBS-via-PT on hybrids. Currently that leaves processors based on Tremont, Gracemont and Crestmont, however there are no events on Tremont that produce data_src information, and for Gracemont and Crestmont there are only: mem-loads event=3D0xd0,umask=3D0x5,ldlat=3D3 mem-stores event=3D0xd0,umask=3D0x6 Affected processors include Alder Lake N (Gracemont), Sierra Forest (Crestmont) and Grand Ridge (Crestmont). Example: # perf record -d -e intel_pt/branch=3D0/ -e mem-loads/aux-output/pp uname Before: # perf.before script --itrace=3Do -Fdata_src 0 |OP No|LVL N/A|SNP N/A|TLB N/A|LCK No|BLK N/A 0 |OP No|LVL N/A|SNP N/A|TLB N/A|LCK No|BLK N/A After: # perf script --itrace=3Do -Fdata_src 10268100142 |OP LOAD|LVL L1 hit|SNP None|TLB L1 or L2 hit|LCK No|BLK N/A 10450100442 |OP LOAD|LVL L2 hit|SNP None|TLB L2 miss|LCK No|BLK N/A Fixes: 975846eddf907 ("perf intel-pt: Add memory information to synthesized= PEBS sample") Signed-off-by: Adrian Hunter Reviewed-by: Kan Liang --- tools/perf/util/intel-pt.c | 205 ++++++++++++++++++++++++++++++++++++- 1 file changed, 202 insertions(+), 3 deletions(-) diff --git a/tools/perf/util/intel-pt.c b/tools/perf/util/intel-pt.c index 4e8a9b172fbc..9b1011fe4826 100644 --- a/tools/perf/util/intel-pt.c +++ b/tools/perf/util/intel-pt.c @@ -127,6 +127,7 @@ struct intel_pt { =20 bool single_pebs; bool sample_pebs; + int pebs_data_src_fmt; struct evsel *pebs_evsel; =20 u64 evt_sample_type; @@ -175,6 +176,7 @@ enum switch_state { struct intel_pt_pebs_event { struct evsel *evsel; u64 id; + int data_src_fmt; }; =20 struct intel_pt_queue { @@ -2272,7 +2274,146 @@ static void intel_pt_add_lbrs(struct branch_stack *= br_stack, } } =20 -static int intel_pt_do_synth_pebs_sample(struct intel_pt_queue *ptq, struc= t evsel *evsel, u64 id) +#define P(a, b) PERF_MEM_S(a, b) +#define OP_LH (P(OP, LOAD) | P(LVL, HIT)) +#define LEVEL(x) P(LVLNUM, x) +#define REM P(REMOTE, REMOTE) +#define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS)) + +#define PERF_PEBS_DATA_SOURCE_GRT_MAX 0x10 +#define PERF_PEBS_DATA_SOURCE_GRT_MASK (PERF_PEBS_DATA_SOURCE_GRT_MAX - 1) + +/* Based on kernel __intel_pmu_pebs_data_source_grt() and pebs_data_source= */ +static const u64 pebs_data_source_grt[PERF_PEBS_DATA_SOURCE_GRT_MAX] =3D { + P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA), /* L3 miss= |SNP N/A */ + OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* L1 hit|= SNP None */ + OP_LH | P(LVL, LFB) | LEVEL(LFB) | P(SNOOP, NONE), /* LFB/MAB= hit|SNP None */ + OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* L2 hit|= SNP None */ + OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* L3 hit|= SNP None */ + OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT), /* L3 hit|= SNP Hit */ + OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* L3 hit|= SNP HitM */ + OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* L3 hit|= SNP HitM */ + OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD), /* L3 hit|= SNP Fwd */ + OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* Remote = L3 hit|SNP HitM */ + OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, HIT), /* RAM hit= |SNP Hit */ + OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* Remote = L3 hit|SNP Hit */ + OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | SNOOP_NONE_MISS, /* RAM hit= |SNP None or Miss */ + OP_LH | P(LVL, REM_RAM1) | LEVEL(RAM) | REM | SNOOP_NONE_MISS, /* Remote = RAM hit|SNP None or Miss */ + OP_LH | P(LVL, IO) | LEVEL(NA) | P(SNOOP, NONE), /* I/O hit= |SNP None */ + OP_LH | P(LVL, UNC) | LEVEL(NA) | P(SNOOP, NONE), /* Uncache= d hit|SNP None */ +}; + +/* Based on kernel __intel_pmu_pebs_data_source_cmt() and pebs_data_source= */ +static const u64 pebs_data_source_cmt[PERF_PEBS_DATA_SOURCE_GRT_MAX] =3D { + P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA), /* L3 miss|S= NP N/A */ + OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* L1 hit|SN= P None */ + OP_LH | P(LVL, LFB) | LEVEL(LFB) | P(SNOOP, NONE), /* LFB/MAB h= it|SNP None */ + OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* L2 hit|SN= P None */ + OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* L3 hit|SN= P None */ + OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, MISS), /* L3 hit|SN= P Hit */ + OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT), /* L3 hit|SN= P HitM */ + OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD), /* L3 hit|SN= P HitM */ + OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* L3 hit|SN= P Fwd */ + OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* Remote L3= hit|SNP HitM */ + OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, NONE), /* RAM hit|S= NP Hit */ + OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE), /* Remote L3= hit|SNP Hit */ + OP_LH | LEVEL(RAM) | REM | P(SNOOPX, FWD), /* RAM hit|S= NP None or Miss */ + OP_LH | LEVEL(RAM) | REM | P(SNOOP, HITM), /* Remote RA= M hit|SNP None or Miss */ + OP_LH | P(LVL, IO) | LEVEL(NA) | P(SNOOP, NONE), /* I/O hit|S= NP None */ + OP_LH | P(LVL, UNC) | LEVEL(NA) | P(SNOOP, NONE), /* Uncached = hit|SNP None */ +}; + +/* Based on kernel pebs_set_tlb_lock() */ +static inline void pebs_set_tlb_lock(u64 *val, bool tlb, bool lock) +{ + /* + * TLB access + * 0 =3D did not miss 2nd level TLB + * 1 =3D missed 2nd level TLB + */ + if (tlb) + *val |=3D P(TLB, MISS) | P(TLB, L2); + else + *val |=3D P(TLB, HIT) | P(TLB, L1) | P(TLB, L2); + + /* locked prefix */ + if (lock) + *val |=3D P(LOCK, LOCKED); +} + +/* Based on kernel __grt_latency_data() */ +static u64 intel_pt_grt_latency_data(u8 dse, bool tlb, bool lock, bool blk, + const u64 *pebs_data_source) +{ + u64 val; + + dse &=3D PERF_PEBS_DATA_SOURCE_GRT_MASK; + val =3D pebs_data_source[dse]; + + pebs_set_tlb_lock(&val, tlb, lock); + + if (blk) + val |=3D P(BLK, DATA); + else + val |=3D P(BLK, NA); + + return val; +} + +/* Default value for data source */ +#define PERF_MEM_NA (PERF_MEM_S(OP, NA) |\ + PERF_MEM_S(LVL, NA) |\ + PERF_MEM_S(SNOOP, NA) |\ + PERF_MEM_S(LOCK, NA) |\ + PERF_MEM_S(TLB, NA) |\ + PERF_MEM_S(LVLNUM, NA)) + +enum DATA_SRC_FORMAT { + DATA_SRC_FORMAT_ERR =3D -1, + DATA_SRC_FORMAT_NA =3D 0, + DATA_SRC_FORMAT_GRT =3D 1, + DATA_SRC_FORMAT_CMT =3D 2, +}; + +/* Based on kernel grt_latency_data() and cmt_latency_data */ +static u64 intel_pt_get_data_src(u64 mem_aux_info, int data_src_fmt) +{ + switch (data_src_fmt) { + case DATA_SRC_FORMAT_GRT: { + union { + u64 val; + struct { + unsigned int dse:4; + unsigned int locked:1; + unsigned int stlb_miss:1; + unsigned int fwd_blk:1; + unsigned int reserved:25; + }; + } x =3D {.val =3D mem_aux_info}; + return intel_pt_grt_latency_data(x.dse, x.stlb_miss, x.locked, x.fwd_blk, + pebs_data_source_grt); + } + case DATA_SRC_FORMAT_CMT: { + union { + u64 val; + struct { + unsigned int dse:5; + unsigned int locked:1; + unsigned int stlb_miss:1; + unsigned int fwd_blk:1; + unsigned int reserved:24; + }; + } x =3D {.val =3D mem_aux_info}; + return intel_pt_grt_latency_data(x.dse, x.stlb_miss, x.locked, x.fwd_blk, + pebs_data_source_cmt); + } + default: + return PERF_MEM_NA; + } +} + +static int intel_pt_do_synth_pebs_sample(struct intel_pt_queue *ptq, struc= t evsel *evsel, + u64 id, int data_src_fmt) { const struct intel_pt_blk_items *items =3D &ptq->state->items; struct perf_sample sample; @@ -2393,6 +2534,18 @@ static int intel_pt_do_synth_pebs_sample(struct inte= l_pt_queue *ptq, struct evse } } =20 + if (sample_type & PERF_SAMPLE_DATA_SRC) { + if (items->has_mem_aux_info && data_src_fmt) { + if (data_src_fmt < 0) { + pr_err("Intel PT missing data_src info\n"); + return -1; + } + sample.data_src =3D intel_pt_get_data_src(items->mem_aux_info, data_src= _fmt); + } else { + sample.data_src =3D PERF_MEM_NA; + } + } + if (sample_type & PERF_SAMPLE_TRANSACTION && items->has_tsx_aux_info) { u64 ax =3D items->has_rax ? items->rax : 0; /* Refer kernel's intel_hsw_transaction() */ @@ -2413,9 +2566,10 @@ static int intel_pt_synth_single_pebs_sample(struct = intel_pt_queue *ptq) { struct intel_pt *pt =3D ptq->pt; struct evsel *evsel =3D pt->pebs_evsel; + int data_src_fmt =3D pt->pebs_data_src_fmt; u64 id =3D evsel->core.id[0]; =20 - return intel_pt_do_synth_pebs_sample(ptq, evsel, id); + return intel_pt_do_synth_pebs_sample(ptq, evsel, id, data_src_fmt); } =20 static int intel_pt_synth_pebs_sample(struct intel_pt_queue *ptq) @@ -2440,7 +2594,7 @@ static int intel_pt_synth_pebs_sample(struct intel_pt= _queue *ptq) hw_id); return intel_pt_synth_single_pebs_sample(ptq); } - err =3D intel_pt_do_synth_pebs_sample(ptq, pe->evsel, pe->id); + err =3D intel_pt_do_synth_pebs_sample(ptq, pe->evsel, pe->id, pe->data_s= rc_fmt); if (err) return err; } @@ -3407,6 +3561,49 @@ static int intel_pt_process_itrace_start(struct inte= l_pt *pt, event->itrace_start.tid); } =20 +/* + * Events with data_src are identified by L1_Hit_Indication + * refer https://github.com/intel/perfmon + */ +static int intel_pt_data_src_fmt(struct intel_pt *pt, struct evsel *evsel) +{ + struct perf_env *env =3D pt->machine->env; + int fmt =3D DATA_SRC_FORMAT_NA; + + if (!env->cpuid) + return DATA_SRC_FORMAT_ERR; + + /* + * PEBS-via-PT is only supported on E-core non-hybrid. Of those only + * Gracemont and Crestmont have data_src. Check for: + * Alderlake N (Gracemont) + * Sierra Forest (Crestmont) + * Grand Ridge (Crestmont) + */ + + if (!strncmp(env->cpuid, "GenuineIntel,6,190,", 19)) + fmt =3D DATA_SRC_FORMAT_GRT; + + if (!strncmp(env->cpuid, "GenuineIntel,6,175,", 19) || + !strncmp(env->cpuid, "GenuineIntel,6,182,", 19)) + fmt =3D DATA_SRC_FORMAT_CMT; + + if (fmt =3D=3D DATA_SRC_FORMAT_NA) + return fmt; + + /* + * Only data_src events are: + * mem-loads event=3D0xd0,umask=3D0x5 + * mem-stores event=3D0xd0,umask=3D0x6 + */ + if (evsel->core.attr.type =3D=3D PERF_TYPE_RAW && + ((evsel->core.attr.config & 0xffff) =3D=3D 0x5d0 || + (evsel->core.attr.config & 0xffff) =3D=3D 0x6d0)) + return fmt; + + return DATA_SRC_FORMAT_NA; +} + static int intel_pt_process_aux_output_hw_id(struct intel_pt *pt, union perf_event *event, struct perf_sample *sample) @@ -3427,6 +3624,7 @@ static int intel_pt_process_aux_output_hw_id(struct i= ntel_pt *pt, =20 ptq->pebs[hw_id].evsel =3D evsel; ptq->pebs[hw_id].id =3D sample->id; + ptq->pebs[hw_id].data_src_fmt =3D intel_pt_data_src_fmt(pt, evsel); =20 return 0; } @@ -3976,6 +4174,7 @@ static void intel_pt_setup_pebs_events(struct intel_p= t *pt) } pt->single_pebs =3D true; pt->sample_pebs =3D true; + pt->pebs_data_src_fmt =3D intel_pt_data_src_fmt(pt, evsel); pt->pebs_evsel =3D evsel; } } --=20 2.45.2 From nobody Sat Feb 7 18:15:08 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F8E925E459; Mon, 12 May 2025 09:39:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747042790; cv=none; b=Ey1xfb6R3XextgsaUYRXexwxxaNaFg49H4QRXhY2KERzZh+bA6kESX1yCJfecdqJTXbTv9HWPFqvH+j+6blXyuv7jTSuG/wV5QvGUZ49RWpswKnXpF0flF6jvFl2ewh7k3gIYvrDhmk4OeDbSLfLbfTlrag5YzbleJTbbaYfrfc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747042790; c=relaxed/simple; bh=+JPZFrLeHan5qO0lHyWxoXHqqYbfROkWGRmWraQxI0Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HPGIYBD7iFOXJaWR48ihHtZudNDnhW1rGQXXYv7sJ8OpQqp+ap5ESdhM9vS/41J3Je9Cz/hEkdwCax4MRPCRiruInJ2RBcXn+vZ1ZN65PdR26oZH43lu4o4swyJRdl7J4x/bGf+lDUV/DmQRB5cHrU5DJ1RyaWEL5rx7nholsII= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=HKSfHYnF; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="HKSfHYnF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1747042789; x=1778578789; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+JPZFrLeHan5qO0lHyWxoXHqqYbfROkWGRmWraQxI0Q=; b=HKSfHYnFqDgsmu71xkI1iYwlzXJJoLiaaRWLHe3kVo0nhN4XTwkGkxqr fxK8kxr4LY3c9AaHno0MqUW7Q9NA/TYg86HNr4F51yiSNHtg56OpaLgR7 +6XHJCaAC7Oip/1EMRvSyegFY2QIWu6GUaoKdfcRN40TVsORf0vHDZyCd 4Bi89Q9CCVY8e7HRsVutZPhAy19GSW3S2bVffu2TeLdfR7fS7L3yMMklS wdlzz5aI7p58XUT/NrA77GBp1E6oiOlIhb5lGGHgRTJiUe1D+w2VhEafJ ibuIU8sjcGazC+HWwDgqW5krG0FmDmB9xNiNPegLkCWKEZB7ITypDM+vF Q==; X-CSE-ConnectionGUID: 86Y+fkgQRkK7QDxYBl1C5w== X-CSE-MsgGUID: 88JXl+zYS46iQUXCJQyIeg== X-IronPort-AV: E=McAfee;i="6700,10204,11430"; a="36457530" X-IronPort-AV: E=Sophos;i="6.15,281,1739865600"; d="scan'208";a="36457530" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2025 02:39:49 -0700 X-CSE-ConnectionGUID: VXHpmoIzSQqzjl2rhyMMww== X-CSE-MsgGUID: xgyaBwUDTE2oZdfVzNJKeA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,281,1739865600"; d="scan'208";a="142214304" Received: from bvivekan-mobl1.gar.corp.intel.com (HELO localhost.localdomain) ([10.245.245.139]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2025 02:39:46 -0700 From: Adrian Hunter To: Arnaldo Carvalho de Melo , Jiri Olsa , Namhyung Kim Cc: Alexander Shishkin , Ian Rogers , Kan Liang , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Subject: [PATCH 2/3] perf intel-pt: Do not default to recording all switch events Date: Mon, 12 May 2025 12:39:31 +0300 Message-ID: <20250512093932.79854-3-adrian.hunter@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250512093932.79854-1-adrian.hunter@intel.com> References: <20250512093932.79854-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On systems with many CPUs, recording extra context switch events can be excessive and unnecessary. Add perf config intel-pt.all-switch-events=3Dfal= se to control the behaviour. Example: # perf config intel-pt.all-switch-events=3Dfalse # perf record -eintel_pt//u uname Linux [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 0.082 MB perf.data ] # perf script -D | grep PERF_RECORD_SWITCH | awk '{print $5}' | uniq -c 5 PERF_RECORD_SWITCH # perf config intel-pt.all-switch-events=3Dtrue # perf record -eintel_pt//u uname Linux [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 0.102 MB perf.data ] # perf script -D | grep PERF_RECORD_SWITCH | awk '{print $5}' | uniq -c 180 PERF_RECORD_SWITCH_CPU_WIDE Signed-off-by: Adrian Hunter --- tools/perf/Documentation/perf-config.txt | 4 ++++ tools/perf/arch/x86/util/intel-pt.c | 16 +++++++++++++++- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/tools/perf/Documentation/perf-config.txt b/tools/perf/Document= ation/perf-config.txt index 36ebebc875ea..c6f335659667 100644 --- a/tools/perf/Documentation/perf-config.txt +++ b/tools/perf/Documentation/perf-config.txt @@ -708,6 +708,10 @@ intel-pt.*:: the maximum is exceeded there will be a "Never-ending loop" error. The default is 100000. =20 + intel-pt.all-switch-events:: + If the user has permission to do so, always record all context + switch events on all CPUs. + auxtrace.*:: =20 auxtrace.dumpdir:: diff --git a/tools/perf/arch/x86/util/intel-pt.c b/tools/perf/arch/x86/util= /intel-pt.c index 8f235d8b67b6..add33cb5d1da 100644 --- a/tools/perf/arch/x86/util/intel-pt.c +++ b/tools/perf/arch/x86/util/intel-pt.c @@ -19,6 +19,7 @@ #include "../../../util/evlist.h" #include "../../../util/evsel.h" #include "../../../util/evsel_config.h" +#include "../../../util/config.h" #include "../../../util/cpumap.h" #include "../../../util/mmap.h" #include @@ -52,6 +53,7 @@ struct intel_pt_recording { struct perf_pmu *intel_pt_pmu; int have_sched_switch; struct evlist *evlist; + bool all_switch_events; bool snapshot_mode; bool snapshot_init_done; size_t snapshot_size; @@ -794,7 +796,7 @@ static int intel_pt_recording_options(struct auxtrace_r= ecord *itr, bool cpu_wide =3D !target__none(&opts->target) && !target__has_task(&opts->target); =20 - if (!cpu_wide && perf_can_record_cpu_wide()) { + if (ptr->all_switch_events && !cpu_wide && perf_can_record_cpu_wide()) { struct evsel *switch_evsel; =20 switch_evsel =3D evlist__add_dummy_on_all_cpus(evlist); @@ -1178,6 +1180,16 @@ static u64 intel_pt_reference(struct auxtrace_record= *itr __maybe_unused) return rdtsc(); } =20 +static int intel_pt_perf_config(const char *var, const char *value, void *= data) +{ + struct intel_pt_recording *ptr =3D data; + + if (!strcmp(var, "intel-pt.all-switch-events")) + ptr->all_switch_events =3D perf_config_bool(var, value); + + return 0; +} + struct auxtrace_record *intel_pt_recording_init(int *err) { struct perf_pmu *intel_pt_pmu =3D perf_pmus__find(INTEL_PT_PMU_NAME); @@ -1197,6 +1209,8 @@ struct auxtrace_record *intel_pt_recording_init(int *= err) return NULL; } =20 + perf_config(intel_pt_perf_config, ptr); + ptr->intel_pt_pmu =3D intel_pt_pmu; ptr->itr.recording_options =3D intel_pt_recording_options; ptr->itr.info_priv_size =3D intel_pt_info_priv_size; --=20 2.45.2 From nobody Sat Feb 7 18:15:08 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54798261381; Mon, 12 May 2025 09:39:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747042794; cv=none; b=APi2VU6Ihhn0mJlZsL5csXwrN/AlvWkMYH+vVJevXOnqvrK9G17sTgKtrQxn4UmhI19HrJ5HZhQg/cNNHkTUsJ/MC6yI64X4O07FcHaxWpfjvYxT4GdlgFiIKry7ExvfC0yjcGVqjbreuxWMdEiZ6sytRQdw7vansKMYg59/BgU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747042794; c=relaxed/simple; bh=GJ9BKJd2PRiCU2kpbBVN9+TUnj1dNbBrQ3BJhhqTcmo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hySSoV9Ljl6smbiYsojLXibbJyfZ47HIN5sTATmxYHTov6f9jvdLbQbz8szGsQhxF5T7krkuseG+oBgEFF30HlXqJN0SZyAaBrYp4gIW37vK6Z6d5dYkN0X2HsOIlQ7F6cWlCsaKkVqZguzlJNByYclVWQ7uX4KR3soQW/1Z9SU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=XeFACxJy; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="XeFACxJy" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1747042793; x=1778578793; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GJ9BKJd2PRiCU2kpbBVN9+TUnj1dNbBrQ3BJhhqTcmo=; b=XeFACxJy0EQqitCNpi4d3S3y4kgK8F+Q/H8BxPpOb5oNXUt5xCm6fMm7 sT7rcBM8mt8hSIoeHA5trq1p71erwSkPb8zVXA2cJhV5NcK/lpbsyRB+F 4ggYdnMMZeuXiw/m8rjxflp2yrU8OqtPyJiA2hPE+61RPPMyKzXWq090C eBLWYqqvxGzdwqyV+3Z/GirtvVPYjZWC4vdtXgotmr+vZH92/6x4dQLyM j07Sv4oupvcJAH+Ua3uq1AdmH/Ro+j+4n7eFh2il3SMc63220CpzRvzmm 5YgvUKsT7ASLL57gEzMZncZK9iiXaIzTnAWWotcJ5BXsDd49b7c3Sz5Cm A==; X-CSE-ConnectionGUID: hh9bdC7UTcmsSVvWNkiY4w== X-CSE-MsgGUID: NKDoc040Tk2rGsHNemRYug== X-IronPort-AV: E=McAfee;i="6700,10204,11430"; a="36457535" X-IronPort-AV: E=Sophos;i="6.15,281,1739865600"; d="scan'208";a="36457535" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2025 02:39:51 -0700 X-CSE-ConnectionGUID: GOJ8cRRZS6SK52RSkifd1Q== X-CSE-MsgGUID: geiVIFlZTdymWDQZhjZX1g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,281,1739865600"; d="scan'208";a="142214310" Received: from bvivekan-mobl1.gar.corp.intel.com (HELO localhost.localdomain) ([10.245.245.139]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2025 02:39:49 -0700 From: Adrian Hunter To: Arnaldo Carvalho de Melo , Jiri Olsa , Namhyung Kim Cc: Alexander Shishkin , Ian Rogers , Kan Liang , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Subject: [PATCH 3/3] perf scripts python: exported-sql-viewer.py: Fix pattern matching with Python 3 Date: Mon, 12 May 2025 12:39:32 +0300 Message-ID: <20250512093932.79854-4-adrian.hunter@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250512093932.79854-1-adrian.hunter@intel.com> References: <20250512093932.79854-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The script allows the user to enter patterns to find symbols. The pattern matching characters are converted for use in SQL. For PostgreSQL the conversion involves using the Python maketrans() method which is slightly different in Python 3 compared with Python 2. Fix to work in Python 3. Fixes: beda0e725e5f ("perf script python: Add Python3 support to exported-s= ql-viewer.py") Signed-off-by: Adrian Hunter --- tools/perf/scripts/python/exported-sql-viewer.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tools/perf/scripts/python/exported-sql-viewer.py b/tools/perf/= scripts/python/exported-sql-viewer.py index 121cf61ba1b3..e0b2e7268ef6 100755 --- a/tools/perf/scripts/python/exported-sql-viewer.py +++ b/tools/perf/scripts/python/exported-sql-viewer.py @@ -680,7 +680,10 @@ class CallGraphModelBase(TreeModel): s =3D value.replace("%", "\\%") s =3D s.replace("_", "\\_") # Translate * and ? into SQL LIKE pattern characters % and _ - trans =3D string.maketrans("*?", "%_") + if sys.version_info[0] =3D=3D 3: + trans =3D str.maketrans("*?", "%_") + else: + trans =3D string.maketrans("*?", "%_") match =3D " LIKE '" + str(s).translate(trans) + "'" else: match =3D " GLOB '" + str(value) + "'" --=20 2.45.2