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To: , , , , CC: , , , , , , , , Mohan Kumar D , Sheetal Subject: [PATCH 3/3] ALSA: hda/tegra: Add Tegra264 support Date: Mon, 12 May 2025 06:42:58 +0000 Message-ID: <20250512064258.1028331-4-sheetal@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250512064258.1028331-1-sheetal@nvidia.com> References: <20250512064258.1028331-1-sheetal@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003446:EE_|PH8PR12MB7136:EE_ X-MS-Office365-Filtering-Correlation-Id: eb53fce9-b24e-46d8-daa6-08dd91204e30 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Jy4avTdDfHhEYRtStWJ2bX4Sw5lQOR/I3U1CNotSYJXM5ehvrqwXfdy2kaI1?= =?us-ascii?Q?RSlawRo8X5odf7aapO6DuNzTe3krmE4O/PVPbwHCdvTWiU/jvYMUyEg5NUvw?= =?us-ascii?Q?GNvpBjaBmjU3Jeq2DTJ8m+JqRDlnk+YHICv8WbdwW7cJIB+t/nuVRV65/y8+?= =?us-ascii?Q?HmTx0sQU1uT/n2tSvOECUFBkrM2vTPDPWLGV3W1qMETZqETBRmHybRWQ8Foi?= =?us-ascii?Q?rtOUVvusWT29nbHjuIQjLNGwv1ucZUrXXLyDG8GcNEJCQ126m/5yPXMUDNem?= =?us-ascii?Q?xI//sNh6Zz0IPTs5jH/g4d8Sx01SQQ0754ZKGMNLoJZ5X1vCTXA5NgJSuIDU?= =?us-ascii?Q?8llqujUNx5BqnMsjyLiuPwqI0waObZx3ZJGtPP3w8m5WynJgk5gbyzRERuqf?= =?us-ascii?Q?4r0gWCr5Nye2rNZJMiIiG0swlZMSM72tbDCZL2GxYz7rts3TVBPYd4mJwNOh?= =?us-ascii?Q?VtDRLglqC749Ckchi7dz+Pe+jCGfuW7GDun5arcURQHgj4ZrogE1HHPffGYU?= =?us-ascii?Q?nIs6q99+0ycZaa34KtztstpN3Gq4z5caPFdk+SQa3eb37DqgfN1kl50bhwVv?= =?us-ascii?Q?GLYIOaHmm221nfig87BQlzHNmOm3T7MP6CdqsKurYdPsOVbXjwAzVhrKN0EV?= =?us-ascii?Q?F8VRmqbg2ImFIzybnCoa9A/AkbOGp76jDn+CpVL2zM6SquWIEvOVJLy+6fLA?= =?us-ascii?Q?j9TWVx8XmVXXsO+DO9UbB83ZvOO9VfYPO9YO3X/SG32WMYQoAu9jdbbdJqBb?= =?us-ascii?Q?2ZeC84+rLu2pxVJMLsOlmSWAdCNxSNp8gEFDauPXWtrYU+2CUtvkCpGbx3I4?= =?us-ascii?Q?xWaz22mjZDoU/dyFjQQeU+lcOYU3IdduOEXGizpHgJ6eVnTDdfPZ/6Gxqf3k?= =?us-ascii?Q?ngP0IPHY3ZS4KL5GeeNl2CSNi0GDDXxJy1fv3ayqMEUClpxiccwF4B5MUcPv?= =?us-ascii?Q?ld+aG04B8nkrBQcg+e3GbXryjXbHU7DtoRop1nSiKDVrO5DA0hHChCwFwtZ7?= =?us-ascii?Q?HlQk3CpQJTQg6b/uTHgV1vpioyDqziFxrmGMca1yzbU3+duElnqyx5jIwx58?= =?us-ascii?Q?PFDutBnoJ6Y6CWL3Xu2b9XQ/01CUcO3cV4ngbwyzlIhNrTeqyowjMkFMd/U5?= =?us-ascii?Q?aHO3j690o/nIDfGIyNlOMQ/xEZmBeCtHuZ62uMWpsqwW+D7E0bGcXlDsSFTX?= =?us-ascii?Q?9Vo5N/7uzypSa9iBfBAl1jfiOwkBFLihngO+h8TjAOZLrHOMG1XuOzfHy1t5?= =?us-ascii?Q?sKFipYlv067f/KdXTZFD1/CpUCxNwJW59Z1KPES0b3Q9oVgVe1gY8o+ia6aV?= =?us-ascii?Q?7yFLCB30x96kVaLMLWEeEngnllQrg5g6VYjreJO4FVSNb00HL9fY0kXvJqax?= =?us-ascii?Q?BmllYrMq+BVeIEosL6aU/yQUaYcetC9otsKy20Ak3fhaufagDZt6upWyvoqR?= =?us-ascii?Q?yDGVBGadLcwuwFmmw/qIJ1qsyvwIhVmm0k+S7H6DpwlfkpYp+StjaY4NwIH2?= =?us-ascii?Q?V2vQt60qCCXobe1s1MTPl/ghKnvraKS6rYDc?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2025 06:43:29.1937 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eb53fce9-b24e-46d8-daa6-08dd91204e30 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003446.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7136 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Mohan Kumar D Update HDA driver to support Tegra264 differences from legacy HDA, which includes: clocks/resets, always power on, and hardware-managed FPCI/IPFS initialization. The driver retrieves this chip-specific information from soc_data. Signed-off-by: Mohan Kumar D Signed-off-by: Sheetal --- sound/pci/hda/hda_tegra.c | 51 +++++++++++++++++++++++++++++++++----- sound/pci/hda/patch_hdmi.c | 1 + 2 files changed, 46 insertions(+), 6 deletions(-) diff --git a/sound/pci/hda/hda_tegra.c b/sound/pci/hda/hda_tegra.c index a590d431c5ff..8c0dd439f5a5 100644 --- a/sound/pci/hda/hda_tegra.c +++ b/sound/pci/hda/hda_tegra.c @@ -72,6 +72,10 @@ struct hda_tegra_soc { bool has_hda2codec_2x_reset; bool has_hda2hdmi; + bool has_hda2codec_2x; + bool input_stream; + bool always_on; + bool requires_init; }; =20 struct hda_tegra { @@ -187,7 +191,9 @@ static int hda_tegra_runtime_resume(struct device *dev) if (rc !=3D 0) return rc; if (chip->running) { - hda_tegra_init(hda); + if (hda->soc->requires_init) + hda_tegra_init(hda); + azx_init_chip(chip, 1); /* disable controller wake up event*/ azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & @@ -250,7 +256,8 @@ static int hda_tegra_init_chip(struct azx *chip, struct= platform_device *pdev) bus->remap_addr =3D hda->regs + HDA_BAR0; bus->addr =3D res->start + HDA_BAR0; =20 - hda_tegra_init(hda); + if (hda->soc->requires_init) + hda_tegra_init(hda); =20 return 0; } @@ -323,7 +330,7 @@ static int hda_tegra_first_init(struct azx *chip, struc= t platform_device *pdev) * starts with offset 0 which is wrong as HW register for output stream * offset starts with 4. */ - if (of_device_is_compatible(np, "nvidia,tegra234-hda")) + if (!hda->soc->input_stream) chip->capture_streams =3D 4; =20 chip->playback_streams =3D (gcap >> 12) & 0x0f; @@ -419,7 +426,6 @@ static int hda_tegra_create(struct snd_card *card, chip->driver_caps =3D driver_caps; chip->driver_type =3D driver_caps & 0xff; chip->dev_index =3D 0; - chip->jackpoll_interval =3D msecs_to_jiffies(5000); INIT_LIST_HEAD(&chip->pcm_list); =20 chip->codec_probe_mask =3D -1; @@ -436,7 +442,16 @@ static int hda_tegra_create(struct snd_card *card, chip->bus.core.sync_write =3D 0; chip->bus.core.needs_damn_long_delay =3D 1; chip->bus.core.aligned_mmio =3D 1; - chip->bus.jackpoll_in_suspend =3D 1; + + /* + * HDA power domain and clocks are always on for Tegra264 and + * the jack detection logic would work always, so no need of + * jack polling mechanism running. + */ + if (!hda->soc->always_on) { + chip->jackpoll_interval =3D msecs_to_jiffies(5000); + chip->bus.jackpoll_in_suspend =3D 1; + } =20 err =3D snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); if (err < 0) { @@ -450,22 +465,44 @@ static int hda_tegra_create(struct snd_card *card, static const struct hda_tegra_soc tegra30_data =3D { .has_hda2codec_2x_reset =3D true, .has_hda2hdmi =3D true, + .has_hda2codec_2x =3D true, + .input_stream =3D true, + .always_on =3D false, + .requires_init =3D true, }; =20 static const struct hda_tegra_soc tegra194_data =3D { .has_hda2codec_2x_reset =3D false, .has_hda2hdmi =3D true, + .has_hda2codec_2x =3D true, + .input_stream =3D true, + .always_on =3D false, + .requires_init =3D true, }; =20 static const struct hda_tegra_soc tegra234_data =3D { .has_hda2codec_2x_reset =3D true, .has_hda2hdmi =3D false, + .has_hda2codec_2x =3D true, + .input_stream =3D false, + .always_on =3D false, + .requires_init =3D true, +}; + +static const struct hda_tegra_soc tegra264_data =3D { + .has_hda2codec_2x_reset =3D true, + .has_hda2hdmi =3D false, + .has_hda2codec_2x =3D false, + .input_stream =3D false, + .always_on =3D true, + .requires_init =3D false, }; =20 static const struct of_device_id hda_tegra_match[] =3D { { .compatible =3D "nvidia,tegra30-hda", .data =3D &tegra30_data }, { .compatible =3D "nvidia,tegra194-hda", .data =3D &tegra194_data }, { .compatible =3D "nvidia,tegra234-hda", .data =3D &tegra234_data }, + { .compatible =3D "nvidia,tegra264-hda", .data =3D &tegra264_data }, {}, }; MODULE_DEVICE_TABLE(of, hda_tegra_match); @@ -520,7 +557,9 @@ static int hda_tegra_probe(struct platform_device *pdev) hda->clocks[hda->nclocks++].id =3D "hda"; if (hda->soc->has_hda2hdmi) hda->clocks[hda->nclocks++].id =3D "hda2hdmi"; - hda->clocks[hda->nclocks++].id =3D "hda2codec_2x"; + + if (hda->soc->has_hda2codec_2x) + hda->clocks[hda->nclocks++].id =3D "hda2codec_2x"; =20 err =3D devm_clk_bulk_get(&pdev->dev, hda->nclocks, hda->clocks); if (err < 0) diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c index 7167989a8d86..6c860fda6648 100644 --- a/sound/pci/hda/patch_hdmi.c +++ b/sound/pci/hda/patch_hdmi.c @@ -4551,6 +4551,7 @@ HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patc= h_tegra_hdmi), HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi), HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi), HDA_CODEC_ENTRY(0x10de0031, "Tegra234 HDMI/DP", patch_tegra234_hdmi), +HDA_CODEC_ENTRY(0x10de0034, "Tegra264 HDMI/DP", patch_tegra234_hdmi), HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), --=20 2.17.1